mirror of
https://github.com/bminor/binutils-gdb.git
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1d506c26d9
This commit is the result of the following actions:
- Running gdb/copyright.py to update all of the copyright headers to
include 2024,
- Manually updating a few files the copyright.py script told me to
update, these files had copyright headers embedded within the
file,
- Regenerating gdbsupport/Makefile.in to refresh it's copyright
date,
- Using grep to find other files that still mentioned 2023. If
these files were updated last year from 2022 to 2023 then I've
updated them this year to 2024.
I'm sure I've probably missed some dates. Feel free to fix them up as
you spot them.
343 lines
8.8 KiB
C
343 lines
8.8 KiB
C
/* Copyright (C) 2009-2024 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "gdbsupport/common-defs.h"
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#include "nat/gdb_ptrace.h"
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#include "mips-linux-watch.h"
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/* Assuming usable watch registers REGS, return the irw_mask of
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register N. */
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uint32_t
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mips_linux_watch_get_irw_mask (struct pt_watch_regs *regs, int n)
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{
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switch (regs->style)
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{
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case pt_watch_style_mips32:
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return regs->mips32.watch_masks[n] & IRW_MASK;
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case pt_watch_style_mips64:
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return regs->mips64.watch_masks[n] & IRW_MASK;
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default:
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internal_error (_("Unrecognized watch register style"));
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}
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}
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/* Assuming usable watch registers REGS, return the reg_mask of
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register N. */
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static uint32_t
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get_reg_mask (struct pt_watch_regs *regs, int n)
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{
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switch (regs->style)
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{
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case pt_watch_style_mips32:
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return regs->mips32.watch_masks[n] & ~IRW_MASK;
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case pt_watch_style_mips64:
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return regs->mips64.watch_masks[n] & ~IRW_MASK;
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default:
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internal_error (_("Unrecognized watch register style"));
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}
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}
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/* Assuming usable watch registers REGS, return the num_valid. */
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uint32_t
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mips_linux_watch_get_num_valid (struct pt_watch_regs *regs)
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{
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switch (regs->style)
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{
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case pt_watch_style_mips32:
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return regs->mips32.num_valid;
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case pt_watch_style_mips64:
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return regs->mips64.num_valid;
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default:
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internal_error (_("Unrecognized watch register style"));
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}
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}
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/* Assuming usable watch registers REGS, return the watchlo of
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register N. */
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CORE_ADDR
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mips_linux_watch_get_watchlo (struct pt_watch_regs *regs, int n)
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{
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switch (regs->style)
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{
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case pt_watch_style_mips32:
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return regs->mips32.watchlo[n];
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case pt_watch_style_mips64:
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return regs->mips64.watchlo[n];
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default:
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internal_error (_("Unrecognized watch register style"));
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}
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}
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/* Assuming usable watch registers REGS, set watchlo of register N to
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VALUE. */
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void
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mips_linux_watch_set_watchlo (struct pt_watch_regs *regs, int n,
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CORE_ADDR value)
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{
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switch (regs->style)
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{
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case pt_watch_style_mips32:
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/* The cast will never throw away bits as 64 bit addresses can
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never be used on a 32 bit kernel. */
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regs->mips32.watchlo[n] = (uint32_t) value;
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break;
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case pt_watch_style_mips64:
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regs->mips64.watchlo[n] = value;
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break;
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default:
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internal_error (_("Unrecognized watch register style"));
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}
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}
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/* Assuming usable watch registers REGS, return the watchhi of
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register N. */
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uint32_t
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mips_linux_watch_get_watchhi (struct pt_watch_regs *regs, int n)
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{
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switch (regs->style)
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{
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case pt_watch_style_mips32:
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return regs->mips32.watchhi[n];
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case pt_watch_style_mips64:
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return regs->mips64.watchhi[n];
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default:
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internal_error (_("Unrecognized watch register style"));
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}
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}
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/* Assuming usable watch registers REGS, set watchhi of register N to
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VALUE. */
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void
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mips_linux_watch_set_watchhi (struct pt_watch_regs *regs, int n,
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uint16_t value)
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{
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switch (regs->style)
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{
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case pt_watch_style_mips32:
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regs->mips32.watchhi[n] = value;
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break;
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case pt_watch_style_mips64:
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regs->mips64.watchhi[n] = value;
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break;
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default:
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internal_error (_("Unrecognized watch register style"));
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}
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}
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/* Read the watch registers of process LWPID and store it in
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WATCH_READBACK. Save true to *WATCH_READBACK_VALID if watch
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registers are valid. Return 1 if watch registers are usable.
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Cached information is used unless FORCE is true. */
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int
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mips_linux_read_watch_registers (long lwpid,
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struct pt_watch_regs *watch_readback,
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int *watch_readback_valid, int force)
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{
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if (force || *watch_readback_valid == 0)
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{
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if (ptrace (PTRACE_GET_WATCH_REGS, lwpid, watch_readback, NULL) == -1)
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{
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*watch_readback_valid = -1;
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return 0;
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}
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switch (watch_readback->style)
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{
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case pt_watch_style_mips32:
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if (watch_readback->mips32.num_valid == 0)
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{
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*watch_readback_valid = -1;
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return 0;
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}
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break;
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case pt_watch_style_mips64:
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if (watch_readback->mips64.num_valid == 0)
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{
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*watch_readback_valid = -1;
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return 0;
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}
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break;
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default:
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*watch_readback_valid = -1;
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return 0;
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}
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/* Watch registers appear to be usable. */
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*watch_readback_valid = 1;
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}
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return (*watch_readback_valid == 1) ? 1 : 0;
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}
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/* Convert GDB's TYPE to an IRW mask. */
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uint32_t
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mips_linux_watch_type_to_irw (enum target_hw_bp_type type)
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{
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switch (type)
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{
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case hw_write:
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return W_MASK;
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case hw_read:
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return R_MASK;
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case hw_access:
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return (W_MASK | R_MASK);
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default:
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return 0;
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}
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}
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/* Set any low order bits in MASK that are not set. */
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static CORE_ADDR
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fill_mask (CORE_ADDR mask)
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{
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CORE_ADDR f = 1;
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while (f && f < mask)
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{
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mask |= f;
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f <<= 1;
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}
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return mask;
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}
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/* Try to add a single watch to the specified registers REGS. The
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address of added watch is ADDR, the length is LEN, and the mask
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is IRW. Return 1 on success, 0 on failure. */
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int
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mips_linux_watch_try_one_watch (struct pt_watch_regs *regs,
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CORE_ADDR addr, int len, uint32_t irw)
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{
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CORE_ADDR base_addr, last_byte, break_addr, segment_len;
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CORE_ADDR mask_bits, t_low;
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uint16_t t_hi;
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int i, free_watches;
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struct pt_watch_regs regs_copy;
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if (len <= 0)
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return 0;
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last_byte = addr + len - 1;
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mask_bits = fill_mask (addr ^ last_byte) | IRW_MASK;
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base_addr = addr & ~mask_bits;
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/* Check to see if it is covered by current registers. */
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for (i = 0; i < mips_linux_watch_get_num_valid (regs); i++)
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{
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t_low = mips_linux_watch_get_watchlo (regs, i);
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if (t_low != 0 && irw == ((uint32_t) t_low & irw))
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{
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t_hi = mips_linux_watch_get_watchhi (regs, i) | IRW_MASK;
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t_low &= ~(CORE_ADDR) t_hi;
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if (addr >= t_low && last_byte <= (t_low + t_hi))
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return 1;
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}
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}
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/* Try to find an empty register. */
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free_watches = 0;
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for (i = 0; i < mips_linux_watch_get_num_valid (regs); i++)
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{
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t_low = mips_linux_watch_get_watchlo (regs, i);
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if (t_low == 0
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&& irw == (mips_linux_watch_get_irw_mask (regs, i) & irw))
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{
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if (mask_bits <= (get_reg_mask (regs, i) | IRW_MASK))
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{
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/* It fits, we'll take it. */
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mips_linux_watch_set_watchlo (regs, i, base_addr | irw);
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mips_linux_watch_set_watchhi (regs, i, mask_bits & ~IRW_MASK);
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return 1;
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}
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else
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{
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/* It doesn't fit, but has the proper IRW capabilities. */
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free_watches++;
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}
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}
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}
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if (free_watches > 1)
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{
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/* Try to split it across several registers. */
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regs_copy = *regs;
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for (i = 0; i < mips_linux_watch_get_num_valid (®s_copy); i++)
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{
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t_low = mips_linux_watch_get_watchlo (®s_copy, i);
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t_hi = get_reg_mask (®s_copy, i) | IRW_MASK;
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if (t_low == 0 && irw == (t_hi & irw))
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{
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t_low = addr & ~(CORE_ADDR) t_hi;
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break_addr = t_low + t_hi + 1;
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if (break_addr >= addr + len)
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segment_len = len;
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else
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segment_len = break_addr - addr;
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mask_bits = fill_mask (addr ^ (addr + segment_len - 1));
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mips_linux_watch_set_watchlo (®s_copy, i,
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(addr & ~mask_bits) | irw);
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mips_linux_watch_set_watchhi (®s_copy, i,
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mask_bits & ~IRW_MASK);
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if (break_addr >= addr + len)
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{
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*regs = regs_copy;
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return 1;
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}
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len = addr + len - break_addr;
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addr = break_addr;
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}
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}
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}
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/* It didn't fit anywhere, we failed. */
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return 0;
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}
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/* Fill in the watch registers REGS with the currently cached
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watches CURRENT_WATCHES. */
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void
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mips_linux_watch_populate_regs (struct mips_watchpoint *current_watches,
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struct pt_watch_regs *regs)
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{
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struct mips_watchpoint *w;
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int i;
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/* Clear them out. */
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for (i = 0; i < mips_linux_watch_get_num_valid (regs); i++)
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{
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mips_linux_watch_set_watchlo (regs, i, 0);
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mips_linux_watch_set_watchhi (regs, i, 0);
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}
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w = current_watches;
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while (w)
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{
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uint32_t irw = mips_linux_watch_type_to_irw (w->type);
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i = mips_linux_watch_try_one_watch (regs, w->addr, w->len, irw);
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/* They must all fit, because we previously calculated that they
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would. */
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gdb_assert (i);
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w = w->next;
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}
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}
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