mirror of
https://github.com/bminor/binutils-gdb.git
synced 2025-12-11 10:03:29 +00:00
1d506c26d9
This commit is the result of the following actions:
- Running gdb/copyright.py to update all of the copyright headers to
include 2024,
- Manually updating a few files the copyright.py script told me to
update, these files had copyright headers embedded within the
file,
- Regenerating gdbsupport/Makefile.in to refresh it's copyright
date,
- Using grep to find other files that still mentioned 2023. If
these files were updated last year from 2022 to 2023 then I've
updated them this year to 2024.
I'm sure I've probably missed some dates. Feel free to fix them up as
you spot them.
465 lines
10 KiB
C
465 lines
10 KiB
C
/* Common target dependent code for GDB on ARM systems.
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Copyright (C) 1988-2024 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "gdbsupport/common-defs.h"
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#include "gdbsupport/common-regcache.h"
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#include "arm.h"
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#include "../features/arm/arm-core.c"
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#include "../features/arm/arm-tls.c"
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#include "../features/arm/arm-vfpv2.c"
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#include "../features/arm/arm-vfpv3.c"
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#include "../features/arm/xscale-iwmmxt.c"
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#include "../features/arm/arm-m-profile.c"
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#include "../features/arm/arm-m-profile-with-fpa.c"
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#include "../features/arm/arm-m-profile-mve.c"
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#include "../features/arm/arm-m-system.c"
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/* See arm.h. */
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int
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thumb_insn_size (unsigned short inst1)
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{
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if ((inst1 & 0xe000) == 0xe000 && (inst1 & 0x1800) != 0)
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return 4;
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else
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return 2;
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}
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/* See arm.h. */
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int
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condition_true (unsigned long cond, unsigned long status_reg)
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{
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if (cond == INST_AL || cond == INST_NV)
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return 1;
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switch (cond)
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{
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case INST_EQ:
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return ((status_reg & FLAG_Z) != 0);
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case INST_NE:
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return ((status_reg & FLAG_Z) == 0);
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case INST_CS:
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return ((status_reg & FLAG_C) != 0);
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case INST_CC:
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return ((status_reg & FLAG_C) == 0);
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case INST_MI:
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return ((status_reg & FLAG_N) != 0);
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case INST_PL:
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return ((status_reg & FLAG_N) == 0);
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case INST_VS:
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return ((status_reg & FLAG_V) != 0);
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case INST_VC:
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return ((status_reg & FLAG_V) == 0);
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case INST_HI:
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return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
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case INST_LS:
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return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
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case INST_GE:
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return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
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case INST_LT:
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return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
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case INST_GT:
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return (((status_reg & FLAG_Z) == 0)
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&& (((status_reg & FLAG_N) == 0)
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== ((status_reg & FLAG_V) == 0)));
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case INST_LE:
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return (((status_reg & FLAG_Z) != 0)
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|| (((status_reg & FLAG_N) == 0)
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!= ((status_reg & FLAG_V) == 0)));
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}
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return 1;
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}
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/* See arm.h. */
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int
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thumb_advance_itstate (unsigned int itstate)
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{
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/* Preserve IT[7:5], the first three bits of the condition. Shift
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the upcoming condition flags left by one bit. */
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itstate = (itstate & 0xe0) | ((itstate << 1) & 0x1f);
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/* If we have finished the IT block, clear the state. */
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if ((itstate & 0x0f) == 0)
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itstate = 0;
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return itstate;
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}
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/* See arm.h. */
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int
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arm_instruction_changes_pc (uint32_t this_instr)
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{
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if (bits (this_instr, 28, 31) == INST_NV)
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/* Unconditional instructions. */
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switch (bits (this_instr, 24, 27))
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{
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case 0xa:
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case 0xb:
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/* Branch with Link and change to Thumb. */
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return 1;
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case 0xc:
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case 0xd:
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case 0xe:
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/* Coprocessor register transfer. */
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if (bits (this_instr, 12, 15) == 15)
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error (_("Invalid update to pc in instruction"));
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return 0;
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default:
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return 0;
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}
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else
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switch (bits (this_instr, 25, 27))
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{
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case 0x0:
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if (bits (this_instr, 23, 24) == 2 && bit (this_instr, 20) == 0)
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{
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/* Multiplies and extra load/stores. */
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if (bit (this_instr, 4) == 1 && bit (this_instr, 7) == 1)
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/* Neither multiplies nor extension load/stores are allowed
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to modify PC. */
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return 0;
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/* Otherwise, miscellaneous instructions. */
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/* BX <reg>, BXJ <reg>, BLX <reg> */
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if (bits (this_instr, 4, 27) == 0x12fff1
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|| bits (this_instr, 4, 27) == 0x12fff2
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|| bits (this_instr, 4, 27) == 0x12fff3)
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return 1;
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/* Other miscellaneous instructions are unpredictable if they
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modify PC. */
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return 0;
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}
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/* Data processing instruction. */
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[[fallthrough]];
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case 0x1:
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if (bits (this_instr, 12, 15) == 15)
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return 1;
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else
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return 0;
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case 0x2:
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case 0x3:
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/* Media instructions and architecturally undefined instructions. */
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if (bits (this_instr, 25, 27) == 3 && bit (this_instr, 4) == 1)
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return 0;
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/* Stores. */
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if (bit (this_instr, 20) == 0)
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return 0;
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/* Loads. */
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if (bits (this_instr, 12, 15) == ARM_PC_REGNUM)
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return 1;
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else
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return 0;
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case 0x4:
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/* Load/store multiple. */
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if (bit (this_instr, 20) == 1 && bit (this_instr, 15) == 1)
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return 1;
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else
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return 0;
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case 0x5:
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/* Branch and branch with link. */
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return 1;
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case 0x6:
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case 0x7:
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/* Coprocessor transfers or SWIs can not affect PC. */
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return 0;
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default:
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internal_error (_("bad value in switch"));
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}
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}
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/* See arm.h. */
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int
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thumb_instruction_changes_pc (unsigned short inst)
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{
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if ((inst & 0xff00) == 0xbd00) /* pop {rlist, pc} */
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return 1;
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if ((inst & 0xf000) == 0xd000) /* conditional branch */
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return 1;
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if ((inst & 0xf800) == 0xe000) /* unconditional branch */
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return 1;
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if ((inst & 0xff00) == 0x4700) /* bx REG, blx REG */
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return 1;
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if ((inst & 0xff87) == 0x4687) /* mov pc, REG */
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return 1;
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if ((inst & 0xf500) == 0xb100) /* CBNZ or CBZ. */
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return 1;
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return 0;
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}
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/* See arm.h. */
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int
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thumb2_instruction_changes_pc (unsigned short inst1, unsigned short inst2)
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{
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if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000)
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{
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/* Branches and miscellaneous control instructions. */
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if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000)
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{
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/* B, BL, BLX. */
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return 1;
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}
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else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00)
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{
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/* SUBS PC, LR, #imm8. */
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return 1;
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}
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else if ((inst2 & 0xd000) == 0x8000 && (inst1 & 0x0380) != 0x0380)
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{
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/* Conditional branch. */
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return 1;
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}
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return 0;
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}
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if ((inst1 & 0xfe50) == 0xe810)
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{
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/* Load multiple or RFE. */
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if (bit (inst1, 7) && !bit (inst1, 8))
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{
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/* LDMIA or POP */
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if (bit (inst2, 15))
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return 1;
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}
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else if (!bit (inst1, 7) && bit (inst1, 8))
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{
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/* LDMDB */
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if (bit (inst2, 15))
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return 1;
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}
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else if (bit (inst1, 7) && bit (inst1, 8))
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{
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/* RFEIA */
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return 1;
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}
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else if (!bit (inst1, 7) && !bit (inst1, 8))
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{
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/* RFEDB */
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return 1;
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}
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return 0;
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}
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if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00)
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{
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/* MOV PC or MOVS PC. */
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return 1;
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}
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if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000)
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{
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/* LDR PC. */
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if (bits (inst1, 0, 3) == 15)
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return 1;
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if (bit (inst1, 7))
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return 1;
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if (bit (inst2, 11))
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return 1;
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if ((inst2 & 0x0fc0) == 0x0000)
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return 1;
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return 0;
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}
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if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000)
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{
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/* TBB. */
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return 1;
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}
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if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010)
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{
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/* TBH. */
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return 1;
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}
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return 0;
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}
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/* See arm.h. */
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unsigned long
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shifted_reg_val (reg_buffer_common *regcache, unsigned long inst,
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int carry, unsigned long pc_val, unsigned long status_reg)
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{
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unsigned long res, shift;
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int rm = bits (inst, 0, 3);
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unsigned long shifttype = bits (inst, 5, 6);
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if (bit (inst, 4))
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{
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int rs = bits (inst, 8, 11);
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shift = (rs == 15
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? pc_val + 8
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: regcache_raw_get_unsigned (regcache, rs)) & 0xFF;
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}
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else
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shift = bits (inst, 7, 11);
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res = (rm == ARM_PC_REGNUM
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? (pc_val + (bit (inst, 4) ? 12 : 8))
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: regcache_raw_get_unsigned (regcache, rm));
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switch (shifttype)
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{
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case 0: /* LSL */
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res = shift >= 32 ? 0 : res << shift;
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break;
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case 1: /* LSR */
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res = shift >= 32 ? 0 : res >> shift;
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break;
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case 2: /* ASR */
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if (shift >= 32)
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shift = 31;
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res = ((res & 0x80000000L)
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? ~((~res) >> shift) : res >> shift);
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break;
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case 3: /* ROR/RRX */
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shift &= 31;
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if (shift == 0)
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res = (res >> 1) | (carry ? 0x80000000L : 0);
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else
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res = (res >> shift) | (res << (32 - shift));
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break;
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}
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return res & 0xffffffff;
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}
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/* See arch/arm.h. */
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target_desc *
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arm_create_target_description (arm_fp_type fp_type, bool tls)
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{
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target_desc_up tdesc = allocate_target_description ();
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#ifndef IN_PROCESS_AGENT
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if (fp_type == ARM_FP_TYPE_IWMMXT)
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set_tdesc_architecture (tdesc.get (), "iwmmxt");
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else
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set_tdesc_architecture (tdesc.get (), "arm");
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#endif
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long regnum = 0;
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regnum = create_feature_arm_arm_core (tdesc.get (), regnum);
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switch (fp_type)
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{
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case ARM_FP_TYPE_NONE:
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break;
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case ARM_FP_TYPE_VFPV2:
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regnum = create_feature_arm_arm_vfpv2 (tdesc.get (), regnum);
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break;
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case ARM_FP_TYPE_VFPV3:
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regnum = create_feature_arm_arm_vfpv3 (tdesc.get (), regnum);
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break;
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case ARM_FP_TYPE_IWMMXT:
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regnum = create_feature_arm_xscale_iwmmxt (tdesc.get (), regnum);
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break;
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default:
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error (_("Invalid Arm FP type: %d"), fp_type);
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}
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if (tls)
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regnum = create_feature_arm_arm_tls (tdesc.get (), regnum);
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return tdesc.release ();
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}
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/* See arch/arm.h. */
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target_desc *
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arm_create_mprofile_target_description (arm_m_profile_type m_type)
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{
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target_desc *tdesc = allocate_target_description ().release ();
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#ifndef IN_PROCESS_AGENT
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set_tdesc_architecture (tdesc, "arm");
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#endif
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long regnum = 0;
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switch (m_type)
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{
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case ARM_M_TYPE_M_PROFILE:
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regnum = create_feature_arm_arm_m_profile (tdesc, regnum);
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break;
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case ARM_M_TYPE_VFP_D16:
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regnum = create_feature_arm_arm_m_profile (tdesc, regnum);
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regnum = create_feature_arm_arm_vfpv2 (tdesc, regnum);
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break;
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case ARM_M_TYPE_WITH_FPA:
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regnum = create_feature_arm_arm_m_profile_with_fpa (tdesc, regnum);
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break;
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case ARM_M_TYPE_MVE:
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regnum = create_feature_arm_arm_m_profile (tdesc, regnum);
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regnum = create_feature_arm_arm_vfpv2 (tdesc, regnum);
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regnum = create_feature_arm_arm_m_profile_mve (tdesc, regnum);
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break;
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case ARM_M_TYPE_SYSTEM:
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regnum = create_feature_arm_arm_m_profile (tdesc, regnum);
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regnum = create_feature_arm_arm_m_system (tdesc, regnum);
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break;
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default:
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error (_("Invalid Arm M type: %d"), m_type);
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}
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return tdesc;
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}
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