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8edca81ece5df534c1cdd1f8362e7b5b9b090cfa
binutils-gdb/include/opcode
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Przemyslaw Wirkus 8edca81ece aarch64: Limit Rt register number for LS64 load/store instructions 
Atomic 64-byte load/store instructions limit Rt register number to
values matching below condition (register <Xt> number must be even
and <= 22):

    if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED;

This patch adds check if Rt fulfills above requirement.

For more details regarding atomic 64-byte load/store instruction for
Armv8.7 please refer to Arm A64 Instruction set documentation for
Armv8-A architecture profile, see document page 157 for load
instruction, and pages 414-418 for store instructions of [0].

    [0]: https://developer.arm.com/docs/ddi0596/i
2020-11-09 11:19:44 +00:00
..
aarch64.h
aarch64: Limit Rt register number for LS64 load/store instructions
2020-11-09 11:19:44 +00:00
alpha.h
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2020-01-01 18:42:54 +10:30
arc-attrs.h
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2020-01-01 18:42:54 +10:30
arc-func.h
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2020-01-01 18:42:54 +10:30
arc.h
[ARC] Add finer details for LLOCK and SCOND
2020-01-07 15:25:34 +02:00
arm.h
Fix the ARM assembler to generate a Realtime profile for armv8-r.
2020-05-19 12:45:42 +01:00
avr.h
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2020-01-01 18:42:54 +10:30
bfin.h
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2020-01-01 18:42:54 +10:30
cgen.h
opcodes: discriminate endianness and insn-endianness in CGEN ports
2020-06-04 16:17:42 +02:00
ChangeLog-0415
binutils ChangeLog rotation
2016-01-01 22:59:17 +10:30
ChangeLog-9103
Add copyright notices
2012-12-10 12:48:03 +00:00
convex.h
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2020-01-01 18:42:54 +10:30
cr16.h
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cris.h
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crx.h
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2020-01-01 18:42:54 +10:30
csky.h
CSKY: Add version flag in eflag and fix bug in disassembling register.
2020-10-26 16:20:10 +08:00
d10v.h
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2020-01-01 18:42:54 +10:30
d30v.h
ubsan: d30v: negation of -2147483648
2020-02-04 14:10:40 +10:30
dlx.h
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2020-01-01 18:42:54 +10:30
ft32.h
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h8300.h
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hppa.h
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i386.h
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ia64.h
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m68hc11.h
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m68k.h
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metag.h
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mips.h
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mmix.h
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mn10200.h
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mn10300.h
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moxie.h
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msp430-decode.h
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2020-01-01 18:42:54 +10:30
msp430.h
MSP430: Fix relocation overflow when using #lo(EXP) macro
2020-01-15 13:23:06 +00:00
nds32.h
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2020-01-01 18:42:54 +10:30
nfp.h
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nios2.h
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nios2r1.h
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nios2r2.h
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np1.h
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ns32k.h
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pdp11.h
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pj.h
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pn.h
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2020-01-01 18:42:54 +10:30
ppc.h
Power10 Reduced precision outer product operations
2020-05-11 21:08:37 +09:30
pru.h
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2020-01-01 18:42:54 +10:30
pyr.h
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2020-01-01 18:42:54 +10:30
riscv-opc.h
RISC-V: Support debug and float CSR as the unprivileged ones.
2020-06-30 09:54:55 +08:00
riscv.h
PR26493 UBSAN: elfnn-riscv.c left shift of negative value
2020-08-31 20:28:10 +09:30
rl78.h
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2020-01-01 18:42:54 +10:30
rx.h
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2020-01-01 18:42:54 +10:30
s12z.h
Enable building the s12z target on Solaris hosts where REG_Y is defined in system header files.
2020-01-02 12:04:40 +00:00
s390.h
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2020-01-01 18:42:54 +10:30
score-datadep.h
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score-inst.h
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sparc.h
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spu-insns.h
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2020-01-01 18:42:54 +10:30
spu.h
ubsan: spu: left shift of negative value
2020-01-10 17:32:33 +10:30
tic4x.h
tic4x: sign extension using shifts
2020-01-13 12:12:05 +10:30
tic6x-control-registers.h
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2020-01-01 18:42:54 +10:30
tic6x-insn-formats.h
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tic6x-opcode-table.h
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tic6x.h
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tic30.h
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tic54x.h
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tilegx.h
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2020-01-01 18:42:54 +10:30
tilepro.h
PR26044, Some targets can't be compiled with GCC 10 (tilepro)
2020-05-28 21:11:51 +09:30
v850.h
ubsan: v850-opc.c:412 left shift cannot be represented
2020-09-02 16:30:44 +09:30
vax.h
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visium.h
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wasm.h
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xgate.h
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