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5e5f37ed00
On x86, MAX_MEM_FOR_RS_ALIGN_CODE is 35, when the most common
alignment is 2**3 or 2**4, where the max memory required for the
alignment nops is 7 and 15 bytes respectively. So there is some
memory wasted since commit 83d94ae428. It's not a large amount,
especially considering that frag overhead on x86_46 is 144 bytes,
but even so I'd rather not be blamed for increasing gas memory usage.
So to reduce the memory we'd like to take the alignment into
consideration when initialising an rs_align_code frag. The only
difficulty here is start_bundle making an rs_align_code frag with an
alignment of zero initially, then later increasing the alignment. We
change that to use the bundle alignment when setting up the frag. I
think that is sufficient as bundle_align_p2 can't change in the middle
of a start_bundle/finish_bundle sequence.
I haven't modified any targets other than x86 in this patch. Most
won't benefit much due to using fairly small MAX_MEM_FOR_RS_ALIGN_CODE.
* read.c (start_bundle): Create rs_align_code frag with
bundle_align_p2 alignment, then set to zero alignment.
(finish_bundle): Adjust comment.
* frags.c (MAX_MEM_FOR_RS_ALIGN_CODE): Pass p2align and max
to macro.
* config/tc-i386.h (HANDLE_ALIGN): Assert that max_bytes is
sufficient for nop padding.
(max_mem_for_rs_align_code): New inline function.
(MAX_MEM_FOR_RS_ALIGN_CODE): Use it.
* config/tc-aarch64.h: Adjust MAX_MEM_FOR_RS_ALIGN_CODE.
* config/tc-alpha.h: Likewise.
* config/tc-arc.h: Likewise.
* config/tc-arm.h: Likewise.
* config/tc-epiphany.h: Likewise.
* config/tc-frv.h: Likewise.
* config/tc-ia64.h: Likewise.
* config/tc-kvx.h: Likewise.
* config/tc-loongarch.h: Likewise.
* config/tc-m32r.h: Likewise.
* config/tc-metag.h: Likewise.
* config/tc-mips.h: Likewise.
* config/tc-nds32.h: Likewise.
* config/tc-ppc.h: Likewise.
* config/tc-riscv.h: Likewise.
* config/tc-rl78.h: Likewise.
* config/tc-rx.h: Likewise.
* config/tc-score.h: Likewise.
* config/tc-sh.h: Likewise.
* config/tc-sparc.h: Likewise.
* config/tc-spu.h: Likewise.
* config/tc-tilegx.h: Likewise.
* config/tc-tilepro.h: Likewise.
* config/tc-visium.h: Likewise.
* config/tc-xtensa.h: Likewise.
110 lines
3.4 KiB
C
110 lines
3.4 KiB
C
/* spu.h -- Assembler for spu
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Copyright (C) 2006-2025 Free Software Foundation, Inc.
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This file is part of GAS, the GNU Assembler.
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GAS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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GAS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GAS; see the file COPYING. If not, write to the Free
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Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
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02110-1301, USA. */
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#ifndef TC_SPU
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#define TC_SPU 1
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#include "opcode/spu.h"
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#define TARGET_FORMAT "elf32-spu"
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#define TARGET_ARCH bfd_arch_spu
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#define TARGET_NAME "elf32-spu"
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#define TARGET_BYTES_BIG_ENDIAN 1
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struct tc_fix_info {
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unsigned short arg_format;
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unsigned short insn_tag;
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};
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/* fixS will have a member named tc_fix_data of this type. */
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#define TC_FIX_TYPE struct tc_fix_info
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#define TC_INIT_FIX_DATA(FIXP) \
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do \
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{ \
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(FIXP)->tc_fix_data.arg_format = 0; \
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(FIXP)->tc_fix_data.insn_tag = 0; \
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} \
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while (0)
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/* Don't reduce function symbols to section symbols, and don't adjust
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references to PPU symbols. */
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#define tc_fix_adjustable(FIXP) \
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(!(S_IS_FUNCTION ((FIXP)->fx_addsy) \
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|| (FIXP)->fx_r_type == BFD_RELOC_SPU_PPU32 \
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|| (FIXP)->fx_r_type == BFD_RELOC_SPU_PPU64 \
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|| (FIXP)->fx_r_type == BFD_RELOC_SPU_ADD_PIC))
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/* Keep relocs on calls. Branches to function symbols are tail or
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sibling calls. */
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#define TC_FORCE_RELOCATION(FIXP) \
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((FIXP)->tc_fix_data.insn_tag == M_BRSL \
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|| (FIXP)->tc_fix_data.insn_tag == M_BRASL \
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|| (((FIXP)->tc_fix_data.insn_tag == M_BR \
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|| (FIXP)->tc_fix_data.insn_tag == M_BRA) \
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&& (FIXP)->fx_addsy != NULL \
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&& S_IS_FUNCTION ((FIXP)->fx_addsy)) \
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|| (FIXP)->fx_r_type == BFD_RELOC_SPU_PPU32 \
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|| (FIXP)->fx_r_type == BFD_RELOC_SPU_PPU64 \
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|| (FIXP)->fx_r_type == BFD_RELOC_SPU_ADD_PIC \
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|| generic_force_reloc (FIXP))
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/* Values passed to md_apply_fix don't include symbol values. */
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#define MD_APPLY_SYM_VALUE(FIX) 0
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/* The spu uses pseudo-ops with no leading period. */
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#define NO_PSEUDO_DOT 1
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/* Don't warn on word overflow; it happens on %hi relocs. */
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#undef WARN_SIGNED_OVERFLOW_WORD
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#define DIFF_EXPR_OK
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#define WORKING_DOT_WORD
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#define md_number_to_chars number_to_chars_bigendian
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#define md_convert_frag(b,s,f) {as_fatal (_("spu convert_frag\n"));}
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/* We don't need to do anything special for undefined symbols. */
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#define md_undefined_symbol(s) 0
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extern symbolS *section_symbol (asection *);
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#define md_operand(e) \
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do { \
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if (strncasecmp (input_line_pointer, "@ppu", 4) == 0) \
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{ \
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e->X_op = O_symbol; \
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if (abs_section_sym == NULL) \
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abs_section_sym = section_symbol (absolute_section); \
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e->X_add_symbol = abs_section_sym; \
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e->X_add_number = 0; \
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} \
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} while (0)
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/* Fill in rs_align_code fragments. */
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extern void spu_handle_align (fragS *);
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#define HANDLE_ALIGN(sec, frag) spu_handle_align (frag)
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#define MAX_MEM_FOR_RS_ALIGN_CODE(p2align, max) (7 + 8)
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#endif /* TC_SPU */
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