mirror of
https://github.com/bminor/binutils-gdb.git
synced 2025-12-15 20:08:23 +00:00
0674ee5dad
Identify non-extensible instructions in the MIPS16 opcode table and
disallow their use with the `.e' instruction size suffix in assembly and
do not interpret any EXTEND prefix present as a part of the instruction
in disassembly.
According to all versions of the MIPS16 ASE specifications the following
instructions encodings are not extensible [1][2][3][4][5][6]: I8/MOV32R,
I8/MOVR32, all RRR minor opcodes, all RR minor opcodes except from DSRA
and DSRL, and EXTEND itself, and as from revision 2.50 of the MIPS16e
ASE specifications it has been further clarified what was previously
implied, that non-extesiable instructions when preceded with an EXTEND
prefix must cause a Reserved Instruction exception [3][5].
Therefore in the presence of an EXTEND prefix none of these instructions
are supposed to be handled as extended instructions and supporting these
forms in disassembly causes confusion, and in the case of the RRR major
opcode it also clashes with the ASMACRO encoding.
References:
[1] "Product Description, MIPS16 Application-Specific Extension",
Version 1.3, MIPS Technologies, Inc., 970130, Table 3. "MIPS16
Instruction Set Summary", p. 5
[2] same, Table 5 "RR Minor Opcodes (RR-type instructions)", p.10
[3] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e
Application-Specific Extension to the MIPS32 Architecture", MIPS
Technologies, Inc., Document Number: MD00076, Revision 2.63, July
16, 2013, Section 3.9 "MIPS16e Instruction Summaries", pp. 37-39
[4] same, Section 3.15 "Instruction Bit Encoding", pp. 46-49
[5] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e
Application-Specific Extension to the MIPS64 Architecture", MIPS
Technologies, Inc., Document Number: MD00077, Revision 2.60, June
25, 2008, Section 1.9 "MIPS16e Instruction Summaries", pp. 38-41
[6] same, Section 1.15 "Instruction Bit Encoding", pp. 48-51
include/
* opcode/mips.h (INSN2_SHORT_ONLY): New macro.
gas/
* config/tc-mips.c (is_size_valid_16): Disallow a `.e' suffix
instruction size override for INSN2_SHORT_ONLY opcode table
entries.
* testsuite/gas/mips/mips16-extend-swap.d: Adjust output.
* testsuite/gas/mips/mips16-macro-e.l: Adjust error messages.
* testsuite/gas/mips/mips16-32@mips16-macro-e.l: Adjust error
messages.
* testsuite/gas/mips/mips16e-32@mips16-macro-e.l: Adjust error
messages.
* testsuite/gas/mips/mips16-insn-e.d: New test.
* testsuite/gas/mips/mips16-insn-t.d: New test.
* testsuite/gas/mips/mips16-32@mips16-insn-e.d: New test.
* testsuite/gas/mips/mips16-64@mips16-insn-e.d: New test.
* testsuite/gas/mips/mips16e-32@mips16-insn-e.d: New test.
* testsuite/gas/mips/mips16-32@mips16-insn-t.d: New test.
* testsuite/gas/mips/mips16-64@mips16-insn-t.d: New test.
* testsuite/gas/mips/mips16e-32@mips16-insn-t.d: New test.
* testsuite/gas/mips/mips16-insn-e.l: New stderr output.
* testsuite/gas/mips/mips16-insn-t.l: New stderr output.
* testsuite/gas/mips/mips16-32@mips16-insn-e.l: New stderr
output.
* testsuite/gas/mips/mips16-64@mips16-insn-e.l: New stderr
output.
* testsuite/gas/mips/mips16e-32@mips16-insn-e.l: New stderr
output.
* testsuite/gas/mips/mips16-32@mips16-insn-t.l: New stderr
output.
* testsuite/gas/mips/mips16-64@mips16-insn-t.l: New stderr
output.
* testsuite/gas/mips/mips16e-32@mips16-insn-t.l: New stderr
output.
* testsuite/gas/mips/mips16-insn-e.s: New test source.
* testsuite/gas/mips/mips16-insn-t.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
opcodes/
* mips-dis.c (print_insn_mips16): Disallow EXTEND prefix
matching for INSN2_SHORT_ONLY opcode table entries.
* mips16-opc.c (SH): New macro.
(mips16_opcodes): Set SH in `pinfo2' for non-extensible
instruction entries: "nop", "addu", "and", "break", "cmp",
"daddu", "ddiv", "ddivu", "div", "divu", "dmult", "dmultu",
"drem", "dremu", "dsllv", "dsll", "dsrav", "dsra", "dsrlv",
"dsrl", "dsubu", "exit", "entry", "jalr", "jal", "jr", "j",
"jalrc", "jrc", "mfhi", "mflo", "move", "mult", "multu", "neg",
"not", "or", "rem", "remu", "sllv", "sll", "slt", "sltu",
"srav", "sra", "srlv", "srl", "subu", "xor", "sdbbp", "seb",
"seh", "sew", "zeb", "zeh", "zew" and "extend".
binutils/
* testsuite/binutils-all/mips/mips16-extend-insn.d: New test.
* testsuite/binutils-all/mips/mips16-extend-insn.s: New test
source.
* testsuite/binutils-all/mips/mips.exp: Run the new tests.
631 lines
9.1 KiB
ArmAsm
631 lines
9.1 KiB
ArmAsm
.set mips16
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.set noreorder
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foo:
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extend 0x123 # ADDIUSP
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addiu $16, $29, 0
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extend 0x123
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addiu $16, $29, 128
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extend 0x123
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addiu $16, $29, 256
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|
extend 0x123
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addiu $16, $29, 384
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extend 0x123
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addiu $16, $29, 512
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extend 0x123
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addiu $16, $29, 640
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extend 0x123
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addiu $16, $29, 768
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extend 0x123
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addiu $16, $29, 896
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|
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extend 0x123 # ADDIUPC
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addiu $16, $pc, 0
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extend 0x123
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addiu $16, $pc, 128
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extend 0x123
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addiu $16, $pc, 256
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extend 0x123
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addiu $16, $pc, 384
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extend 0x123
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addiu $16, $pc, 512
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extend 0x123
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addiu $16, $pc, 640
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extend 0x123
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addiu $16, $pc, 768
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extend 0x123
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addiu $16, $pc, 896
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|
|
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extend 0x123 # B
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b . + 2
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extend 0x123
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b . + 66
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extend 0x123
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b . + 130
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extend 0x123
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b . + 194
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extend 0x123
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b . + 258
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|
extend 0x123
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b . + 322
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extend 0x123
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b . + 386
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extend 0x123
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b . + 450
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|
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extend 0x123 # BEQZ
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beqz $16, . + 2
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extend 0x123
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beqz $16, . + 66
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extend 0x123
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beqz $16, . + 130
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extend 0x123
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beqz $16, . + 194
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extend 0x123
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beqz $16, . - 254
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extend 0x123
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beqz $16, . - 190
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extend 0x123
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beqz $16, . - 126
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extend 0x123
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beqz $16, . - 62
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extend 0x123 # BNEZ
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bnez $16, . + 2
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extend 0x123
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bnez $16, . + 66
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extend 0x123
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bnez $16, . + 130
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extend 0x123
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bnez $16, . + 194
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extend 0x123
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bnez $16, . - 254
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extend 0x123
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bnez $16, . - 190
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extend 0x123
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bnez $16, . - 126
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extend 0x123
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bnez $16, . - 62
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extend 0x123 # SHIFT # SLL
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sll $16, $16, 8
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extend 0x123
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sll $16, $16, 1
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extend 0x123
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sll $16, $16, 2
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extend 0x123
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sll $16, $16, 3
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extend 0x123
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sll $16, $16, 4
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extend 0x123
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sll $16, $16, 5
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extend 0x123
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sll $16, $16, 6
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extend 0x123
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sll $16, $16, 7
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extend 0x123 # DSLL
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dsll $16, $16, 8
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extend 0x123
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dsll $16, $16, 1
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extend 0x123
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dsll $16, $16, 2
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extend 0x123
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dsll $16, $16, 3
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extend 0x123
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dsll $16, $16, 4
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extend 0x123
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dsll $16, $16, 5
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extend 0x123
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dsll $16, $16, 6
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extend 0x123
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dsll $16, $16, 7
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extend 0x123 # SRL
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srl $16, $16, 8
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extend 0x123
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srl $16, $16, 1
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extend 0x123
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srl $16, $16, 2
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extend 0x123
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srl $16, $16, 3
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extend 0x123
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srl $16, $16, 4
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extend 0x123
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srl $16, $16, 5
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extend 0x123
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srl $16, $16, 6
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extend 0x123
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srl $16, $16, 7
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extend 0x123 # SRA
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sra $16, $16, 8
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extend 0x123
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sra $16, $16, 1
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extend 0x123
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sra $16, $16, 2
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extend 0x123
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sra $16, $16, 3
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extend 0x123
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sra $16, $16, 4
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extend 0x123
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sra $16, $16, 5
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extend 0x123
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sra $16, $16, 6
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extend 0x123
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sra $16, $16, 7
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extend 0x123 # LD
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ld $16, 0($16)
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extend 0x123 # RRI-A # ADDIU
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addiu $16, $16, 0
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extend 0x123 # DADDIU
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daddiu $16, $16, 0
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extend 0x123 # ADDIU8
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addiu $16, 0
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extend 0x123
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addiu $16, 32
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extend 0x123
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addiu $16, 64
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extend 0x123
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addiu $16, 96
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extend 0x123
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addiu $16, -128
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extend 0x123
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addiu $16, -96
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extend 0x123
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addiu $16, -64
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extend 0x123
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addiu $16, -32
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extend 0x123 # SLTI
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slti $16, 0
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extend 0x123
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slti $16, 32
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extend 0x123
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slti $16, 64
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extend 0x123
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slti $16, 96
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extend 0x123
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slti $16, 128
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extend 0x123
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slti $16, 160
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extend 0x123
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slti $16, 192
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extend 0x123
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slti $16, 224
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extend 0x123 # SLTIU
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sltiu $16, 0
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extend 0x123
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sltiu $16, 32
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extend 0x123
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sltiu $16, 64
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extend 0x123
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sltiu $16, 96
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extend 0x123
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sltiu $16, 128
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extend 0x123
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sltiu $16, 160
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extend 0x123
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sltiu $16, 192
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extend 0x123
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sltiu $16, 224
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extend 0x123 # I8 # BTEQZ
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bteqz . + 2
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extend 0x123
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bteqz . + 66
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extend 0x123
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bteqz . + 130
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extend 0x123
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bteqz . + 194
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extend 0x123
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bteqz . - 254
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extend 0x123
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bteqz . - 190
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extend 0x123
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bteqz . - 126
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extend 0x123
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bteqz . - 62
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extend 0x123 # BTNEZ
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btnez . + 2
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extend 0x123
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btnez . + 66
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extend 0x123
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btnez . + 130
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extend 0x123
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btnez . + 194
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extend 0x123
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btnez . - 254
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extend 0x123
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btnez . - 190
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extend 0x123
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btnez . - 126
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extend 0x123
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btnez . - 62
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extend 0x123 # SWRASP
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sw $31, 0($29)
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extend 0x123
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sw $31, 128($29)
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extend 0x123
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sw $31, 256($29)
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extend 0x123
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sw $31, 512($29)
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extend 0x123
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sw $31, 640($29)
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extend 0x123
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sw $31, 768($29)
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extend 0x123
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sw $31, 896($29)
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extend 0x123
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sw $31, 0($29)
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extend 0x123 # ADJSP
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addiu $29, 0
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extend 0x123
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addiu $29, 256
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extend 0x123
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addiu $29, 512
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extend 0x123
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addiu $29, 768
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extend 0x123
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addiu $29, -1024
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extend 0x123
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addiu $29, -768
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extend 0x123
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addiu $29, -512
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extend 0x123
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addiu $29, -256
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extend 0x123 # SVRS # RESTORE
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restore 128
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extend 0x123 # SAVE
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save 128
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extend 0x123 # MOV32R
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move $0, $16
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extend 0x123
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move $0, $17
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extend 0x123 # MOVR32
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move $16, $0
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extend 0x123 # LI
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li $16, 0
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extend 0x123
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li $16, 32
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extend 0x123
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li $16, 64
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extend 0x123
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li $16, 96
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extend 0x123
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li $16, 128
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extend 0x123
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li $16, 160
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extend 0x123
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li $16, 192
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extend 0x123
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li $16, 224
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extend 0x123 # CMPI
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cmpi $16, 0
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extend 0x123
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cmpi $16, 32
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extend 0x123
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cmpi $16, 64
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extend 0x123
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cmpi $16, 96
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extend 0x123
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cmpi $16, 128
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extend 0x123
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cmpi $16, 160
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extend 0x123
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cmpi $16, 192
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extend 0x123
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cmpi $16, 224
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extend 0x123 # SD
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sd $16, 0($16)
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extend 0x123 # LB
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lb $16, 0($16)
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extend 0x123 # LH
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lh $16, 0($16)
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extend 0x123 # LWSP
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lw $16, 0($29)
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extend 0x123
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lw $16, 128($29)
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extend 0x123
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lw $16, 256($29)
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extend 0x123
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lw $16, 384($29)
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extend 0x123
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lw $16, 512($29)
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extend 0x123
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lw $16, 640($29)
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extend 0x123
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lw $16, 768($29)
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extend 0x123
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lw $16, 896($29)
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extend 0x123 # LW
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lw $16, 0($16)
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extend 0x123 # LBU
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lbu $16, 0($16)
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extend 0x123 # LHU
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lhu $16, 0($16)
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extend 0x123 # LWPC
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lw $16, 0($pc)
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extend 0x123
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lw $16, 128($pc)
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extend 0x123
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lw $16, 256($pc)
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extend 0x123
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lw $16, 384($pc)
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extend 0x123
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lw $16, 512($pc)
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extend 0x123
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lw $16, 640($pc)
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extend 0x123
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lw $16, 768($pc)
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extend 0x123
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lw $16, 896($pc)
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extend 0x123 # LWU
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lwu $16, 0($16)
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extend 0x123 # SB
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sb $16, 0($16)
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extend 0x123 # SH
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sh $16, 0($16)
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extend 0x123 # SWSP
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sw $16, 0($29)
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extend 0x123
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sw $16, 128($29)
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extend 0x123
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sw $16, 256($29)
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extend 0x123
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sw $16, 384($29)
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extend 0x123
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sw $16, 512($29)
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extend 0x123
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sw $16, 640($29)
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extend 0x123
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sw $16, 768($29)
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extend 0x123
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sw $16, 896($29)
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extend 0x123 # SW
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sw $16, 0($16)
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extend 0x123 # RRR # DADDU
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daddu $16, $16, $16
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extend 0x123 # ADDU
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addu $16, $16, $16
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extend 0x123 # DSUBU
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dsubu $16, $16, $16
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extend 0x123 # SUBU
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subu $16, $16, $16
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extend 0x123 # RR # J(AL)R(C) # JR rx
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jr $16
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extend 0x123 # JR ra
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jr $31
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extend 0x123 # JALR
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jalr $16
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extend 0x123 # JRC rx
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jrc $16
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extend 0x123 # JRC ra
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jrc $31
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extend 0x123 # JALRC
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jalrc $16
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extend 0x123 # SDBBP
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sdbbp 0
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extend 0x123 # SLT
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slt $16, $16
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extend 0x123 # SLTU
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sltu $16, $16
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extend 0x123 # SLLV
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sllv $16, $16
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extend 0x123 # BREAK
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break 0
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extend 0x123 # SRLV
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srlv $16, $16
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extend 0x123 # SRAV
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srav $16, $16
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extend 0x123 # DSRL
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dsrl $16, 8
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extend 0x123
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dsrl $16, 1
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extend 0x123
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dsrl $16, 2
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extend 0x123
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dsrl $16, 3
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extend 0x123
|
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dsrl $16, 4
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extend 0x123
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dsrl $16, 5
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extend 0x123
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dsrl $16, 6
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extend 0x123
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dsrl $16, 7
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extend 0x123 # ENTRY/EXIT
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entry
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extend 0x123
|
|
entry $31
|
|
extend 0x123
|
|
exit $f0
|
|
extend 0x123
|
|
exit $f0-$f1
|
|
extend 0x123
|
|
exit
|
|
|
|
extend 0x123 # CMP
|
|
cmp $16, $16
|
|
|
|
extend 0x123 # NEG
|
|
neg $16, $16
|
|
|
|
extend 0x123 # AND
|
|
and $16, $16
|
|
|
|
extend 0x123 # OR
|
|
or $16, $16
|
|
|
|
extend 0x123 # XOR
|
|
xor $16, $16
|
|
|
|
extend 0x123 # NOT
|
|
not $16, $16
|
|
|
|
extend 0x123 # MFHI
|
|
mfhi $16
|
|
|
|
extend 0x123 # CNVT # ZEB
|
|
zeb $16
|
|
extend 0x123 # ZEH
|
|
zeh $16
|
|
extend 0x123 # ZEW
|
|
zew $16
|
|
extend 0x123 # SEB
|
|
seb $16
|
|
extend 0x123 # SEH
|
|
seh $16
|
|
extend 0x123 # SEW
|
|
sew $16
|
|
|
|
extend 0x123 # MFLO
|
|
mflo $16
|
|
|
|
extend 0x123 # DSRA
|
|
dsra $16, 8
|
|
extend 0x123
|
|
dsra $16, 1
|
|
extend 0x123
|
|
dsra $16, 2
|
|
extend 0x123
|
|
dsra $16, 3
|
|
extend 0x123
|
|
dsra $16, 4
|
|
extend 0x123
|
|
dsra $16, 5
|
|
extend 0x123
|
|
dsra $16, 6
|
|
extend 0x123
|
|
dsra $16, 7
|
|
|
|
extend 0x123 # DSLLV
|
|
dsllv $16, $16
|
|
|
|
extend 0x123 # DSRLV
|
|
dsrlv $16, $16
|
|
|
|
extend 0x123 # DSRAV
|
|
dsrav $16, $16
|
|
|
|
extend 0x123 # MULT
|
|
mult $16, $16
|
|
|
|
extend 0x123 # MULTU
|
|
multu $16, $16
|
|
|
|
extend 0x123 # DIV
|
|
div $0, $16, $16
|
|
|
|
extend 0x123 # DIVU
|
|
divu $0, $16, $16
|
|
|
|
extend 0x123 # DMULT
|
|
dmult $16, $16
|
|
|
|
extend 0x123 # DMULTU
|
|
dmultu $16, $16
|
|
|
|
extend 0x123 # DDIV
|
|
ddiv $0, $16, $16
|
|
|
|
extend 0x123 # DDIVU
|
|
ddivu $0, $16, $16
|
|
|
|
extend 0x123 # EXTEND
|
|
extend 0
|
|
|
|
extend 0x123 # I64 # LDSP
|
|
ld $16, 0($29)
|
|
|
|
extend 0x123 # SDSP
|
|
sd $16, 0($29)
|
|
|
|
extend 0x123 # SDRASP
|
|
sd $31, 0($29)
|
|
extend 0x123
|
|
sd $31, 256($29)
|
|
extend 0x123
|
|
sd $31, 512($29)
|
|
extend 0x123
|
|
sd $31, 768($29)
|
|
extend 0x123
|
|
sd $31, 1024($29)
|
|
extend 0x123
|
|
sd $31, 1280($29)
|
|
extend 0x123
|
|
sd $31, 1536($29)
|
|
extend 0x123
|
|
sd $31, 1792($29)
|
|
|
|
extend 0x123 # DADJSP
|
|
daddiu $29, 0
|
|
extend 0x123
|
|
daddiu $29, 256
|
|
extend 0x123
|
|
daddiu $29, 512
|
|
extend 0x123
|
|
daddiu $29, 768
|
|
extend 0x123
|
|
daddiu $29, -1024
|
|
extend 0x123
|
|
daddiu $29, -768
|
|
extend 0x123
|
|
daddiu $29, -512
|
|
extend 0x123
|
|
daddiu $29, -256
|
|
|
|
extend 0x123 # LDPC
|
|
ld $16, 0($pc)
|
|
|
|
extend 0x123 # DADDIU5
|
|
daddiu $16, 0
|
|
|
|
extend 0x123 # DADDIUPC
|
|
daddiu $16, $pc, 0
|
|
|
|
extend 0x123 # DADDIUSP
|
|
daddiu $16, $sp, 0
|
|
|
|
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
|
|
.align 4, 0
|
|
.space 16
|