Sivan Shani 4373edd2f6 AArch64: Add FEAT_F16F32DOT instructions ...

This includes the instructions for the F16F32DOT feature:
    - FDOT half-precision to single-precision, by element
    - FDOT half-precision to single-precision, vector

2025-12-27 12:45:52 +00:00

..

aarch64.h

AArch64: Add FEAT_F16F32DOT instructions

2025-12-27 12:45:52 +00:00

alpha.h

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arc-attrs.h

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arc-func.h

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arc.h

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arm.h

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avr.h

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bfin.h

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bpf.h

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cgen.h

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ChangeLog-0415

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ChangeLog-9103

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convex.h

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cr16.h

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cris.h

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crx.h

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csky.h

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d10v.h

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d30v.h

gas d30v_insn plus other non-const pointers

2025-07-09 09:35:07 +09:30

dlx.h

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ft32.h

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h8300.h

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hppa.h

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i386.h

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ia64.h

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kvx.h

kvx gcc-4.5 build fixes

2025-06-11 07:26:07 +09:30

loongarch.h

LoongArch: Add disassembly support for ud ui5

2025-12-20 10:49:47 +08:00

m68hc11.h

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m68k.h

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metag.h

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mips.h

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mmix.h

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mn10200.h

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mn10300.h

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moxie.h

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msp430-decode.h

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msp430.h

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nds32.h

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nfp.h

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np1.h

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ns32k.h

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pdp11.h

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pj.h

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pn.h

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ppc.h

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pru.h

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pyr.h

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riscv-opc.h

RISC-V: Fixed opcodes for some bitmanip instructions

2025-11-21 22:33:09 +03:00

riscv.h

RISC-V: Clarify the imply rule of c

2025-07-10 19:32:07 +08:00

rl78.h

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2025-01-01 18:29:57 +10:30

rx.h

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s12z.h

Enable building the s12z target on Solaris hosts where REG_Y is defined in system header files.

2020-01-02 12:04:40 +00:00

s390.h

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2025-01-01 18:29:57 +10:30

score-datadep.h

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score-inst.h

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sparc.h

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spu-insns.h

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spu.h

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tic4x.h

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tic6x-control-registers.h

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tic6x-insn-formats.h

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tic6x-opcode-table.h

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tic6x.h

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tic30.h

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tic54x.h

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tilegx.h

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tilepro.h

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v850.h

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vax.h

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visium.h

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wasm.h

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xgate.h

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