Srinath Parvathaneni 37fd5c9428 aarch64: Add support for POE2 instructions ...

This patch adds support for FEAT_S1POE2 feature enabled by "+poe2"
flag along with support for following instructions.

* TCHANGEB (immediate)
* TCHANGEB (register)
* TCHANGEF (immediate)
* TCHANGEF (register)

A new operand AARCH64_OPND_NOT_BALANCED_17 is added to the code in this
patch to support the new optional argument "NB" (not_balanced) which
is a 1-bit field in the encoding for all the above mentioned
instructions.

Co-authored-by:  Matthew Malcomson <matthew.malcomson@arm.com>

2026-01-05 17:50:24 +00:00

..

aarch64.h

aarch64: Add support for POE2 instructions

2026-01-05 17:50:24 +00:00

alpha.h

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arc-attrs.h

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arc-func.h

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arc.h

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arm.h

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avr.h

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bfin.h

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bpf.h

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cgen.h

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ChangeLog-0415

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ChangeLog-9103

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convex.h

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cr16.h

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cris.h

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crx.h

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csky.h

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d10v.h

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d30v.h

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dlx.h

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ft32.h

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h8300.h

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hppa.h

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i386.h

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ia64.h

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kvx.h

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loongarch.h

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m68hc11.h

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m68k.h

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metag.h

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mips.h

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mmix.h

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mn10200.h

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mn10300.h

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moxie.h

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msp430-decode.h

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msp430.h

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nds32.h

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nfp.h

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np1.h

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ns32k.h

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pdp11.h

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pj.h

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pn.h

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ppc.h

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pru.h

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pyr.h

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riscv-opc.h

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riscv.h

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rl78.h

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rx.h

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s12z.h

Enable building the s12z target on Solaris hosts where REG_Y is defined in system header files.

2020-01-02 12:04:40 +00:00

s390.h

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score-datadep.h

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score-inst.h

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sparc.h

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spu-insns.h

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spu.h

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tic4x.h

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tic6x-control-registers.h

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tic6x-insn-formats.h

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tic6x-opcode-table.h

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tic6x.h

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tic30.h

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tic54x.h

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tilegx.h

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tilepro.h

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v850.h

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vax.h

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visium.h

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wasm.h

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xgate.h

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