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a8acc70c5e
Introduce corresponding C pseudo registers that contain the following
fields:
type = struct __gdb_builtin_type_capability {
uint64_t l;
uint64_t u;
bool t;
}
For each register of the C set, users can reference the pseudo registers by
adding a 'p' prefix. For example, the pseudo register of c0 and pcc are pc0
and ppcc.
Users can set the entire 129 bits of the capability this way, if the
cheri.ptrace_forge_cap flag is enabled.
176 lines
4.9 KiB
C
176 lines
4.9 KiB
C
/* Common target dependent code for GDB on AArch64 systems.
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Copyright (C) 2009-2020 Free Software Foundation, Inc.
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Contributed by ARM Ltd.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef AARCH64_TDEP_H
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#define AARCH64_TDEP_H
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#include "arch/aarch64.h"
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#include "infrun.h"
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/* Forward declarations. */
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struct gdbarch;
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struct regset;
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/* AArch64 Dwarf register numbering. */
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#define AARCH64_DWARF_X0 0
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#define AARCH64_DWARF_SP 31
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#define AARCH64_DWARF_PAUTH_RA_STATE 34
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#define AARCH64_DWARF_PAUTH_DMASK 35
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#define AARCH64_DWARF_PAUTH_CMASK 36
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#define AARCH64_DWARF_V0 64
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#define AARCH64_DWARF_SVE_VG 46
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#define AARCH64_DWARF_SVE_FFR 47
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#define AARCH64_DWARF_SVE_P0 48
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#define AARCH64_DWARF_SVE_Z0 96
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#define AARCH64_DWARF_C0 198
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#define AARCH64_DWARF_CLR 228
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#define AARCH64_DWARF_CSP 229
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#define AARCH64_DWARF_PCC 230
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#define AARCH64_DWARF_DDC 231
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#define AARCH64_DWARF_RESERVED_1 232
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#define AARCH64_DWARF_RESERVED_2 233
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/* Size of integer registers. */
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#define X_REGISTER_SIZE 8
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#define B_REGISTER_SIZE 1
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#define H_REGISTER_SIZE 2
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#define S_REGISTER_SIZE 4
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#define D_REGISTER_SIZE 8
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#define V_REGISTER_SIZE 16
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#define Q_REGISTER_SIZE 16
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#define C_REGISTER_SIZE 16
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/* Total number of general (X) registers. */
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#define AARCH64_X_REGISTER_COUNT 32
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/* Total number of D registers. */
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#define AARCH64_D_REGISTER_COUNT 32
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/* Total number of Morello pseudo registers. */
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#define AARCH64_C_PSEUDO_COUNT 39
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/* The maximum number of modified instructions generated for one
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single-stepped instruction. */
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#define AARCH64_DISPLACED_MODIFIED_INSNS 1
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/* AArch64 ABI used by the inferior. */
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enum aarch64_abi_kind
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{
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AARCH64_ABI_AUTO,
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/* Procedure Call Standard for the Arm 64-bit Architecture. */
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AARCH64_ABI_AAPCS64,
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/* The pure capability Procedure Call Standard for the Arm 64-bit
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Architecture (AArch64). */
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AARCH64_ABI_AAPCS64_CAP,
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AARCH64_ABI_LAST
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};
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/* Target-dependent structure in gdbarch. */
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struct gdbarch_tdep
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{
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/* The current ABI. */
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aarch64_abi_kind abi;
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/* Lowest address at which instructions will appear. */
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CORE_ADDR lowest_pc;
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/* Offset to PC value in jump buffer. If this is negative, longjmp
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support will be disabled. */
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int jb_pc;
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/* And the size of each entry in the buf. */
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size_t jb_elt_size;
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/* Types for AdvSISD registers. */
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struct type *vnq_type;
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struct type *vnd_type;
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struct type *vns_type;
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struct type *vnh_type;
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struct type *vnb_type;
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struct type *vnv_type;
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/* syscall record. */
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int (*aarch64_syscall_record) (struct regcache *regcache, unsigned long svc_number);
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/* The VQ value for SVE targets, or zero if SVE is not supported. */
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uint64_t vq;
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/* Returns true if the target supports SVE. */
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bool has_sve () const
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{
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return vq != 0;
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}
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int pauth_reg_base;
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int pauth_ra_state_regnum;
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/* Returns true if the target supports pauth. */
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bool has_pauth () const
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{
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return pauth_reg_base != -1;
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}
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/* First register from the capability set. */
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int cap_reg_base;
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/* Last register from the capability set. */
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int cap_reg_last;
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/* CLR register number. */
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int cap_reg_clr;
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/* CSP register numbers. */
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int cap_reg_csp;
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/* PCC register number. */
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int cap_reg_pcc;
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/* RCSP register number. */
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int cap_reg_rcsp;
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/* First capability pseudo register. */
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int cap_pseudo_base;
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/* Number of capability pseudo registers. */
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int cap_pseudo_count;
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/* Types for Morello. */
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struct type *morello_capability_pseudo_type;
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/* Returns true if the target supports capabilities. */
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bool has_capability () const
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{
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return cap_reg_base != -1;
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}
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};
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const target_desc *aarch64_read_description (uint64_t vq, bool pauth_p,
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bool capability_p);
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extern int aarch64_process_record (struct gdbarch *gdbarch,
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struct regcache *regcache, CORE_ADDR addr);
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displaced_step_closure_up
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aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch,
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CORE_ADDR from, CORE_ADDR to,
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struct regcache *regs);
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void aarch64_displaced_step_fixup (struct gdbarch *gdbarch,
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struct displaced_step_closure *dsc,
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CORE_ADDR from, CORE_ADDR to,
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struct regcache *regs);
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int aarch64_displaced_step_hw_singlestep (struct gdbarch *gdbarch,
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struct displaced_step_closure *closure);
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#endif /* aarch64-tdep.h */
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