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https://github.com/bminor/binutils-gdb.git
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1a5362ce51
Propagate the use of target_desc unique pointers further. Basically, avoid releasing target_desc objects, except in some spots in gdbserver (e.g. netbsd) where we don't currently have a persistent container for created target descriptions (and the target desc just leaks). Introduce const_target_desc_up to change some `const target_desc *` to a unique pointer without loss of constness. Architectures that use the old regformats/regdat.sh don't need to be changed, because their target_desc objects are statically allocated in the generated files. I was able to built-test these native configs: - Linux AArch64 - Linux ARC - Linux AMD64 - Linux ARM - Linux LoongArch - Linux M68K - Linux Microblaze - Linux MIPS (32 and 64) - Linux or1k - Linux PPC (32 and 64) - Linux RISC-V - Linux s390x - Linux SH4 - Linux Sparc (32 and 64) - Linux Xtensa - FreeBSD AMD64 - NetBSD AMD64 - Windows i686 - Windows AMD64 For the rest, I did my best by staring at the code long enough. I probably missed or messed some spots, but that shouldn't be difficult to fix. Change-Id: I8db8790c57942edd2bfe890987157e2dc0c67879 Reviewed-by: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
255 lines
8.8 KiB
C++
255 lines
8.8 KiB
C++
/* Common target-dependent functionality for AArch64.
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Copyright (C) 2017-2025 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef GDB_ARCH_AARCH64_H
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#define GDB_ARCH_AARCH64_H
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#include "gdbsupport/tdesc.h"
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/* Holds information on what architectural features are available. This is
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used to select register sets. */
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struct aarch64_features
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{
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/* A non zero VQ value indicates both the presence of SVE and the
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Vector Quotient - the number of 128-bit chunks in an SVE Z
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register.
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The maximum value for VQ is 16 (5 bits). */
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uint64_t vq = 0;
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bool pauth = false;
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bool mte = false;
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bool fpmr = false;
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/* A positive TLS value indicates the number of TLS registers available. */
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uint8_t tls = 0;
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/* The allowed values for SVQ are the following:
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0 - SME is not supported/available.
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1 - SME is available, SVL is 16 bytes / 128-bit.
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2 - SME is available, SVL is 32 bytes / 256-bit.
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4 - SME is available, SVL is 64 bytes / 512-bit.
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8 - SME is available, SVL is 128 bytes / 1024-bit.
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16 - SME is available, SVL is 256 bytes / 2048-bit.
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These use at most 5 bits to represent. */
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uint8_t svq = 0;
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/* Whether SME2 is supported. */
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bool sme2 = false;
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/* Whether Guarded Control Stack is supported. */
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bool gcs = false;
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/* Whether Guarded Control Stack Linux features are supported. */
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bool gcs_linux = false;
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};
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inline bool operator==(const aarch64_features &lhs, const aarch64_features &rhs)
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{
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return lhs.vq == rhs.vq
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&& lhs.pauth == rhs.pauth
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&& lhs.mte == rhs.mte
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&& lhs.tls == rhs.tls
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&& lhs.svq == rhs.svq
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&& lhs.sme2 == rhs.sme2
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&& lhs.gcs == rhs.gcs
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&& lhs.gcs_linux == rhs.gcs_linux
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&& lhs.fpmr == rhs.fpmr;
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}
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namespace std
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{
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template<>
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struct hash<aarch64_features>
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{
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std::size_t operator()(const aarch64_features &features) const noexcept
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{
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std::size_t h;
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h = features.vq;
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h = h << 1 | features.pauth;
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h = h << 1 | features.mte;
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/* Shift by two bits for now. We may need to increase this in the future
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if more TLS registers get added. */
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h = h << 2 | features.tls;
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/* Make sure the SVQ values are within the limits. */
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gdb_assert (features.svq >= 0);
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gdb_assert (features.svq <= 16);
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h = h << 5 | (features.svq & 0x5);
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/* SME2 feature. */
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h = h << 1 | features.sme2;
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h = h << 1 | features.gcs;
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h = h << 1 | features.gcs_linux;
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/* FPMR feature. */
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h = h << 1 | features.fpmr;
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return h;
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}
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};
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}
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/* Create the aarch64 target description. */
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target_desc_up
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aarch64_create_target_description (const aarch64_features &features);
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/* Given a pointer value POINTER and a MASK of non-address bits, remove the
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non-address bits from the pointer and sign-extend the result if required.
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The sign-extension is required so we can handle kernel addresses
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correctly. */
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CORE_ADDR aarch64_remove_top_bits (CORE_ADDR pointer, CORE_ADDR mask);
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/* Given CMASK and DMASK the two PAC mask registers, return the correct PAC
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mask to use for removing non-address bits from a pointer. */
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CORE_ADDR
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aarch64_mask_from_pac_registers (const CORE_ADDR cmask, const CORE_ADDR dmask);
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/* Register numbers of various important registers.
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Note that on SVE, the Z registers reuse the V register numbers and the V
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registers become pseudo registers. */
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enum aarch64_regnum
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{
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AARCH64_X0_REGNUM, /* First integer register. */
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AARCH64_FP_REGNUM = AARCH64_X0_REGNUM + 29, /* Frame register, if used. */
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AARCH64_LR_REGNUM = AARCH64_X0_REGNUM + 30, /* Return address. */
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AARCH64_SP_REGNUM, /* Stack pointer. */
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AARCH64_PC_REGNUM, /* Program counter. */
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AARCH64_CPSR_REGNUM, /* Current Program Status Register. */
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AARCH64_V0_REGNUM, /* First fp/vec register. */
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AARCH64_V31_REGNUM = AARCH64_V0_REGNUM + 31, /* Last fp/vec register. */
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AARCH64_SVE_Z0_REGNUM = AARCH64_V0_REGNUM, /* First SVE Z register. */
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AARCH64_SVE_Z31_REGNUM = AARCH64_V31_REGNUM, /* Last SVE Z register. */
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AARCH64_FPSR_REGNUM, /* Floating Point Status Register. */
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AARCH64_FPCR_REGNUM, /* Floating Point Control Register. */
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AARCH64_SVE_P0_REGNUM, /* First SVE predicate register. */
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AARCH64_SVE_P15_REGNUM = AARCH64_SVE_P0_REGNUM + 15, /* Last SVE predicate
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register. */
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AARCH64_SVE_FFR_REGNUM, /* SVE First Fault Register. */
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AARCH64_SVE_VG_REGNUM, /* SVE Vector Granule. */
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/* Other useful registers. */
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AARCH64_LAST_X_ARG_REGNUM = AARCH64_X0_REGNUM + 7,
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AARCH64_STRUCT_RETURN_REGNUM = AARCH64_X0_REGNUM + 8,
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AARCH64_LAST_V_ARG_REGNUM = AARCH64_V0_REGNUM + 7
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};
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/* Sizes of various AArch64 registers. */
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#define AARCH64_TLS_REGISTER_SIZE 8
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#define V_REGISTER_SIZE 16
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/* PAC-related constants. */
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/* Bit 55 is used to select between a kernel-space and user-space address. */
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#define VA_RANGE_SELECT_BIT_MASK 0x80000000000000ULL
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/* Mask with 1's in bits 55~63, used to remove the top byte of pointers
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(Top Byte Ignore). */
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#define AARCH64_TOP_BITS_MASK 0xff80000000000000ULL
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/* Pseudo register base numbers. */
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#define AARCH64_Q0_REGNUM 0
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#define AARCH64_D0_REGNUM (AARCH64_Q0_REGNUM + AARCH64_D_REGISTER_COUNT)
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#define AARCH64_S0_REGNUM (AARCH64_D0_REGNUM + 32)
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#define AARCH64_H0_REGNUM (AARCH64_S0_REGNUM + 32)
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#define AARCH64_B0_REGNUM (AARCH64_H0_REGNUM + 32)
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#define AARCH64_SVE_V0_REGNUM (AARCH64_B0_REGNUM + 32)
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#define AARCH64_PAUTH_DMASK_REGNUM(pauth_reg_base) (pauth_reg_base)
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#define AARCH64_PAUTH_CMASK_REGNUM(pauth_reg_base) (pauth_reg_base + 1)
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/* The high versions of these masks are used for bare metal/kernel-mode pointer
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authentication support. */
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#define AARCH64_PAUTH_DMASK_HIGH_REGNUM(pauth_reg_base) (pauth_reg_base + 2)
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#define AARCH64_PAUTH_CMASK_HIGH_REGNUM(pauth_reg_base) (pauth_reg_base + 3)
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/* This size is only meant for Linux, not bare metal. QEMU exposes 4 masks. */
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#define AARCH64_PAUTH_REGS_SIZE (16)
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#define AARCH64_X_REGS_NUM 31
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#define AARCH64_V_REGS_NUM 32
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#define AARCH64_SVE_Z_REGS_NUM AARCH64_V_REGS_NUM
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#define AARCH64_SVE_P_REGS_NUM 16
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#define AARCH64_NUM_REGS AARCH64_FPCR_REGNUM + 1
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#define AARCH64_SVE_NUM_REGS AARCH64_SVE_VG_REGNUM + 1
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/* There are a number of ways of expressing the current SVE vector size:
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VL : Vector Length.
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The number of bytes in an SVE Z register.
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VQ : Vector Quotient.
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The number of 128bit chunks in an SVE Z register.
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VG : Vector Granule.
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The number of 64bit chunks in an SVE Z register. */
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#define sve_vg_from_vl(vl) ((vl) / 8)
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#define sve_vl_from_vg(vg) ((vg) * 8)
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#ifndef sve_vq_from_vl
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#define sve_vq_from_vl(vl) ((vl) / 0x10)
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#endif
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#ifndef sve_vl_from_vq
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#define sve_vl_from_vq(vq) ((vq) * 0x10)
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#endif
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#define sve_vq_from_vg(vg) (sve_vq_from_vl (sve_vl_from_vg (vg)))
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#define sve_vg_from_vq(vq) (sve_vg_from_vl (sve_vl_from_vq (vq)))
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/* Maximum supported VQ value. Increase if required. */
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#define AARCH64_MAX_SVE_VQ 16
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/* SME definitions
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Some of these definitions are not found in the Architecture Reference
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Manual, but we use them so we can keep a similar standard compared to the
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SVE definitions that the Linux Kernel uses. Otherwise it can get
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confusing.
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SVL : Streaming Vector Length.
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Although the documentation handles SVL in bits, we do it in
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bytes to match what we do for SVE.
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The streaming vector length dictates the size of the ZA register and
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the size of the SVE registers when in streaming mode.
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SVQ : Streaming Vector Quotient.
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The number of 128-bit chunks in an SVE Z register or the size of
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each dimension of the SME ZA matrix.
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SVG : Streaming Vector Granule.
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The number of 64-bit chunks in an SVE Z register or the size of
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half a SME ZA matrix dimension. The SVG definition was added so
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we keep a familiar definition when dealing with SVE registers in
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streaming mode. */
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/* The total number of tiles. This is always fixed regardless of the
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streaming vector length (svl). */
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#define AARCH64_ZA_TILES_NUM 31
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/* svl limits for SME. */
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#define AARCH64_SME_MIN_SVL 128
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#define AARCH64_SME_MAX_SVL 2048
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/* Size of the SME2 ZT0 register in bytes. */
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#define AARCH64_SME2_ZT0_SIZE 64
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/* Feature check for Floating Point Mode Register. */
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#ifndef HWCAP2_FPMR
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#define HWCAP2_FPMR (1ULL << 48)
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#endif /* HWCAP2_FPMR */
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#endif /* GDB_ARCH_AARCH64_H */
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