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63b862be76
This patch adds the user mode register PL3_SSP which is part of the
Intel(R) Control-Flow Enforcement Technology (CET) feature for support
of shadow stack.
For now, only native and remote debugging support for shadow stack
userspace on amd64 linux are covered by this patch including 64 bit and
x32 support. 32 bit support is not covered due to missing Linux kernel
support.
This patch requires fixing the test gdb.base/inline-frame-cycle-unwind
which is failing in case the shadow stack pointer is unavailable.
Such a state is possible if shadow stack is disabled for the current thread
but supported by HW.
This test uses the Python unwinder inline-frame-cycle-unwind.py which fakes
the cyclic stack cycle by reading the pending frame's registers and adding
them to the unwinder:
~~~
for reg in pending_frame.architecture().registers("general"):
val = pending_frame.read_register(reg)
unwinder.add_saved_register(reg, val)
return unwinder
~~~
However, in case the python unwinder is used we add a register (pl3_ssp) that is
unavailable. This leads to a NOT_AVAILABLE_ERROR caught in
gdb/frame-unwind.c:frame_unwind_try_unwinder and it is continued with standard
unwinders. This destroys the faked cyclic behavior and the stack is
further unwinded after frame 5.
In the working scenario an error should be triggered:
~~~
bt
0 inline_func () at /tmp/gdb.base/inline-frame-cycle-unwind.c:49^M
1 normal_func () at /tmp/gdb.base/inline-frame-cycle-unwind.c:32^M
2 0x000055555555516e in inline_func () at /tmp/gdb.base/inline-frame-cycle-unwind.c:45^M
3 normal_func () at /tmp/gdb.base/inline-frame-cycle-unwind.c:32^M
4 0x000055555555516e in inline_func () at /tmp/gdb.base/inline-frame-cycle-unwind.c:45^M
5 normal_func () at /tmp/gdb.base/inline-frame-cycle-unwind.c:32^M
Backtrace stopped: previous frame identical to this frame (corrupt stack?)
(gdb) PASS: gdb.base/inline-frame-cycle-unwind.exp: cycle at level 5: backtrace when the unwind is broken at frame 5
~~~
To fix the Python unwinder, we simply skip the unavailable registers.
Also it makes the test gdb.dap/scopes.exp fail. The shadow stack feature is
disabled by default, so the pl3_ssp register which is added with my CET
shadow stack series will be shown as unavailable and we see a TCL error:
~~
>>> {"seq": 12, "type": "request", "command": "variables", "arguments": {"variablesReference": 2, "count": 85}}
Content-Length: 129^M
^M
{"request_seq": 12, "type": "response", "command": "variables", "success": false, "message": "value is not available", "seq": 25}FAIL: gdb.dap/scopes.exp: fetch all registers success
ERROR: tcl error sourcing /tmp/gdb/testsuite/gdb.dap/scopes.exp.
ERROR: tcl error code TCL LOOKUP DICT body
ERROR: key "body" not known in dictionary
while executing
"dict get $val body variables"
(file "/tmp/gdb/testsuite/gdb.dap/scopes.exp" line 152)
invoked from within
"source /tmp/gdb/testsuite/gdb.dap/scopes.exp"
("uplevel" body line 1)
invoked from within
"uplevel #0 source /tmp/gdb/testsuite/gdb.dap/scopes.exp"
invoked from within
"catch "uplevel #0 source $test_file_name" msg"
UNRESOLVED: gdb.dap/scopes.exp: testcase '/tmp/gdb/testsuite/gdb.dap/scopes.exp' aborted due to Tcl error
~~
I am fixing this by enabling the test for CET shadow stack, in case we
detect that the HW supports it:
~~~
# If x86 shadow stack is supported we need to configure GLIBC_TUNABLES
# such that the feature is enabled and the register pl3_ssp is
# available. Otherwise the reqeust to fetch all registers will fail
# with "message": "value is not available".
if { [allow_ssp_tests] } {
append_environment GLIBC_TUNABLES "glibc.cpu.hwcaps" "SHSTK"
}
~~~
Reviewed-by: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
Reviewed-By: Eli Zaretskii <eliz@gnu.org>
Approved-By: Luis Machado <luis.machado@arm.com>
Approved-By: Andrew Burgess <aburgess@redhat.com>
155 lines
5.3 KiB
C++
155 lines
5.3 KiB
C++
/* Target-dependent definitions for AMD64.
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Copyright (C) 2001-2025 Free Software Foundation, Inc.
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Contributed by Jiri Smid, SuSE Labs.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef GDB_AMD64_TDEP_H
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#define GDB_AMD64_TDEP_H
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struct gdbarch;
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class frame_info_ptr;
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struct regcache;
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#include "i386-tdep.h"
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#include "infrun.h"
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/* Register numbers of various important registers. */
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enum amd64_regnum
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{
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AMD64_RAX_REGNUM, /* %rax */
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AMD64_RBX_REGNUM, /* %rbx */
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AMD64_RCX_REGNUM, /* %rcx */
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AMD64_RDX_REGNUM, /* %rdx */
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AMD64_RSI_REGNUM, /* %rsi */
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AMD64_RDI_REGNUM, /* %rdi */
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AMD64_RBP_REGNUM, /* %rbp */
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AMD64_RSP_REGNUM, /* %rsp */
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AMD64_R8_REGNUM, /* %r8 */
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AMD64_R9_REGNUM, /* %r9 */
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AMD64_R10_REGNUM, /* %r10 */
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AMD64_R11_REGNUM, /* %r11 */
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AMD64_R12_REGNUM, /* %r12 */
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AMD64_R13_REGNUM, /* %r13 */
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AMD64_R14_REGNUM, /* %r14 */
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AMD64_R15_REGNUM, /* %r15 */
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AMD64_RIP_REGNUM, /* %rip */
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AMD64_EFLAGS_REGNUM, /* %eflags */
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AMD64_CS_REGNUM, /* %cs */
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AMD64_SS_REGNUM, /* %ss */
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AMD64_DS_REGNUM, /* %ds */
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AMD64_ES_REGNUM, /* %es */
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AMD64_FS_REGNUM, /* %fs */
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AMD64_GS_REGNUM, /* %gs */
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AMD64_ST0_REGNUM = 24, /* %st0 */
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AMD64_ST1_REGNUM, /* %st1 */
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AMD64_FCTRL_REGNUM = AMD64_ST0_REGNUM + 8,
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AMD64_FSTAT_REGNUM = AMD64_ST0_REGNUM + 9,
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AMD64_FTAG_REGNUM = AMD64_ST0_REGNUM + 10,
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AMD64_XMM0_REGNUM = 40, /* %xmm0 */
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AMD64_XMM1_REGNUM, /* %xmm1 */
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AMD64_MXCSR_REGNUM = AMD64_XMM0_REGNUM + 16,
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AMD64_YMM0H_REGNUM, /* %ymm0h */
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AMD64_YMM15H_REGNUM = AMD64_YMM0H_REGNUM + 15,
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/* MPX is deprecated. Yet we keep this to not give the registers below
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a new number. That could break older gdbservers. */
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AMD64_BND0R_REGNUM = AMD64_YMM15H_REGNUM + 1,
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AMD64_BND3R_REGNUM = AMD64_BND0R_REGNUM + 3,
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AMD64_BNDCFGU_REGNUM,
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AMD64_BNDSTATUS_REGNUM,
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AMD64_XMM16_REGNUM,
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AMD64_XMM31_REGNUM = AMD64_XMM16_REGNUM + 15,
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AMD64_YMM16H_REGNUM,
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AMD64_YMM31H_REGNUM = AMD64_YMM16H_REGNUM + 15,
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AMD64_K0_REGNUM,
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AMD64_K7_REGNUM = AMD64_K0_REGNUM + 7,
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AMD64_ZMM0H_REGNUM,
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AMD64_ZMM31H_REGNUM = AMD64_ZMM0H_REGNUM + 31,
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AMD64_PKRU_REGNUM,
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AMD64_PL3_SSP_REGNUM,
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AMD64_FSBASE_REGNUM,
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AMD64_GSBASE_REGNUM
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};
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/* Number of general purpose registers. */
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#define AMD64_NUM_GREGS 24
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#define AMD64_NUM_REGS (AMD64_GSBASE_REGNUM + 1)
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extern displaced_step_copy_insn_closure_up amd64_displaced_step_copy_insn
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(struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to,
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struct regcache *regs);
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extern void amd64_displaced_step_fixup
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(struct gdbarch *gdbarch, displaced_step_copy_insn_closure *closure,
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CORE_ADDR from, CORE_ADDR to, struct regcache *regs, bool completed_p);
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/* Initialize the ABI for amd64. Uses DEFAULT_TDESC as fallback
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tdesc, if INFO does not specify one. */
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extern void amd64_init_abi (struct gdbarch_info info,
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struct gdbarch *gdbarch,
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const target_desc *default_tdesc);
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/* Initialize the ABI for x32. Uses DEFAULT_TDESC as fallback tdesc,
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if INFO does not specify one. */
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extern void amd64_x32_init_abi (struct gdbarch_info info,
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struct gdbarch *gdbarch,
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const target_desc *default_tdesc);
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/* Return the target description for the specified xsave features as
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defined in XSTATE_BV and SEGMENTS. */
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extern const struct target_desc *amd64_target_description
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(uint64_t xstate_bv, bool segments);
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/* Fill register REGNUM in REGCACHE with the appropriate
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floating-point or SSE register value from *FXSAVE. If REGNUM is
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-1, do this for all registers. This function masks off any of the
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reserved bits in *FXSAVE. */
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extern void amd64_supply_fxsave (struct regcache *regcache, int regnum,
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const void *fxsave);
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/* Similar to amd64_supply_fxsave, but use XSAVE extended state. */
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extern void amd64_supply_xsave (struct regcache *regcache, int regnum,
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const void *xsave);
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/* Fill register REGNUM (if it is a floating-point or SSE register) in
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*FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
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all registers. This function doesn't touch any of the reserved
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bits in *FXSAVE. */
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extern void amd64_collect_fxsave (const struct regcache *regcache, int regnum,
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void *fxsave);
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/* Similar to amd64_collect_fxsave, but use XSAVE extended state. */
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extern void amd64_collect_xsave (const struct regcache *regcache,
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int regnum, void *xsave, int gcore);
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/* Floating-point register set. */
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extern const struct regset amd64_fpregset;
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/* Variables exported from amd64-linux-tdep.c. */
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extern int amd64_linux_gregset_reg_offset[];
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/* Variables exported from amd64-netbsd-tdep.c. */
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extern int amd64nbsd_r_reg_offset[];
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/* Variables exported from amd64-obsd-tdep.c. */
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extern int amd64obsd_r_reg_offset[];
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#endif /* GDB_AMD64_TDEP_H */
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