mirror of
https://github.com/bminor/binutils-gdb.git
synced 2025-12-11 01:53:10 +00:00
d2d240ff89
Run gdb/contrib/spellcheck.sh on directory sim. Fix auto-corrected typos: ... accessable -> accessible accidently -> accidentally accomodate -> accommodate adress -> address afair -> affair agains -> against agressively -> aggressively annuled -> annulled arbitary -> arbitrary arround -> around auxillary -> auxiliary availablity -> availability clasic -> classic comming -> coming controled -> controlled controling -> controlling destory -> destroy existance -> existence explictly -> explicitly faciliate -> facilitate fouth -> fourth fullfilled -> fulfilled guarentee -> guarantee hinderance -> hindrance independant -> independent inital -> initial loosing -> losing occurance -> occurrence occured -> occurred occuring -> occurring omited -> omitted oportunity -> opportunity parallely -> parallelly permissable -> permissible postive -> positive powerfull -> powerful preceed -> precede preceeding -> preceding preceeds -> precedes primative -> primitive probaly -> probably programable -> programmable propogate -> propagate propper -> proper recieve -> receive reconized -> recognized refered -> referred refering -> referring relevent -> relevant responisble -> responsible retreive -> retrieve safty -> safety specifiying -> specifying spontanous -> spontaneous sqaure -> square successfull -> successful supress -> suppress sytem -> system thru -> through transfered -> transferred trigered -> triggered unfortunatly -> unfortunately upto -> up to usefull -> useful wierd -> weird writen -> written doesnt -> doesn't isnt -> isn't ... Manually undid the "andd -> and" transformation in sim/testsuite/cr16/andd.cgs and sim/cr16/simops.c. Tested by rebuilding on x86_64-linux. Approved-By: Tom Tromey <tom@tromey.com>
446 lines
13 KiB
C
446 lines
13 KiB
C
/* The IGEN simulator generator for GDB, the GNU Debugger.
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Copyright 2002-2024 Free Software Foundation, Inc.
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Contributed by Andrew Cagney.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "misc.h"
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#include "lf.h"
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#include "table.h"
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#include "filter.h"
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#include "igen.h"
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#include "ld-insn.h"
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#include "ld-decode.h"
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#include "gen.h"
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#include "gen-idecode.h"
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#include "gen-engine.h"
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#include "gen-icache.h"
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#include "gen-semantics.h"
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static void
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print_engine_issue_prefix_hook (lf *file)
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{
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lf_printf (file, "\n");
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lf_indent_suppress (file);
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lf_printf (file, "#if defined (ENGINE_ISSUE_PREFIX_HOOK)\n");
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lf_printf (file, "ENGINE_ISSUE_PREFIX_HOOK();\n");
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lf_indent_suppress (file);
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lf_printf (file, "#endif\n");
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lf_printf (file, "\n");
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}
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static void
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print_engine_issue_postfix_hook (lf *file)
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{
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lf_printf (file, "\n");
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lf_indent_suppress (file);
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lf_printf (file, "#if defined (ENGINE_ISSUE_POSTFIX_HOOK)\n");
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lf_printf (file, "ENGINE_ISSUE_POSTFIX_HOOK();\n");
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lf_indent_suppress (file);
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lf_printf (file, "#endif\n");
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lf_printf (file, "\n");
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}
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static void
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print_run_body (lf *file, const gen_entry *table)
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{
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/* Output the function to execute real code:
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Unfortunately, there are multiple cases to consider vis:
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<icache> X <smp>
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Consequently this function is written in multiple different ways */
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lf_printf (file, "{\n");
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lf_indent (file, +2);
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if (!options.gen.smp)
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{
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lf_printf (file, "%sinstruction_address cia;\n",
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options.module.global.prefix.l);
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}
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lf_printf (file, "int current_cpu = next_cpu_nr;\n");
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if (options.gen.icache)
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{
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lf_printf (file, "/* flush the icache of a possible break insn */\n");
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lf_printf (file, "{\n");
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lf_printf (file, " int cpu_nr;\n");
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lf_printf (file, " for (cpu_nr = 0; cpu_nr < nr_cpus; cpu_nr++)\n");
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lf_printf (file, " cpu_flush_icache (STATE_CPU (sd, cpu_nr));\n");
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lf_printf (file, "}\n");
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}
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if (!options.gen.smp)
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{
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lf_putstr (file, "\
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/* CASE 1: NO SMP (with or with out instruction cache).\n\
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\n\
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In this case, we can take advantage of the fact that the current\n\
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instruction address (CIA) does not need to be read from / written to\n\
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the CPU object after the execution of an instruction.\n\
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\n\
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Instead, CIA is only saved when the main loop exits. This occures\n\
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when either sim_engine_halt or sim_engine_restart is called. Both of\n\
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these functions save the current instruction address before halting /\n\
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restarting the simulator.\n\
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\n\
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As a variation, there may also be support for an instruction cracking\n\
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cache. */\n\
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\n\
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");
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lf_putstr (file, "\n");
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lf_putstr (file, "/* prime the main loop */\n");
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lf_putstr (file, "SIM_ASSERT (current_cpu == 0);\n");
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lf_putstr (file, "SIM_ASSERT (nr_cpus == 1);\n");
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lf_putstr (file, "cia = CPU_PC_GET (CPU);\n");
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lf_putstr (file, "\n");
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lf_putstr (file, "while (1)\n");
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lf_putstr (file, " {\n");
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lf_indent (file, +4);
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lf_printf (file, "%sinstruction_address nia;\n",
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options.module.global.prefix.l);
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lf_printf (file, "\n");
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if (!options.gen.icache)
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{
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lf_printf (file,
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"%sinstruction_word instruction_0 = IMEM%d (cia);\n",
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options.module.global.prefix.l, options.insn_bit_size);
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print_engine_issue_prefix_hook (file);
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print_idecode_body (file, table, "nia = ");
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print_engine_issue_postfix_hook (file);
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}
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else
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{
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lf_putstr (file, "idecode_cache *cache_entry =\n");
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lf_putstr (file, " cpu_icache_entry (cpu, cia);\n");
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lf_putstr (file, "if (cache_entry->address == cia)\n");
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lf_putstr (file, " {\n");
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lf_indent (file, -4);
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lf_putstr (file, "/* cache hit */\n");
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lf_putstr (file,
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"idecode_semantic *const semantic = cache_entry->semantic;\n");
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lf_putstr (file, "cia = semantic (cpu, cache_entry, cia);\n");
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/* tail */
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lf_indent (file, -4);
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lf_putstr (file, " }\n");
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lf_putstr (file, "else\n");
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lf_putstr (file, " {\n");
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lf_indent (file, +4);
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lf_putstr (file, "/* cache miss */\n");
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if (!options.gen.semantic_icache)
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{
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lf_putstr (file, "idecode_semantic *semantic;\n");
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}
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lf_printf (file, "instruction_word instruction = IMEM%d (cia);\n",
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options.insn_bit_size);
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lf_putstr (file, "if (WITH_MON != 0)\n");
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lf_putstr (file,
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" mon_event (mon_event_icache_miss, cpu, cia);\n");
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if (options.gen.semantic_icache)
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{
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lf_putstr (file, "{\n");
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lf_indent (file, +2);
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print_engine_issue_prefix_hook (file);
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print_idecode_body (file, table, "nia =");
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print_engine_issue_postfix_hook (file);
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lf_indent (file, -2);
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lf_putstr (file, "}\n");
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}
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else
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{
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print_engine_issue_prefix_hook (file);
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print_idecode_body (file, table, "semantic =");
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lf_putstr (file, "nia = semantic (cpu, cache_entry, cia);\n");
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print_engine_issue_postfix_hook (file);
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}
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lf_indent (file, -4);
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lf_putstr (file, " }\n");
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}
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/* update the cpu if necessary */
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switch (options.gen.nia)
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{
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case nia_is_cia_plus_one:
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lf_printf (file, "\n");
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lf_printf (file, "/* Update the instruction address */\n");
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lf_printf (file, "cia = nia;\n");
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break;
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case nia_is_void:
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case nia_is_invalid:
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ERROR ("engine gen when NIA complex");
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}
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/* events */
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lf_putstr (file, "\n");
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lf_putstr (file, "/* process any events */\n");
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lf_putstr (file, "if (sim_events_tick (sd))\n");
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lf_putstr (file, " {\n");
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lf_putstr (file, " CPU_PC_SET (CPU, cia);\n");
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lf_putstr (file, " sim_events_process (sd);\n");
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lf_putstr (file, " cia = CPU_PC_GET (CPU);\n");
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lf_putstr (file, " }\n");
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lf_indent (file, -4);
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lf_printf (file, " }\n");
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}
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if (options.gen.smp)
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{
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lf_putstr (file, "\
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/* CASE 2: SMP (With or without ICACHE)\n\
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\n\
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The complexity here comes from needing to correctly halt the simulator\n\
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when it is aborted. For instance, if cpu0 requests a restart then\n\
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cpu1 will normally be the next cpu that is run. Cpu0 being restarted\n\
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after all the other CPU's and the event queue have been processed */\n\
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\n\
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");
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lf_putstr (file, "\n");
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lf_printf (file,
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"/* have ensured that the event queue is NOT next */\n");
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lf_printf (file, "SIM_ASSERT (current_cpu >= 0);\n");
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lf_printf (file, "SIM_ASSERT (current_cpu <= nr_cpus - 1);\n");
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lf_printf (file, "SIM_ASSERT (nr_cpus <= MAX_NR_PROCESSORS);\n");
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lf_putstr (file, "\n");
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lf_putstr (file, "while (1)\n");
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lf_putstr (file, " {\n");
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lf_indent (file, +4);
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lf_putstr (file, "sim_cpu *cpu = STATE_CPU (sd, current_cpu);\n");
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lf_putstr (file, "instruction_address cia = CPU_PC_GET (cpu);\n");
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lf_putstr (file, "\n");
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if (!options.gen.icache)
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{
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lf_printf (file, "instruction_word instruction_0 = IMEM%d (cia);\n",
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options.insn_bit_size);
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print_engine_issue_prefix_hook (file);
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print_idecode_body (file, table, "cia =");
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lf_putstr (file, "CPU_PC_SET (cpu, cia);\n");
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print_engine_issue_postfix_hook (file);
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}
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if (options.gen.icache)
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{
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lf_putstr (file, "engine_cache *cache_entry =\n");
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lf_putstr (file, " cpu_icache_entry(processor, cia);\n");
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lf_putstr (file, "\n");
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lf_putstr (file, "if (cache_entry->address == cia) {\n");
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{
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lf_indent (file, +2);
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lf_putstr (file, "\n");
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lf_putstr (file, "/* cache hit */\n");
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lf_putstr (file,
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"engine_semantic *semantic = cache_entry->semantic;\n");
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lf_putstr (file,
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"cia = semantic(processor, cache_entry, cia);\n");
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/* tail */
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lf_putstr (file, "cpu_set_program_counter(processor, cia);\n");
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lf_putstr (file, "\n");
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lf_indent (file, -2);
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}
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lf_putstr (file, "}\n");
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lf_putstr (file, "else {\n");
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{
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lf_indent (file, +2);
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lf_putstr (file, "\n");
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lf_putstr (file, "/* cache miss */\n");
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if (!options.gen.semantic_icache)
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{
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lf_putstr (file, "engine_semantic *semantic;\n");
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}
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lf_printf (file, "instruction_word instruction = IMEM%d (cia);\n",
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options.insn_bit_size);
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lf_putstr (file, "if (WITH_MON != 0)\n");
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lf_putstr (file,
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" mon_event(mon_event_icache_miss, processors[current_cpu], cia);\n");
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if (options.gen.semantic_icache)
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{
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lf_putstr (file, "{\n");
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lf_indent (file, +2);
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print_engine_issue_prefix_hook (file);
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print_idecode_body (file, table, "cia =");
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print_engine_issue_postfix_hook (file);
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lf_indent (file, -2);
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lf_putstr (file, "}\n");
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}
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else
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{
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print_engine_issue_prefix_hook (file);
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print_idecode_body (file, table, "semantic = ");
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lf_putstr (file,
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"cia = semantic(processor, cache_entry, cia);\n");
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print_engine_issue_postfix_hook (file);
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}
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/* tail */
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lf_putstr (file, "cpu_set_program_counter(processor, cia);\n");
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lf_putstr (file, "\n");
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lf_indent (file, -2);
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}
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lf_putstr (file, "}\n");
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}
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lf_putstr (file, "\n");
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lf_putstr (file, "current_cpu += 1;\n");
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lf_putstr (file, "if (current_cpu == nr_cpus)\n");
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lf_putstr (file, " {\n");
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lf_putstr (file, " if (sim_events_tick (sd))\n");
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lf_putstr (file, " {\n");
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lf_putstr (file, " sim_events_process (sd);\n");
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lf_putstr (file, " }\n");
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lf_putstr (file, " current_cpu = 0;\n");
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lf_putstr (file, " }\n");
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/* tail */
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lf_indent (file, -4);
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lf_putstr (file, " }\n");
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}
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lf_indent (file, -2);
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lf_putstr (file, "}\n");
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}
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/****************************************************************/
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void
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print_engine_run_function_header (lf *file,
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const char *processor,
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function_decl_type decl_type)
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{
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int indent;
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lf_printf (file, "\n");
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switch (decl_type)
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{
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case is_function_declaration:
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lf_print__function_type (file, "void", "INLINE_ENGINE", "\n");
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break;
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case is_function_definition:
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lf_print__function_type (file, "void", "INLINE_ENGINE", " ");
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break;
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case is_function_variable:
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lf_printf (file, "void (*");
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break;
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}
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indent = print_function_name (file, "run", NULL, /* format name */
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processor, NULL, /* expanded bits */
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function_name_prefix_engine);
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switch (decl_type)
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{
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case is_function_definition:
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lf_putstr (file, "\n(");
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indent = 1;
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break;
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case is_function_declaration:
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indent += lf_printf (file, " (");
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break;
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case is_function_variable:
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lf_putstr (file, ")\n(");
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indent = 1;
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break;
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}
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lf_indent (file, +indent);
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lf_printf (file, "SIM_DESC sd,\n");
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lf_printf (file, "int next_cpu_nr,\n");
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lf_printf (file, "int nr_cpus,\n");
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lf_printf (file, "int siggnal)");
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lf_indent (file, -indent);
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switch (decl_type)
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{
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case is_function_definition:
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lf_putstr (file, "\n");
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break;
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case is_function_variable:
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case is_function_declaration:
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lf_putstr (file, ";\n");
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break;
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}
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}
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void
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gen_engine_h (lf *file,
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const gen_table *gen,
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const insn_table *isa,
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cache_entry *cache_rules)
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{
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gen_list *entry;
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for (entry = gen->tables; entry != NULL; entry = entry->next)
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{
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print_engine_run_function_header (file,
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(options.gen.multi_sim
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? entry->model->name
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: NULL), is_function_declaration);
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}
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}
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void
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gen_engine_c (lf *file,
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const gen_table *gen,
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const insn_table *isa,
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cache_entry *cache_rules)
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{
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const gen_list *entry;
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/* the intro */
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print_includes (file);
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print_include_inline (file, options.module.semantics);
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print_include (file, options.module.engine);
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lf_printf (file, "\n");
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lf_printf (file, "#include \"sim-assert.h\"\n");
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lf_printf (file, "\n");
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print_idecode_globals (file);
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lf_printf (file, "\n");
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for (entry = gen->tables; entry != NULL; entry = entry->next)
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{
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switch (options.gen.code)
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{
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case generate_calls:
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print_idecode_lookups (file, entry->table, cache_rules);
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/* output the main engine routine */
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print_engine_run_function_header (file,
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(options.gen.multi_sim
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? entry->model->name
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: NULL), is_function_definition);
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print_run_body (file, entry->table);
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break;
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case generate_jumps:
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ERROR ("Jumps currently unimplemented");
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break;
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}
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}
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}
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