Richard Earnshaw 687dd74c9b arm: don't treat XScale features as part of the FPU [PR 28031] ...

Although the XScale and its iwMMX extensions are implemented in the
Arm co-processor space, they are not considered to be part of the FPU
specification.  In particular, they cannot be enabled or disabled via
a .fpu directive.  It's therefore incorrect to strip these properties
when a new .fpu directive is encountered.

Note that the legacy Maverick co-processor is considered to be a FPU
and it is possible to control this via the .fpu directive.

include:

	PR gas/28031
	* opcode/arm.h (FPU_ANY): Exclude XScale-related features.

2021-07-01 17:47:11 +01:00

..

aarch64.h

aarch64: Remove support for CSRE

2021-01-11 15:03:13 +00:00

alpha.h

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arc-attrs.h

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arc-func.h

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arc.h

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arm.h

arm: don't treat XScale features as part of the FPU [PR 28031]

2021-07-01 17:47:11 +01:00

avr.h

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bfin.h

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cgen.h

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ChangeLog-0415

binutils ChangeLog rotation

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ChangeLog-9103

Add copyright notices

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convex.h

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cr16.h

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cris.h

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crx.h

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csky.h

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d10v.h

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d30v.h

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dlx.h

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ft32.h

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h8300.h

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hppa.h

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i386.h

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ia64.h

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m68hc11.h

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m68k.h

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metag.h

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mips.h

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mmix.h

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mn10200.h

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mn10300.h

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moxie.h

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msp430-decode.h

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msp430.h

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nds32.h

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nfp.h

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nios2.h

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nios2r1.h

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nios2r2.h

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np1.h

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ns32k.h

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pdp11.h

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pj.h

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pn.h

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ppc.h

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pru.h

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pyr.h

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riscv-opc.h

RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instructions.

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riscv.h

RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instructions.

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rl78.h

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rx.h

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s12z.h

Enable building the s12z target on Solaris hosts where REG_Y is defined in system header files.

2020-01-02 12:04:40 +00:00

s390.h

IBM Z: Implement instruction set extensions

2021-02-19 14:19:12 +01:00

score-datadep.h

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score-inst.h

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sparc.h

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spu-insns.h

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spu.h

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tic4x.h

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tic6x-control-registers.h

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tic6x-insn-formats.h

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tic6x-opcode-table.h

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tic6x.h

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tic30.h

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tic54x.h

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tilegx.h

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tilepro.h

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v850.h

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vax.h

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visium.h

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wasm.h

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xgate.h

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