Commit Graph

3 Commits

Author SHA1 Message Date
Mike Frysinger
f4fdd84587 sim: fully merge sim_state_base into sim_state
Now that all ports have migrated to the new framework, drop support
for the old sim_state_base layout.
2021-05-17 01:05:08 -04:00
Mike Frysinger
10c23a2c6f sim: riscv: invert sim_state storage 2021-05-17 01:02:09 -04:00
Mike Frysinger
b9249c461c sim: riscv: new port
This is a hand-written implementation that should have fairly complete
coverage for the base integer instruction set ("i"), and for the atomic
("a") and integer multiplication+division ("m") extensions.  It also
covers 32-bit & 64-bit targets.

The unittest coverage is a bit weak atm, but should get better.
2021-02-04 19:02:19 -05:00