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775 Commits

Author SHA1 Message Date
Maciej W. Rozycki
62fd0a980b MIPS/GAS: Remove a stale OPTION_COMPAT_ARCH_BASE option marker 
Complement commit 23fce1e311 ("MIPS16 intermix test failure"),
<https://sourceware.org/ml/binutils/2009-01/msg00335.html>, and
remove a stale option marker entry.

	gas/
	* config/tc-mips.c (options): Remove OPTION_COMPAT_ARCH_BASE
	enum value.
 2018-01-23 19:01:35 +00:00
Maciej W. Rozycki
b4f6242e95 MIPS/GAS: Correct as --help' always reporting o32' as the default ABI 
Remove an issue with `as --help' always reporting `o32' as the default
ABI regardless of what the default actually is, originally caused by
commit cac012d6d3 ("check mips abi x linker emulation compatibility"),
<https://sourceware.org/ml/binutils/2003-05/msg00187.html> missing an
update here.

	gas/
	* config/tc-mips.c (md_show_usage): Correctly indicate the
	configuration-specific default ABI.
 2018-01-23 14:51:22 +00:00
Maciej W. Rozycki
f866b262e8 MIPS/GAS: Add missing -mmips16e2'/-mno-mips16e2' help text 
Correct a commit 25499ac7ee ("MIPS16e2: Add MIPS16e2 ASE support") GAS
bug and add missing help text for the `-mmips16e2' and `-mno-mips16e2'
options added with said commit.

	gas/
	* config/tc-mips.c (md_show_usage): Report `-mmips16e2' and
	`-mno-mips16e2' options.
 2018-01-23 14:51:22 +00:00
Alan Modra
219d1afa89 Update year range in copyright notice of binutils files 2018-01-03 17:49:56 +10:30
Maciej W. Rozycki
defc8e2b35 MIPS: Preset EF_MIPS_ABI2 with n32 ELF objects 
Fix a bug in MIPS n32 ELF object file generation and make such objects
consistent with the n32 BFD requested, by presetting the EF_MIPS_ABI2
flag in the `e_flags' member of the newly created ELF file header, as it
is this flag that tells n32 objects apart from o32 objects.

This flag will then stay set through to output file generation for
writers such as GAS or GDB's `generate-core-file' command.  Readers will
overwrite the whole of `e_flags' along with the rest of the ELF file
header in `elf_swap_ehdr_in' and then verify in `mips_elf_n32_object_p'
that the flag is still set before accepting an input file as an n32
object.

The issue was discovered with GDB's `generate-core-file' command making
o32 core files out of n32 debuggees.

	bfd/
	* elfn32-mips.c (mips_elf_n32_mkobject): New prototype and
	function.
	(bfd_elf32_mkobject): Use `mips_elf_n32_mkobject' rather than
	`_bfd_mips_elf_mkobject'.

	gas/
	* config/tc-mips.c (mips_elf_final_processing): Don't set
	EF_MIPS_ABI2 in `e_flags'.
 2017-10-23 15:39:46 +01:00
James Cowgill
42c0794e96 PR gas/21762: MIPS: Fix .stabs directive marking labels as MIPS16 
If a .stabs directive was used before another .set directive in a MIPS
source file, s_mips_stab would call mips_mark_labels without having
initialized the mips_opts structure yet.  Fix this by calling
file_mips_check_options which will initialize mips_opts if necessary.

gas/
	PR gas/21762
	* config/tc-mips.c (s_mips_stab): Insert call to
	file_mips_check_options.
	* testsuite/gas/mips/micromips@stabs-symbol-type.d: New test.
	* testsuite/gas/mips/mips.exp: Run the new tests.
	* testsuite/gas/mips/mips16@stabs-symbol-type.d: New test.
	* testsuite/gas/mips/stabs-symbol-type.d: New test.
	* testsuite/gas/mips/stabs-symbol-type.s: New test source.
 2017-09-22 00:54:19 +01:00
Maciej W. Rozycki
37b2d32751 MIPS/GAS: Also respect `-mignore-branch-isa' with MIPS16 code 
Fix a bug in commit 8b10b0b3e1 ("MIPS: Add options to control branch
ISA checks") and with the `-mignore-branch-isa' command-line option also
lift a GAS check for invalid MIPS16 branches between ISA modes, which is
made separately from regular MIPS and microMIPS checks.

	gas/
	* config/tc-mips.c (md_convert_frag): Respect
	`mips_ignore_branch_isa'.
	* testsuite/gas/mips/branch-local-5.d: New test.
	* testsuite/gas/mips/branch-local-n32-5.d: New test.
	* testsuite/gas/mips/branch-local-n64-5.d: New test.
	* testsuite/gas/mips/branch-local-6.d: New test.
	* testsuite/gas/mips/branch-local-n32-6.d: New test.
	* testsuite/gas/mips/branch-local-n64-6.d: New test.
	* testsuite/gas/mips/branch-local-7.d: New test.
	* testsuite/gas/mips/branch-local-n32-7.d: New test.
	* testsuite/gas/mips/branch-local-n64-7.d: New test.
	* testsuite/gas/mips/branch-local-ignore-5.d: New test.
	* testsuite/gas/mips/branch-local-ignore-n32-5.d: New test.
	* testsuite/gas/mips/branch-local-ignore-n64-5.d: New test.
	* testsuite/gas/mips/branch-local-ignore-6.d: New test.
	* testsuite/gas/mips/branch-local-ignore-n32-6.d: New test.
	* testsuite/gas/mips/branch-local-ignore-n64-6.d: New test.
	* testsuite/gas/mips/branch-local-5.l: New stderr output.
	* testsuite/gas/mips/branch-local-6.l: New stderr output.
	* testsuite/gas/mips/branch-local-5.s: New test source.
	* testsuite/gas/mips/branch-local-6.s: New test source.
	* testsuite/gas/mips/branch-local-7.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.
 2017-08-30 16:05:53 +01:00
Yuri Chornovian
de194d8575 Fix spelling typos. 2017-07-18 16:58:14 +01:00
Maciej W. Rozycki
834a65aadf MIPS/GAS: Use a switch on relaxation type in microMIPS fixup creation 
Use a switch on the relaxation type rather than a chain of conditionals
in microMIPS fixup creation, improving source code structure and aiding
the compiler with code generation.

	gas/
	* config/tc-mips.c (md_convert_frag): Use a switch on the
	microMIPS relaxation type rather than a chain of conditionals.
 2017-07-01 00:42:19 +01:00
Maciej W. Rozycki
bbd27b7684 MIPS/GAS: Use frag symbol/offset directly in fixup creation 
There is no need to use a helper expression in the creation of fixups
made from a frag's symbol and offset, because a simple `symbol+offset'
expression can be handled directly, with the use of a `fix_new' rather
than a `fix_new_exp' call.  Rewrite `md_convert_frag' using `fix_new'
then and remove all the unneeded helper expressions, simplifying code.

	gas/
	* config/tc-mips.c (md_convert_frag): Rewrite `fix_new_exp'
	calls in terms of `fix_new'.
 2017-07-01 00:42:19 +01:00
Maciej W. Rozycki
9f00292e69 MIPS/GAS: Use non-zero frag offset directly in PIC branch relaxation 
Use frag symbols with a non-zero offset directly in `fix_new_exp' calls
made in PIC branch relaxation.  There is no need here to make a helper
symbol to hold the result of a `symbol+offset' calculation requested as
only branches to local symbols are relaxed and in this case the LO16
part of the PIC address load sequence will have the offset accounted for
in calculation against the local GOT entry retrieved as the GOT16 high
part.  Consequently actual code produed is identical whether a helper
symbol is used or the original `symbol+offset' expression used directly.
Verify that this is indeed the case with GAS and LD tests.

	gas/
	* config/tc-mips.c (md_convert_frag): Don't make a helper
	expression symbol for `fix_new_exp' called with a non-zero
	offset.
	* testsuite/gas/mips/relax-offset.d: New test.
	* testsuite/gas/mips/mips1@relax-offset.d: New test.
	* testsuite/gas/mips/r3000@relax-offset.d: New test.
	* testsuite/gas/mips/r3900@relax-offset.d: New test.
	* testsuite/gas/mips/micromips@relax-offset.d: New test.
	* testsuite/gas/mips/relax-offset.l: New stderr output.
	* testsuite/gas/mips/relax-offset.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.

	ld/
	* testsuite/ld-mips-elf/relax-offset.dd: New test.
	* testsuite/ld-mips-elf/relax-offset.gd: New test.
	* testsuite/ld-mips-elf/relax-offset-umips.dd: New test.
	* testsuite/ld-mips-elf/relax-offset-umips.gd: New test.
	* testsuite/ld-mips-elf/relax-offset.ld: New test linker script.
	* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
	(prune_warnings): New temporary procedure.
 2017-07-01 00:42:19 +01:00
Maciej W. Rozycki
33f466961c MIPS/GAS: Update match_float_constant' and match_operand' descriptions 
Complement commit a92713e60e ("Preparse MIPS instructions into
tokens"), <https://sourceware.org/ml/binutils/2013-07/msg00143.html>,
and update `match_float_constant' and `match_operand' function
descriptions according to semantics changes.

	gas/
	* config/tc-mips.c (match_float_constant): Update description.
	(match_operand): Likewise.
 2017-06-30 15:40:36 +01:00
Maciej W. Rozycki
909b4e3d5f MIPS: Add microMIPS XPA support 
Add support for the base and Virtualization ASE microMIPS instructions
as per the architecture specifications[1][2][3][4].

Most of this change by Andrew Bennett.

[1] "MIPS Architecture for Programmers Volume II-B: The microMIPS32
    Instruction Set", MIPS Technologies, Inc., Document Number: MD00582,
    Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit
    Instructions", p. 340

[2] "microMIPS32 Architecture for Programmers Volume IV-i:
    Virtualization Module of the microMIPS32 Architecture", MIPS
    Technologies, Inc., Document Number: MD00848, Revision 1.06,
    December 10, 2013, Section 6.1 "Overview", pp. 133, 136

[3] "MIPS Architecture for Programmers Volume II-B: The microMIPS64
    Instruction Set", MIPS Technologies, Inc., Document Number: MD00594,
    Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit
    Instructions", pp. 415, 444

[4] "microMIPS64 Architecture for Programmers Volume IV-i:
    Virtualization Module of the microMIPS64 Architecture", MIPS
    Technologies, Inc., Document Number: MD00849, Revision 1.06,
    December 10, 2013, Section 6.1 "Overview", pp. 134-135, 139-140

	binutils/
	* NEWS: Mention microMIPS XPA support.

	opcodes/
	* micromips-opc.c (XPA, XPAVZ): New macros.
	(micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
	"mthgc0".

	gas/
	* config/tc-mips.c (mips_ases): Add microMIPS XPA support.
	* testsuite/gas/mips/micromips@xpa.d: New test.
	* testsuite/gas/mips/mips.exp: Run the new test.  Enable
	`xpa-virt-err' test for `micromips'.
 2017-06-30 07:21:56 +01:00
Maciej W. Rozycki
9785fc2a4d MIPS: Fix XPA base and Virtualization ASE instruction handling 
Correct a commit 7d64c587c1 ("Add support for the MIPS eXtended
Physical Address (XPA) ASE.") bug, causing XPA base and Virtualization
ASE instructions to be wrongly always enabled with the selection of the
MIPS32r2 or higher ISA.

For example this source assembles successfully as shown below:

$ cat xpa.s
	mfhc0	$2, $1
$ as -32 -mips32 -o xpa.o xpa.s
xpa.s: Assembler messages:
xpa.s:1: Error: opcode not supported on this processor: mips32 (mips32) `mfhc0 $2,$1'
$ as -32 -mips32r2 -o xpa.o xpa.s
$ objdump -d xpa.o

xpa.o:     file format elf32-tradbigmips

Disassembly of section .text:

00000000 <.text>:
   0:	40420800 	mfhc0	v0,c0_random
	...
$

To address this issue remove the I33 (INSN_ISA32R2) marking from all XPA
instructions in the opcode table.  Additionally, for XPA Virtualization
ASE instructions implement an XPAVZ (ASE_XPA_VIRT) combination ASE flag
and use it in place of IVIRT|XPA (ASE_VIRT|ASE_XPA).

Now the same source is correctly rejected unless the `-mxpa' option is
also used:

$ as -32 -mips32r2 -o xpa.o xpa.s
xpa.s: Assembler messages:
xpa.s:1: Error: opcode not supported on this processor: mips32r2 (mips32r2) `mfhc0 $2,$1'
$ as -32 -mips32r2 -mxpa -o xpa.o xpa.s
$

Add test cases for XPA base and XPA Virtualization ASE instructions.

Parts of this change by Andrew Bennett.

	include/
	* opcode/mips.h (ASE_XPA_VIRT): New macro.

	opcodes/
	* mips-dis.c (mips_calculate_combination_ases): Handle the
	ASE_XPA_VIRT flag.
	(parse_mips_ase_option): New function.
	(parse_mips_dis_option): Factor out ASE option handling to the
	new function.  Call `mips_calculate_combination_ases'.
	* mips-opc.c (XPAVZ): New macro.
	(mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
	"mfhgc0", "mthc0" and "mthgc0".

	gas/
	* config/tc-mips.c (mips_set_ase): Handle the ASE_XPA_VIRT flag.
	* testsuite/gas/mips/xpa.d: Remove `xpa' from `-M' in `objdump'
	flags.  Add `-mvirt' to `as' flags.
	* testsuite/gas/mips/xpa-err.d: New test.
	* testsuite/gas/mips/xpa-virt-err.d: New test.
	* testsuite/gas/mips/xpa-err.l: New stderr output.
	* testsuite/gas/mips/xpa-virt-err.l: New stderr output.
	* testsuite/gas/mips/xpa-err.s: New test source.
	* testsuite/gas/mips/xpa-virt-err.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.

	binutils/
	* testsuite/binutils-all/mips/mips-xpa-virt-1.d: New test.
	* testsuite/binutils-all/mips/mips-xpa-virt-2.d: New test.
	* testsuite/binutils-all/mips/mips-xpa-virt-3.d: New test.
	* testsuite/binutils-all/mips/mips-xpa-virt-4.d: New test.
	* testsuite/binutils-all/mips/mips-xpa-virt.s: New test source.
	* testsuite/binutils-all/mips/mips.exp: Run the new tests.
 2017-06-30 07:21:55 +01:00
Maciej W. Rozycki
92cebb3dbe MIPS/GAS: Clear the ASE_MIPS16E2_MT flag for recalculation 
Correct a commit 25499ac7ee ("MIPS16e2: Add MIPS16e2 ASE support") GAS
bug with the handling of the ASE_MIPS16E2_MT combination ASE flag, which
is not correctly calculated as `.set nomips16e2' and `.set nomt'
pseudo-ops are processed.  This leads to code like:

$ cat foo.s
	.set	nomt
	evpe
	.align	4, 0
$ cat bar.s
	.set	nomips16e2
	dvpe
	.align	4, 0
$

to successfully assemble where it should not:

$ as -32 -mips32r3 -mmt -mips16 -mmips16e2 -o foo.o foo.s
$ as -32 -mips32r3 -mmt -mips16 -mmips16e2 -o bar.o bar.s
$ objdump -m mips:16 -d foo.o

foo.o:     file format elf32-tradbigmips

Disassembly of section .text:

00000000 <.text>:
   0:	f027 6700 	evpe
	...

bar.o:     file format elf32-tradbigmips

Disassembly of section .text:

00000000 <.text>:
   0:	f026 6700 	dvpe
	...
$

This happens because ASE_MIPS16E2_MT once set in `mips_set_ase' is never
cleared.  Fix the problem by clearing it there before it is calculated
based on the ASE_MT and ASE_MIPS16E2 flags, making assembly fail as
expected:

$ as -32 -mips32r3 -mmt -mips16 -mmips16e2 -o foo.o foo.s
foo.s: Assembler messages:
foo.s:2: Error: opcode not supported on this processor: mips32r3 (mips32r3) `evpe'
$ as -32 -mips32r3 -mmt -mips16 -mmips16e2 -o bar.o bar.s
bar.s: Assembler messages:
bar.s:2: Error: opcode not supported on this processor: mips32r3 (mips32r3) `dvpe'
$

	gas/
	* config/tc-mips.c (mips_set_ase): Clear the ASE_MIPS16E2_MT
	flag before recalculating.
	* testsuite/gas/mips/mips16e2-mt-err.d: New test.
	* testsuite/gas/mips/mips16e2-mt-err.l: New stderr output.
	* testsuite/gas/mips/mips16e2-mt-err.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new test.
 2017-06-30 00:55:07 +01:00
Maciej W. Rozycki
38bf472a15 MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor support 
Add support for the Imagination interAptiv MR2 MIPS32r3 processor with
the MIPS16e2 ASE as per documentation, including in particular:

1. Support for implementation-specific interAptiv MR2 COPYW and UCOPYW
   MIPS16e2 instructions[1], for assembly and disassembly,

2. Support for implementation-specific interAptiv MR2 SAVE and RESTORE
   regular MIPS instructions[2], for assembly and disassembly,

3. ELF binary file annotation for the interAptiv MR2 MIPS architecture
   extension.

4. Support for interAptiv MR2 architecture selection for assembly, in
   the form of the `-march=interaptiv-mr2' command-line option and its
   corresponding `arch=interaptiv-mr2' setting for the `.set' and
   `.module' pseudo-ops.

5. Support for interAptiv MR2 architecture selection for disassembly,
   in the form of the `mips:interaptiv-mr2' target architecture, for
   use e.g. with the `-m' command-line option for `objdump'.

Parts of this change by Matthew Fortune and Andrew Bennett.

References:

[1] "MIPS32 interAptiv Multiprocessing System Software User's Manual",
    Imagination Technologies Ltd., Document Number: MD00904, Revision
    02.01, June 15, 2016, Section 24.3 "MIPS16e2 Implementation Specific
    Instructions", pp. 878-883

[2] same, Chapter 25 "Implementation-specific Instructions", pp. 911-917

	include/
	* elf/mips.h (E_MIPS_MACH_IAMR2): New macro.
	(AFL_EXT_INTERAPTIV_MR2): Likewise.
	* opcode/mips.h: Document new operand codes defined.
	(INSN_INTERAPTIV_MR2): New macro.
	(INSN_CHIP_MASK): Adjust accordingly.
	(CPU_INTERAPTIV_MR2): New macro.
	(cpu_is_member) <CPU_INTERAPTIV_MR2>: New case.
	(MIPS16_ALL_ARGS): Rename to...
	(MIPS_SVRS_ALL_ARGS): ... this.
	(MIPS16_ALL_STATICS): Rename to...
	(MIPS_SVRS_ALL_STATICS): ... this.

	bfd/
	* archures.c (bfd_mach_mips_interaptiv_mr2): New macro.
	* cpu-mips.c (I_interaptiv_mr2): New enum value.
	(arch_info_struct): Add "mips:interaptiv-mr2" entry.
	* elfxx-mips.c (_bfd_elf_mips_mach) <E_MIPS_MACH_IAMR2>: New
	case.
	(mips_set_isa_flags) <bfd_mach_mips_interaptiv_mr2>: Likewise.
	(bfd_mips_isa_ext) <bfd_mach_mips_interaptiv_mr2>: Likewise.
	(print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise.
	(mips_mach_extensions): Add `bfd_mach_mipsisa32r3' and
	`bfd_mach_mips_interaptiv_mr2' entries.
	* bfd-in2.h: Regenerate.

	opcodes/
	* mips-formats.h (INT_BIAS): New macro.
	(INT_ADJ): Redefine in INT_BIAS terms.
	* mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
	(mips_print_save_restore): New function.
	(print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
	(validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
	call.
	(print_insn_args): Handle OP_SAVE_RESTORE_LIST.
	(print_mips16_insn_arg): Call `mips_print_save_restore' for
	OP_SAVE_RESTORE_LIST handling, factored out from here.
	* mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
	(RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
	(mips_builtin_opcodes): Add "restore" and "save" entries.
	* mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
	(IAMR2): New macro.
	(mips16_opcodes): Add "copyw" and "ucopyw" entries.

	binutils/
	* readelf.c (get_machine_flags) <E_MIPS_MACH_IAMR2>: New case.
	(print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise.
	* NEWS: Mention Imagination interAptiv MR2 processor support.

	gas/
	* config/tc-mips.c (validate_mips_insn): Handle
	OP_SAVE_RESTORE_LIST specially.
	(mips_encode_save_restore, mips16_encode_save_restore): New
	functions.
	(match_save_restore_list_operand): Factor out SAVE/RESTORE
	operand insertion into the instruction word or halfword to these
	new functions.
	(mips_cpu_info_table): Add "interaptiv-mr2" entry.

	* doc/c-mips.texi (MIPS Options): Add `interaptiv-mr2' to the
	`-march=' argument list.
 2017-06-28 02:07:36 +01:00
Alan Modra
535b785fb0 Don't compare boolean values against TRUE or FALSE 
bfd/
	* arc-got.h: Don't compare boolean values against TRUE or FALSE.
	* elf-m10300.c: Likewise.
	* elf.c: Likewise.
	* elf32-arc.c: Likewise.
	* elf32-bfin.c: Likewise.
	* elf32-m68k.c: Likewise.
	* elf32-nds32.c: Likewise.
	* elf32-tilepro.c: Likewise.
	* elflink.c: Likewise.
	* elfnn-aarch64.c: Likewise.
	* elfnn-riscv.c: Likewise.
	* elfxx-tilegx.c: Likewise.
	* mach-o.c: Likewise.
	* peXXigen.c: Likewise.
	* vms-alpha.c: Likewise.
	* vms-lib.c: Likewise.
opcodes/
	* aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
	* aarch64-dis.c: Likewise.
	* aarch64-gen.c: Likewise.
	* aarch64-opc.c: Likewise.
binutils/
	* strings.c: Don't compare boolean values against TRUE or FALSE.
gas/
	* config/tc-aarch64.c: Don't compare booleans against TRUE or FALSE.
	* config/tc-hppa.c: Likewise.
	* config/tc-mips.c: Likewise.
	* config/tc-score7.c: Likewise.
ld/
	* emultempl/elf32.em: Don't compare boolean values against TRUE or FALSE.
	* emultempl/pe.em: Likewise.
	* emultempl/pep.em: Likewise.
	* emultempl/xtensaelf.em: Likewise.
 2017-05-18 14:59:33 +09:30
Maciej W. Rozycki
25499ac7ee MIPS16e2: Add MIPS16e2 ASE support 
Add MIPS16e2 ASE support as per the architecture specification[1],
including in particular:

1. A new ELF ASE flag to mark MIPS16e2 binaries.

2. MIPS16e2 instruction assembly support, including a relaxation update
   to use LUI rather than an LI/SLL instruction pair for loading the
   high part of 32-bit addresses.

3. MIPS16e2 instruction disassembly support, including updated rules for
   extended forms of instructions that are now subdecoded and therefore
   do not alias to the original MIPS16 ISA revision instructions even
   for encodings that are not valid in the MIPS16e2 instruction set.

Add `-mmips16e2' and `-mno-mips16e2' GAS command-line options and their
corresponding `mips16e2' and `no-mips16e2' settings for the `.set' and
`.module' pseudo-ops.  Control the availability of the MT ASE subset of
the MIPS16e2 instruction set with a combination of these controls and
the preexisting MT ASE controls.

Parts of this change by Matthew Fortune and Andrew Bennett.

References:

[1] "MIPS32 Architecture for Programmers: MIPS16e2 Application-Specific
    Extension Technical Reference Manual", Imagination Technologies
    Ltd., Document Number: MD01172, Revision 01.00, April 26, 2016

	include/
	* elf/mips.h (AFL_ASE_MIPS16E2): New macro.
	(AFL_ASE_MASK): Adjust accordingly.
	* opcode/mips.h: Document new operand codes defined.
	(mips_operand_type): Add OP_REG28 enum value.
	(INSN2_SHORT_ONLY): Update description.
	(ASE_MIPS16E2, ASE_MIPS16E2_MT): New macros.

	bfd/
	* elfxx-mips.c (print_mips_ases): Handle MIPS16e2 ASE.

	opcodes/
	* mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
	ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
	(mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
	(print_insn_arg) <OP_REG28>: Add handler.
	(validate_insn_args) <OP_REG28>: Handle.
	(print_mips16_insn_arg): Handle MIPS16 instructions that require
	32-bit encoding and 9-bit immediates.
	(print_insn_mips16): Handle MIPS16 instructions that require
	32-bit encoding and MFC0/MTC0 operand decoding.
	* mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
	<'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
	(RD_C0, WR_C0, E2, E2MT): New macros.
	(mips16_opcodes): Add entries for MIPS16e2 instructions:
	GP-relative "addiu" and its "addu" spelling, "andi", "cache",
	"di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
	"lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
	"movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
	"pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
	instructions, "swl", "swr", "sync" and its "sync_acquire",
	"sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
	"xori", "dmt", "dvpe", "emt" and "evpe".  Add split
	regular/extended entries for original MIPS16 ISA revision
	instructions whose extended forms are subdecoded in the MIPS16e2
	ISA revision: "li", "sll" and "srl".

	binutils/
	* readelf.c (print_mips_ases): Handle MIPS16e2 ASE.
	* NEWS: Mention MIPS16e2 ASE support.

	gas/
	* config/tc-mips.c (RELAX_MIPS16_ENCODE): Add `e2' flag.
	(RELAX_MIPS16_E2): New macro.
	(RELAX_MIPS16_PIC, RELAX_MIPS16_SYM32, RELAX_MIPS16_NOMACRO)
	(RELAX_MIPS16_USER_SMALL, RELAX_MIPS16_USER_EXT)
	(RELAX_MIPS16_DSLOT, RELAX_MIPS16_JAL_DSLOT)
	(RELAX_MIPS16_EXTENDED, RELAX_MIPS16_MARK_EXTENDED)
	(RELAX_MIPS16_CLEAR_EXTENDED, RELAX_MIPS16_ALWAYS_EXTENDED)
	(RELAX_MIPS16_MARK_ALWAYS_EXTENDED)
	(RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED, RELAX_MIPS16_MACRO)
	(RELAX_MIPS16_MARK_MACRO, RELAX_MIPS16_CLEAR_MACRO): Shift bits.
	(mips16_immed_extend): New prototype.
	(options): Add OPTION_MIPS16E2 and OPTION_NO_MIPS16E2 enum
	values.
	(md_longopts): Add "mmips16e2" and "mno-mips16e2" options.
	(mips_ases): Add "mips16e2" entry.
	(mips_set_ase): Handle MIPS16e2 ASE.
	(insn_insert_operand): Explicitly handle immediates with MIPS16
	instructions that require 32-bit encoding.
	(is_opcode_valid_16): Pass enabled ASE bitmask on to
	`opcode_is_member'.
	(validate_mips_insn): Explicitly handle immediates with MIPS16
	instructions that require 32-bit encoding.
	(operand_reg_mask) <OP_REG28>: Add handler.
	(match_reg28_operand): New function.
	(match_operand) <OP_REG28>: Add handler.
	(append_insn): Pass ASE_MIPS16E2 setting to RELAX_MIPS16_ENCODE.
	(match_mips16_insn): Handle MIPS16 instructions that require
	32-bit encoding and `V' and `u' operand codes.
	(mips16_ip): Allow any characters except from `.' in opcodes.
	(mips16_immed_extend): Handle 9-bit immediates.  Do not shuffle
	immediates whose width is not one of these listed.
	(md_estimate_size_before_relax): Handle MIPS16e2 relaxation.
	(mips_relax_frag): Likewise.
	(md_convert_frag): Likewise.
	(mips_convert_ase_flags): Handle MIPS16e2 ASE.

	* doc/as.texinfo (Target MIPS options): Add `-mmips16e2' and
	`-mno-mips16e2' options.
	(-mmips16e2, -mno-mips16e2): New options.
	* doc/c-mips.texi (MIPS Options): Add `-mmips16e2' and
	`-mno-mips16e2' options.
	(MIPS ASE Instruction Generation Overrides): Add `.set mips16e2'
	and `.set nomips16e2'.
 2017-05-15 13:57:10 +01:00
Maciej W. Rozycki
20c59b843a MIPS16/GAS: Improve [32768,65535] out-of-range operand error diagnostics 
Improve out-of-range operand error diagnostics for invalid values in the
[32768,65535] range used for a signed 16-bit immediate, making the
message consistent with that used for other invalid values, e.g.:

foo.s:1: Error: operand 2 must be an immediate expression `addiu $2,$gp,32768'
foo.s:2: Error: invalid operands `lw $2,32768($gp)'

vs:

foo.s:3: Error: operand 3 out of range `addiu $2,$gp,-32769'
foo.s:4: Error: operand 2 out of range `lw $2,-32769($gp)'

This case does not currently trigger however, for two reasons.

First, for regular MIPS and microMIPS assembly in the case of no match
caused by `match_int_operand' here, the function is always called again
from `mips_ip' via `match_insns', `match_insn' and then `match_operand'
for the same opcode table's entry with `lax_match' set to TRUE, in which
case the attempt to match succeeds and no error is issued.

Second, in the case of MIPS16 assembly no call to `match_int_operand' is
made at all for signed 16-bit immediates, because such immediates are
currently only matched with extensible instructions, and these are
handled in `match_mips16_insn' via `match_expression' directly rather
than via `match_operand'.

This will change for MIPS16 code with MIPS16e2 support introduced, where
non-extensible instructions accepting signed 16-bit immediates will be
added, so make the case work well right from the start:

foo.s:1: Error: operand 3 out of range `addiu $2,$gp,32768'
foo.s:2: Error: operand 2 out of range `lw $2,32768($gp)'

	gas/
	* config/tc-mips.c (match_int_operand): Call
	`match_out_of_range' before returning failure for 0x8000-0xffff
	values conditionally allowed.
 2017-05-15 13:57:10 +01:00
Maciej W. Rozycki
602b88e3ab MIPS16/GAS: Improve non-constant operand error diagnostics 
Improve operand error diagnostics for non-constant expressions used for
a 16-bit immediate, making the message more descriptive and indicating
the offending operand, e.g.:

foo.s:1: Error: invalid operands `lui $2,foo-bar'

will show as:

foo.s:1: Error: operand 2 must be constant `lui $2,foo-bar'

This case does not currently trigger however, for two reasons.

First, for regular MIPS and microMIPS assembly in the case of no match
caused by `match_int_operand' here, the function is always called again
from `mips_ip' via `match_insns', `match_insn' and then `match_operand'
for the same opcode table's entry with `lax_match' set to TRUE, in which
case the attempt to match succeeds and no error is issued.

Second, in the case of MIPS16 assembly no call to `match_int_operand' is
made at all for 16-bit immediates, because such immediates are currently
only matched with extensible instructions, and these are handled in
`match_mips16_insn' via `match_expression' directly rather than via
`match_operand'.

This will change for MIPS16 code with MIPS16e2 support introduced, where
non-extensible instructions accepting 16-bit immediates will be added,
so make the case work well right from the start.

	gas/
	* config/tc-mips.c (match_int_operand): Call
	`match_not_constant' before returning failure for a non-constant
	16-bit immediate conditionally allowed.
 2017-05-15 13:57:09 +01:00
Maciej W. Rozycki
c96425c560 MIPS/GAS: Improve bignum operand error diagnostics 
Improve bignum operand error diagnostics for cases where a constant
would be accepted and report them as range errors, also indicating the
offending operand and instruction, e.g.:

$ cat bignum.s
	addiu	$2, 0x10000000000000000
	break	0x10000000000000000
$ as -o bignum.o bignum.s
bignum.s:1: Error: bignum invalid
bignum.s:2: Error: operand 1 must be constant `break 0x10000000000000000'
$

now show as:

$ as -o bignum.o bignum.s
bignum.s:1: Error: operand 2 out of range `addiu $2,0x10000000000000000'
bignum.s:2: Error: operand 1 out of range `break 0x10000000000000000'
$

	gas/
	* config/tc-mips.c (match_const_int): Call `match_out_of_range'
	rather than `match_not_constant' for unrelocated operands
	retrieved as an `O_big' expression.
	(match_int_operand): Call `match_out_of_range' for relocatable
	operands retrieved as an `O_big' expression.
	(match_mips16_insn): Call `match_out_of_range' for relaxable
	operands retrieved as an `O_big' expression.
	* testsuite/gas/mips/addiu-error.d: New test.
	* testsuite/gas/mips/mips16@addiu-error.d: New test.
	* testsuite/gas/mips/micromips@addiu-error.d: New test.
	* testsuite/gas/mips/break-error.d: New test.
	* testsuite/gas/mips/lui-1.l: Adjust error message.
	* testsuite/gas/mips/addiu-error.l: New stderr output.
	* testsuite/gas/mips/mips16@addiu-error.l: New stderr output.
	* testsuite/gas/mips/micromips@addiu-error.l: New stderr output.
	* testsuite/gas/mips/break-error.l: New stderr output.
	* testsuite/gas/mips/addiu-error.s: New test source.
	* testsuite/gas/mips/break-error.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.
 2017-05-15 13:57:09 +01:00
Maciej W. Rozycki
1a7bf198b6 MIPS16/GAS: Improve non-immediate operand error diagnostics 
Improve non-immediate operand error diagnostics for extensible MIPS16
instructions and make it match corresponding regular MIPS and microMIPS
handling, e.g:

$ cat addiu.s
        addiu    $4, $3, $2
$ as -o addiu.o addiu.s
addiu.s: Assembler messages:
addiu.s:1: Error: operand 3 must be an immediate expression `addiu $4,$3,$2'
$ as -mips16 -o addiu.o addiu.s
addiu.s: Assembler messages:
addiu.s:1: Error: invalid operands `addiu $4,$3,$2'
$

To do so observe that for extensible MIPS16 instructions and a non-PC
relative operand this case is handled by an explicit OT_INTEGER check in
`match_mips16_insn' returning a failure right away and consequently
preventing a call to `match_expression' from being made.  As from commit
d436c1c2e8 ("Improve error reporting for register expressions"),
<https://sourceware.org/ml/binutils/2013-08/msg00134.html>, however the
check has become redundant as `match_expression' now only ever returns
success for OT_INTEGER argument tokens, and a special case of an OT_CHAR
`(' token already handled by `match_mips16_insn' just ahead of the
`match_expression' call.  Previously it also returned success for OT_REG
argument tokens.

Let the call to `match_expression' always happen then, yielding the same
failure for the affected cases, however with more accurate diagnostics
provided by the call making reporting consistent:

$ as -mips16 -o addiu.o addiu.s
addiu.s: Assembler messages:
addiu.s:1: Error: operand 3 must be an immediate expression `addiu $4,$3,$2'
$

	gas/
	* config/tc-mips.c (match_mips16_insn): Remove the explicit
	OT_INTEGER check before the `match_expression' call.
	* testsuite/gas/mips/mips16-insn-e.l: Adjust messages.
	* testsuite/gas/mips/mips16-32@mips16-insn-e.l: Likewise.
	* testsuite/gas/mips/mips16-64@mips16-insn-e.l: Likewise.
	* testsuite/gas/mips/mips16e-32@mips16-insn-e.l: Likewise.
	* testsuite/gas/mips/mips16-reg-error.d: New test.
	* testsuite/gas/mips/mips16-reg-error.l: New stderr output.
	* testsuite/gas/mips/mips16-reg-error.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new test.
 2017-05-15 13:57:08 +01:00
Maciej W. Rozycki
e295202f60 MIPS16/GAS: Improve disallowed relocation operand error diagnostics 
Improve disallowed relocation operand error diagnostics for MIPS16 code
and make it match corresponding regular MIPS and microMIPS handling,
e.g:

$ cat sltu.s
	sltu	$2, %lo(foo)
$ as -o sltu.o sltu.s
sltu.s: Assembler messages:
sltu.s:1: Error: operand 2 must be constant `sltu $2,%lo(foo)'
$ as -mips16 -o sltu.o sltu.s
sltu.s: Assembler messages:
sltu.s:1: Error: invalid operands `sltu $2,%lo(foo)'
$

To do so call `match_not_constant' from `match_mips16_insn' whenever a
disallowed relocation operation has been noticed, like `match_const_int'
does, making reporting consistent:

$ as -mips16 -o sltu.o sltu.s
sltu.s: Assembler messages:
sltu.s:1: Error: operand 2 must be constant `sltu $2,%lo(foo)'
$

	gas/
	* config/tc-mips.c (match_mips16_insn): Call
	`match_not_constant' for a disallowed relocation operation.
	* testsuite/gas/mips/mips16-reloc-error.d: New test.
	* testsuite/gas/mips/mips16-reloc-error.l: New stderr output.
	* testsuite/gas/mips/mips16-reloc-error.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new test.
 2017-05-15 13:57:08 +01:00
Maciej W. Rozycki
a54d5f8bb3 MIPS/GAS: Update `match_const_int' description 
Remove a stale reference to FALLBACK parameter from the description of
`match_const_int', matching commit 1a00e61226 ("Remove soft_match"),
<https://sourceware.org/ml/binutils/2013-08/msg00133.html>.

	gas/
	* config/tc-mips.c (match_const_int): Update description.
 2017-05-15 13:57:07 +01:00
Maciej W. Rozycki
be3f100674 MIPS/GAS: Unify GP-relative percent-ops 
For a reason that is unclear commit d6f1659387 ("Support for MIPS16
HI16/LO16 relocations"),
<https://sourceware.org/ml/binutils/2005-02/msg00332.html>, which has
added support for the R_MIPS16_GPREL relocation, has spelled its
corresponding MIPS16 percent-op as `%gprel', rather than `%gp_rel' which
is how its regular MIPS counterpart is spelled.  To make assembly code
sharing easier between the regular MIPS and the MIPS16 ISA make both
percent-op spellings acceptable in both kinds of code now.

Parts of this change by Matthew Fortune.

	gas/
	* config/tc-mips.c (mips_percent_op): Add "%gprel".
	(mips16_percent_op): Add "%gp_rel".
	* testsuite/gas/mips/elf-rel8.s:: Add `%gprel' forms.
	* testsuite/gas/mips/elf-rel8-mips16.s: Add `%gp_rel' forms.
	* testsuite/gas/mips/elf-rel8.d: Adjust accordingly.
	* testsuite/gas/mips/elf-rel8-mips16.d: Likewise.
 2017-05-12 02:34:56 +01:00
Maciej W. Rozycki
8507b6e797 MIPS16/GAS: Relax 32-bit non-PIC PC-relative synthetic instructions 
Implement the relaxation of MIPS16 PC-relative synthetic LA, DLA, LW and
LD instructions to an equivalent sequence of instructions produced where
the address operand requested is out of range, absolute or requires
linker relocation, for ABIs that use 32-bit addressing and non-PIC code.

The sequence generated uses the register specified for the destination
operand as a temporary and begins with LI to load the high 16-bit part
of the address, then continues with SLL by 16 bits to move that part
into place and finally completes with a suitable operation corresponding
to the synthetic instruction used, one of: 2-argument ADDIU, 2-argument
DADDIU, absolute LW, and absolute LD respectively, providing the low
16-bit part of the address.  All instructions use the extended encoding.
As a special exception accept absolute addresses for relaxation even in
PIC code.

For example:

	la	$2, 0x12345678

produces code as:

	li	$2, 0x1234
	sll	$2, $2, 16
	addiu	$2, 0x5678

would.

Where linker relocation is required emit an R_MIPS16_HI16 relocation on
the initial LI instruction and an R_MIPS16_LO16 relocation on the final
operation.

For example (where `foo' is not local):

	lw	$3, foo

produces code as:

	li	$3, %hi(foo)
	sll	$3, $3, 16
	lw	$3, %lo(foo)($3)

would.

Emit assembly warnings as appropriate where this new relaxation triggers
in the `nomacro' mode or for an instruction manually placed in a branch
delay slot in the `noreorder' mode.  Refrain from relaxation where an
explicit instruction size suffix has been used and in the `noautoextend'
mode.

	gas/
	* config/tc-mips.c (RELAX_MIPS16_ENCODE): Add `pic', `sym32' and
	`nomacro' flags.
	(RELAX_MIPS16_PIC, RELAX_MIPS16_SYM32, RELAX_MIPS16_NOMACRO):
	New macros.
	(RELAX_MIPS16_USER_SMALL, RELAX_MIPS16_USER_EXT)
	(RELAX_MIPS16_DSLOT, RELAX_MIPS16_JAL_DSLOT)
	(RELAX_MIPS16_EXTENDED, RELAX_MIPS16_MARK_EXTENDED)
	(RELAX_MIPS16_CLEAR_EXTENDED, RELAX_MIPS16_ALWAYS_EXTENDED)
	(RELAX_MIPS16_MARK_ALWAYS_EXTENDED)
	(RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED): Shift bits.
	(RELAX_MIPS16_MACRO, RELAX_MIPS16_MARK_MACRO)
	(RELAX_MIPS16_CLEAR_MACRO): New macros.
	(append_insn): Pass `mips_pic', HAVE_32BIT_SYMBOLS and
	`mips_opts.warn_about_macros' settings to RELAX_MIPS16_ENCODE.
	(mips16_macro_frag): New function.
	(md_estimate_size_before_relax): Handle HI16/LO16 relaxation.
	(mips_relax_frag): Likewise.
	(md_convert_frag): Likewise.

	* testsuite/gas/mips/mips16@relax-swap3.d: Remove error output,
	add dump patterns.
	* testsuite/gas/mips/mips16e@relax-swap3.d: New test
	subarchitecture.
	* testsuite/gas/mips/micromips@relax-swap3.d: Remove trailing
	NOP padding.
	* testsuite/gas/mips/mips16-pcrel-reloc-2.d: Remove error
	output, add dump patterns.
	* testsuite/gas/mips/mips16-pcrel-reloc-3.d: Remove error
	output, add dump patterns.
	* testsuite/gas/mips/mips16-pcrel-reloc-6.d: Remove error
	output, add dump patterns.
	* testsuite/gas/mips/mips16-pcrel-reloc-7.d: Remove error
	output, add dump patterns.
	* testsuite/gas/mips/mips16-pcrel-addend-2.d: Remove error
	output, add dump patterns.
	* testsuite/gas/mips/mips16-pcrel-addend-3.d: Remove error
	output, add dump patterns.
	* testsuite/gas/mips/mips16-pcrel-absolute.d: Remove error
	output, add dump patterns.
	* testsuite/gas/mips/mips16-pcrel-absolute-1.d: Remove error
	output, add dump patterns.
	* testsuite/gas/mips/mips16@relax-swap3.l: Remove file.
	* testsuite/gas/mips/mips16-pcrel-reloc-2.l: Remove file.
	* testsuite/gas/mips/mips16-pcrel-reloc-3.l: Remove file.
	* testsuite/gas/mips/mips16-pcrel-reloc-6.l: Remove file.
	* testsuite/gas/mips/mips16-pcrel-reloc-7.l: Remove file.
	* testsuite/gas/mips/mips16-pcrel-addend-2.l: Remove file.
	* testsuite/gas/mips/mips16-pcrel-addend-3.l: Remove file.
	* testsuite/gas/mips/mips16-pcrel-absolute.l: Remove file.
	* testsuite/gas/mips/mips16-pcrel-absolute-1.l: Remove file.
	* testsuite/gas/mips/relax-swap3.s: Adjust trailing padding.

	* testsuite/gas/mips/mips16-pcrel-0.d: New test.
	* testsuite/gas/mips/mips16-pcrel-1.d: New test.
	* testsuite/gas/mips/mips16-pcrel-2.d: New test.
	* testsuite/gas/mips/mips16-pcrel-3.d: New test.
	* testsuite/gas/mips/mips16-pcrel-4.d: New test.
	* testsuite/gas/mips/mips16-pcrel-5.d: New test.
	* testsuite/gas/mips/mips16-pcrel-pic-0.d: New test.
	* testsuite/gas/mips/mips16-pcrel-pic-1.d: New test.
	* testsuite/gas/mips/mips16-pcrel-n32-0.d: New test.
	* testsuite/gas/mips/mips16-pcrel-n32-1.d: New test.
	* testsuite/gas/mips/mips16-pcrel-n64-sym32-0.d: New test.
	* testsuite/gas/mips/mips16-pcrel-n64-sym32-1.d: New test.
	* testsuite/gas/mips/mips16-pcrel-n64-0.d: New test.
	* testsuite/gas/mips/mips16-pcrel-n64-1.d: New test.
	* testsuite/gas/mips/mips16-pcrel-delay-0.d: New test.
	* testsuite/gas/mips/mips16-pcrel-delay-1.d: New test.
	* testsuite/gas/mips/mips16-pcrel-addend-4.d: New test.
	* testsuite/gas/mips/mips16-pcrel-addend-5.d: New test.
	* testsuite/gas/mips/mips16-pcrel-addend-6.d: New test.
	* testsuite/gas/mips/mips16-pcrel-addend-7.d: New test.
	* testsuite/gas/mips/mips16-pcrel-addend-8.d: New test.
	* testsuite/gas/mips/mips16-pcrel-addend-9.d: New test.
	* testsuite/gas/mips/mips16-pcrel-addend-pic-8.d: New test.
	* testsuite/gas/mips/mips16-pcrel-addend-pic-9.d: New test.
	* testsuite/gas/mips/mips16-pcrel-addend-n32-8.d: New test.
	* testsuite/gas/mips/mips16-pcrel-addend-n32-9.d: New test.
	* testsuite/gas/mips/mips16-pcrel-addend-n64-sym32-8.d: New test.
	* testsuite/gas/mips/mips16-pcrel-addend-n64-sym32-9.d: New test.
	* testsuite/gas/mips/mips16-pcrel-addend-n64-8.d: New test.
	* testsuite/gas/mips/mips16-pcrel-addend-n64-9.d: New test.
	* testsuite/gas/mips/mips16-pcrel-absolute-2.d: New test.
	* testsuite/gas/mips/mips16-pcrel-absolute-3.d: New test.
	* testsuite/gas/mips/mips16-pcrel-absolute-4.d: New test.
	* testsuite/gas/mips/mips16-pcrel-absolute-5.d: New test.
	* testsuite/gas/mips/mips16-pcrel-absolute-6.d: New test.
	* testsuite/gas/mips/mips16-pcrel-absolute-7.d: New test.
	* testsuite/gas/mips/mips16-pcrel-absolute-pic-4.d: New test.
	* testsuite/gas/mips/mips16-pcrel-absolute-pic-6.d: New test.
	* testsuite/gas/mips/mips16-pcrel-absolute-n32-4.d: New test.
	* testsuite/gas/mips/mips16-pcrel-absolute-n32-6.d: New test.
	* testsuite/gas/mips/mips16-pcrel-absolute-n64-4.d: New test.
	* testsuite/gas/mips/mips16-pcrel-absolute-n64-6.d: New test.
	* testsuite/gas/mips/mips16-pcrel-absolute-n64-sym32-4.d: New
	test.
	* testsuite/gas/mips/mips16-pcrel-absolute-n64-sym32-6.d: New
	test.
	* testsuite/gas/mips/mips16-pcrel-absolute-pic-n32-4.d: New
	test.
	* testsuite/gas/mips/mips16-pcrel-absolute-pic-n32-6.d: New
	test.
	* testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-4.d: New
	test.
	* testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-6.d: New
	test.
	* testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-sym32-4.d:
	New test.
	* testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-sym32-6.d:
	New test.
	* testsuite/gas/mips/mips16-pcrel-0.l: New stderr output.
	* testsuite/gas/mips/mips16-pcrel-1.l: New stderr output.
	* testsuite/gas/mips/mips16-pcrel-2.l: New stderr output.
	* testsuite/gas/mips/mips16-pcrel-3.l: New stderr output.
	* testsuite/gas/mips/mips16-pcrel-4.l: New stderr output.
	* testsuite/gas/mips/mips16-pcrel-5.l: New stderr output.
	* testsuite/gas/mips/mips16-pcrel-delay-0.l: New stderr output.
	* testsuite/gas/mips/mips16-pcrel-delay-1.l: New stderr output.
	* testsuite/gas/mips/mips16-pcrel-addend-8.l: New stderr output.
	* testsuite/gas/mips/mips16-pcrel-addend-9.l: New stderr output.
	* testsuite/gas/mips/mips16-pcrel-absolute-4.l: New stderr
	output.
	* testsuite/gas/mips/mips16-pcrel-absolute-6.l: New stderr
	output.
	* testsuite/gas/mips/mips16-pcrel-0.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-1.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-2.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-3.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-4.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-5.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-delay-0.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-delay-1.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-addend-4.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-addend-5.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-addend-6.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-addend-7.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-addend-8.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-addend-9.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-absolute-2.s: New test.
	* testsuite/gas/mips/mips16-pcrel-absolute-3.s: New test.
	* testsuite/gas/mips/mips16-pcrel-absolute-4.s: New test.
	* testsuite/gas/mips/mips16-pcrel-absolute-5.s: New test.
	* testsuite/gas/mips/mips16-pcrel-absolute-6.s: New test.
	* testsuite/gas/mips/mips16-pcrel-absolute-7.s: New test.
	* testsuite/gas/mips/mips.exp: Run the new tests.

	ld/
	* testsuite/ld-mips-elf/mips16-pcrel-0.d: New test.
	* testsuite/ld-mips-elf/mips16-pcrel-1.d: New test.
	* testsuite/ld-mips-elf/mips16-pcrel-addend-2.d: New test.
	* testsuite/ld-mips-elf/mips16-pcrel-addend-6.d: New test.
	* testsuite/ld-mips-elf/mips16-pcrel-n32-0.d: New test.
	* testsuite/ld-mips-elf/mips16-pcrel-n32-1.d: New test.
	* testsuite/ld-mips-elf/mips16-pcrel-n64-sym32-0.d: New test.
	* testsuite/ld-mips-elf/mips16-pcrel-n64-sym32-1.d: New test.
	* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
 2017-05-03 20:47:40 +01:00
Maciej W. Rozycki
82d808edbc MIPS16/GAS: Fix absolute references with PC-relative synthetic instructions 
Complement commit 88a7ef1689 ("MIPS16/GAS: Restore unsupported
relocation diagnostics") and also propagate constant expressions, either
already reduced from absolute symbol references or created from literals
in the first place, used as a PC-relative operand with the MIPS16 LA,
LW, DLA and LD synthetic instructions to relaxation, matching the way
forward absolute symbol references have been handled as from the commit
referred and letting relaxation produce any necessary relocations, if
possible, for the absolute value requested to be reproduced at the run
time.

Call `symbol_append' for any expression symbol created for the purpose
of MIPS16 relaxation as with constant expressions now propagated from
earlier on such symbols may make it through and have R_MIPS16_PC16_S1
relocations emitted against, and therefore need to appear in the symbol
table produced.

	gas/
	* config/tc-mips.c (append_insn): Call `symbol_append' for any
	expression symbol created for MIPS16 relaxation.
	(match_mips16_insn): Don't encode a constant value as an
	immediate with a PC-relative operand.

	* testsuite/gas/mips/mips16-pcrel-absolute-1.d: New test.
	* testsuite/gas/mips/mips16-branch-absolute-1.d: New test.
	* testsuite/gas/mips/mips16-branch-absolute-2.d: New test.
	* testsuite/gas/mips/mips16-branch-absolute-addend-1.d: New
	test.
	* testsuite/gas/mips/mips16-branch-absolute-n32-1.d: New test.
	* testsuite/gas/mips/mips16-branch-absolute-n32-2.d: New test.
	* testsuite/gas/mips/mips16-branch-absolute-addend-n32-1.d: New
	test.
	* testsuite/gas/mips/mips16-branch-absolute-n64-1.d: New test.
	* testsuite/gas/mips/mips16-branch-absolute-n64-2.d: New test.
	* testsuite/gas/mips/mips16-branch-absolute-addend-n64-1.d: New
	test.
	* testsuite/gas/mips/mips16-pcrel-absolute-1.l: New stderr
	output.
	* testsuite/gas/mips/mips16-pcrel-absolute-1.s: New test source.
	* testsuite/gas/mips/mips16-branch-absolute-1.s: New test
	source.
	* testsuite/gas/mips/mips16-branch-absolute-2.s: New test
	source.
	* testsuite/gas/mips/mips16-branch-absolute-addend-1.s: New test
	source.
	* testsuite/gas/mips/mips.exp: Run the new tests.

	ld/
	* testsuite/ld-mips-elf/mips16-branch-absolute-1.d: New test.
	* testsuite/ld-mips-elf/mips16-branch-absolute-2.d: New test.
	* testsuite/ld-mips-elf/mips16-branch-absolute-addend-1.d: New
	test.
	* testsuite/ld-mips-elf/mips16-branch-absolute-n32-1.d: New
	test.
	* testsuite/ld-mips-elf/mips16-branch-absolute-n32-2.d: New
	test.
	* testsuite/ld-mips-elf/mips16-branch-absolute-addend-n32-1.d:
	New test.
	* testsuite/ld-mips-elf/mips16-branch-absolute-n64-1.d: New
	test.
	* testsuite/ld-mips-elf/mips16-branch-absolute-n64-2.d: New
	test.
	* testsuite/ld-mips-elf/mips16-branch-absolute-addend-n64-1.d:
	New test.
	* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
 2017-05-03 00:15:56 +01:00
Maciej W. Rozycki
14f72d45a2 MIPS16/GAS: Factor out duplicate symbol value conversion code 
Factor out and consolidate duplicate section-relative to PC-relative
symbol value conversion in `mips16_extended_frag' and `md_convert_frag'
used for MIPS16 relaxation, observing that the final calculation in the
latter function implies `stretch == 0'.  Sanitize the formatting of code
moved.

	gas/
	* config/tc-mips.c (mips16_pcrel_val): New function, factored
	out from...
	(mips16_extended_frag): ... here.
	(md_convert_frag): Use `mips16_pcrel_val' rather than repeated
	code in MIPS16 relaxation, with `stretch' hardcoded to 0.
 2017-04-27 12:21:58 +01:00
Maciej W. Rozycki
1425c41dcd MIPS16/GAS: Rename the LONG_BRANCH relaxation flag 
Following commit 177b4a6ad0 ("infinite loop in mips16 assembler
relaxation"), <https://sourceware.org/ml/binutils/2002-03/msg00345.html>
the LONG_BRANCH flag used in MIPS16 relaxation has lost its use for
branches.  Complement commit 88a7ef1689 ("MIPS16/GAS: Restore
unsupported relocation diagnostics") then, which has removed the remains
of code deactivated by the former commit, and rename the flag to
ALWAYS_EXTENDED, more accurately reflecting its current use to select
the extended form of PC-relative ADDIU, DADDIU, LD and LW instructions.

	gas/
	* config/tc-mips.c (RELAX_MIPS16_LONG_BRANCH): Rename to...
	(RELAX_MIPS16_ALWAYS_EXTENDED): ... this.
	(RELAX_MIPS16_MARK_LONG_BRANCH): Rename to...
	(RELAX_MIPS16_MARK_ALWAYS_EXTENDED): ... this.
	(RELAX_MIPS16_CLEAR_LONG_BRANCH): Rename to...
	(RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED): ... this.
	(mips16_extended_frag): Adjust accordingly.
 2017-04-27 12:19:39 +01:00
Maciej W. Rozycki
ce8ad87213 MIPS/GAS: Fix `.option picX' handling with relaxation 
Correct the handling of `.option pic0' and `.option pic2' GAS pseudo-ops
in relaxation and use the setting of `mips_pic' (which these directives
control) as at the time a relaxed frag has been created rather than the
final `mips_pic' setting at the end of the source file processed.

To do so record whether `mips_pic' is NO_PIC or not in the frag itself
and use this information throughout relaxation instead of `mips_pic' to
decide which of NO_PIC or SVR4_PIC to produce machine code for, fixing
code generation and removing a possible fatal failure reproducible with:

$ as -32 --relax-branch -o option-pic-relax-3.o option-pic-relax-3.s
option-pic-relax-3.s: Assembler messages:
option-pic-relax-3.s:7: Warning: relaxed out-of-range branch into a jump
option-pic-relax-3.s: Internal error in cvt_frag_to_fill at .../gas/write.c:490.
Please report this bug.
$

using the test source included, due to a buffer overrun in filling the
variable part of a frag.

Likewise use the `fx_tcbit2' flag of a BFD_RELOC_16_PCREL_S2 fixup to
handle the simple case of substituting an out of range unconditional
branch with an equivalent absolute jump in NO_PIC code.

Retain the current way of VXWORKS_PIC use, which commit 41a1578ed1
("MIPS/GAS: Sanitize `.option picX' pseudo-op") has forbidden the use of
`.option picX' with.

	gas/
	* config/tc-mips.c (RELAX_ENCODE): Add `PIC' flag.
	(RELAX_PIC): New macro.
	(RELAX_USE_SECOND, RELAX_SECOND_LONGER, RELAX_NOMACRO)
	(RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT)
	(RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND):
	Shift bits.
	(RELAX_BRANCH_ENCODE): Add `pic' flag.
	(RELAX_BRANCH_UNCOND, RELAX_BRANCH_LIKELY, RELAX_BRANCH_LINK)
	(RELAX_BRANCH_TOOFAR): Shift bits.
	(RELAX_BRANCH_PIC): New macro.
	(RELAX_MICROMIPS_ENCODE): Add `pic' flag.
	(RELAX_MICROMIPS_PIC): New macro.
	(RELAX_MICROMIPS_UNCOND, RELAX_MICROMIPS_COMPACT)
	(RELAX_MICROMIPS_LINK, RELAX_MICROMIPS_NODS)
	(RELAX_MICROMIPS_RELAX32): Shift bits.
	(relax_close_frag): Pass `mips_pic' setting to RELAX_ENCODE.
	(append_insn): Pass `mips_pic' setting to RELAX_BRANCH_ENCODE
	and RELAX_MICROMIPS_ENCODE, and record it in `fx_tcbit2' of the
	first fixup created.
	(md_apply_fix) <BFD_RELOC_16_PCREL_S2>: Use `fx_tcbit2' of the
	fixup processed rather than `mips_pic' in choosing to relax an
	out of range branch to a jump.
	(relaxed_branch_length): Use the `pic' flag of the relaxed frag
	rather than `mips_pic'.
	(relaxed_micromips_32bit_branch_length): Likewise.
	(md_estimate_size_before_relax): Likewise.
	(md_convert_frag): Likewise.

	* testsuite/gas/mips/option-pic-relax-0.d: New test.
	* testsuite/gas/mips/option-pic-relax-1.d: New test.
	* testsuite/gas/mips/option-pic-relax-2.d: New test.
	* testsuite/gas/mips/option-pic-relax-3.d: New test.
	* testsuite/gas/mips/option-pic-relax-3a.d: New test.
	* testsuite/gas/mips/option-pic-relax-4.d: New test.
	* testsuite/gas/mips/option-pic-relax-5.d: New test.
	* testsuite/gas/mips/option-pic-relax-2.l: New stderr output.
	* testsuite/gas/mips/option-pic-relax-3.l: New stderr output.
	* testsuite/gas/mips/option-pic-relax-4.l: New stderr output.
	* testsuite/gas/mips/option-pic-relax-5.l: New stderr output.
	* testsuite/gas/mips/option-pic-relax-0.s: New test source.
	* testsuite/gas/mips/option-pic-relax-1.s: New test source.
	* testsuite/gas/mips/option-pic-relax-2.s: New test source.
	* testsuite/gas/mips/option-pic-relax-3.s: New test source.
	* testsuite/gas/mips/option-pic-relax-4.s: New test source.
	* testsuite/gas/mips/option-pic-relax-5.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.
 2017-04-27 00:50:57 +01:00
Maciej W. Rozycki
adc1273cb2 MIPS/GAS: Correct BFD_RELOC_MIPS16_16_PCREL_S1 fixup size 
Correct the size of a BFD_RELOC_MIPS16_16_PCREL_S1 fixup made in
`md_convert_frag', fixing a bug introduced with commit c9775dde32
("MIPS16: Add R_MIPS16_PC16_S1 branch relocation support)".  Add test
cases to verify that the overflow of this fixup's in-place addend is
still correctly detected.

	gas/
	* config/tc-mips.c (md_convert_frag): Correct
	BFD_RELOC_MIPS16_16_PCREL_S1 fixup size.
	* testsuite/gas/mips/mips16-branch-addend-4.d: New test.
	* testsuite/gas/mips/mips16-branch-addend-5.d: New test.
	* testsuite/gas/mips/mips16-branch-addend-5.l: New stderr
	output.
	* testsuite/gas/mips/mips16-branch-addend-4.s: New test source.
	* testsuite/gas/mips/mips16-branch-addend-5.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.
 2017-04-25 11:53:45 +01:00
H.J. Lu
a91e1603af Support ELF SHF_GNU_MBIND and PT_GNU_MBIND_XXX 
Mark an ALLOC section, which should be placed in special memory area,
with SHF_GNU_MBIND.  Its sh_info field indicates the special memory
type.  GNU_MBIND section names start with ".mbind" so that they are
placed as orphan sections by linker.  All input GNU_MBIND sections
with the same sh_type, sh_flags and sh_info are placed in one output
GNU_MBIND section.  In executable and shared object, create a
GNU_MBIND segment for each GNU_MBIND section and its segment type is
PT_GNU_MBIND_LO plus the sh_info value.  Each GNU_MBIND segment is
aligned at page boundary.

The assembler syntax:

    .section .mbind.foo,"adx",%progbits
                          ^             0: Special memory type.
                          |
                         'd' for SHF_GNU_MBIND.

    .section .mbind.foo,"adx",%progbits,0x1
                          ^             1: Special memory type.
                          |
                         'd' for SHF_GNU_MBIND.

    .section .mbind.bar,"adG",%progbits,.foo_group,comdat,0x2
                          ^                               2: Special memory type.
                          |
                         'd' for SHF_GNU_MBIND.

bfd/

	* elf.c (get_program_header_size): Add a GNU_MBIND segment for
	each GNU_MBIND section and align GNU_MBIND section to page size.
	(_bfd_elf_map_sections_to_segments): Create a GNU_MBIND
	segment for each GNU_MBIND section.
	(_bfd_elf_init_private_section_data): Copy sh_info from input
	for GNU_MBIND section.

binutils/

	* NEWS: Mention support for ELF SHF_GNU_MBIND and
	PT_GNU_MBIND_XXX.
	* readelf.c (get_segment_type): Handle PT_GNU_MBIND_XXX.
	(get_elf_section_flags): Handle SHF_GNU_MBIND.
	(process_section_headers): Likewise.
	* testsuite/binutils-all/mbind1.s: New file.
	* testsuite/binutils-all/objcopy.exp: Run readelf test on
	mbind1.s.

gas/

	* NEWS: Mention support for ELF SHF_GNU_MBIND.
	* config/obj-elf.c (section_match): New.
	(get_section): Match both sh_info and group name.
	(obj_elf_change_section): Add argument for sh_info.  Pass both
	sh_info and group name to get_section. Issue an error for
	SHF_GNU_MBIND section without SHF_ALLOC.  Set sh_info.
	(obj_elf_parse_section_letters): Set SHF_GNU_MBIND for 'd'.
	(obj_elf_section): Support SHF_GNU_MBIND section info.
	* config/obj-elf.h (obj_elf_change_section): Add argument for
	sh_info.
	* config/tc-arm.c (start_unwind_section): Pass 0 as sh_info to
	obj_elf_change_section.
	* config/tc-ia64.c (obj_elf_vms_common): Likewise.
	* config/tc-microblaze.c (microblaze_s_data): Likewise.
	(microblaze_s_sdata): Likewise.
	(microblaze_s_rdata): Likewise.
	(microblaze_s_bss): Likewise.
	* config/tc-mips.c (s_change_section): Likewise.
	* config/tc-msp430.c (msp430_profiler): Likewise.
	* config/tc-rx.c (parse_rx_section): Likewise.
	* config/tc-tic6x.c (tic6x_start_unwind_section): Likewise.
	* doc/as.texinfo: Document 'd' for SHF_GNU_MBIND.
	* testsuite/gas/elf/elf.exp: Run section12a, section12b and
	section13.
	* testsuite/gas/elf/section10.d: Updated.
	* testsuite/gas/elf/section10.s: Likewise.
	* testsuite/gas/elf/section12.s: New file.
	* testsuite/gas/elf/section12a.d: Likewise.
	* testsuite/gas/elf/section12b.d: Likewise.
	* testsuite/gas/elf/section13.l: Likewise.
	* testsuite/gas/elf/section13.d: Likewise.
	* testsuite/gas/elf/section13.s: Likewise.

include/

	* elf/common.h (PT_GNU_MBIND_NUM): New.
	(PT_GNU_MBIND_LO): Likewise.
	(PT_GNU_MBIND_HI): Likewise.
	(SHF_GNU_MBIND): Likewise.

ld/

	* NEWS: Mention support for ELF SHF_GNU_MBIND and
	PT_GNU_MBIND_XXX.
	* emultempl/elf32.em (gld${EMULATION_NAME}_place_orphan): Place
	input GNU_MBIND sections with the same type, attributes and
	sh_info field into a single output GNU_MBIND section.
	* testsuite/ld-elf/elf.exp: Run mbind2a and mbind2b.
	* testsuite/ld-elf/mbind1.s: New file.
	* testsuite/ld-elf/mbind1a.d: Likewise.
	* testsuite/ld-elf/mbind1b.d: Likewise.
	* testsuite/ld-elf/mbind1c.d: Likewise.
	* testsuite/ld-elf/mbind2a.s: Likewise.
	* testsuite/ld-elf/mbind2b.c: Likewise.
 2017-04-04 09:06:04 -07:00
Maciej W. Rozycki
5ff6a06c21 GAS: Consistently fix labels at the `.end' pseudo-op 
Fix a functional regression with the `.end' pseudo-op, introduced with
commit ecb4347ade ("Last take: approval for MIPS_STABS_ELF killing"),
<https://sourceware.org/ml/binutils/2002-06/msg00443.html>, and commit
dcd410fe15 ("GNU as 2.14 on IRIX 6: crashes with shared libs"),
<https://sourceware.org/ml/binutils/2003-07/msg00415.html>, which caused
symbol values for labels placed between the end of a function's contents
and its terminating `.end' followed by one of the alignment pseudo-ops
to be different depending on whether either `-mdebug', or `-mno-pdr', or
neither of the command-line options is in effect, be it implied or
specified.

Given debug-label-end.s as follows and the `mips-linux' target we have:

$ cat debug-label-end.s
	.text

	.globl	foo
	.globl	bar
	.align	4, 0
	.ent	foo
foo:
	nop
	.aent	bar
bar:
	.insn
	.end	foo
	.align	4, 0
	.space	16

	.globl	baz
	.ent	baz
baz:
	nop
	.end	baz
	.align	4, 0
	.space	16
$ as -o debug-label-end.o debug-label-end.s
$ readelf -s debug-label-end.o | grep bar
     9: 00000004     0 FUNC    GLOBAL DEFAULT    1 bar
$ as -mdebug -o debug-label-end.o debug-label-end.s
$ readelf -s debug-label-end.o | grep bar
     9: 00000010     0 FUNC    GLOBAL DEFAULT    1 bar
$ as -mno-pdr -o debug-label-end.o debug-label-end.s
$ readelf -s debug-label-end.o | grep bar
     8: 00000010     0 FUNC    GLOBAL DEFAULT    1 bar
$

The reason is the call to `md_flush_pending_output', which in the case
of `mips*-*-*' targets expands to `mips_emit_delays', which in turn
calls `mips_no_prev_insn', which calls `mips_clear_insn_labels', which
clears the list of outstanding labels.  That list is in turn consulted
in `mips_align', called in the interpretation of alignment directives,
and the labels adjusted to the current location.

A call to `md_flush_pending_output' is only made from `s_mips_end' and
then only if `-mpdr' is in effect, which is the default for `*-*-linux*'
and some other `mips*-*-*' targets.  A call to `md_flush_pending_output'
is never made from `ecoff_directive_end', which is used in place of
`s_mips_end' when `-mdebug' is in effect.  Consequently if `-mno-pdr' or
`-mdebug' is in effect the list of outstanding labels makes it through
to any alignment directive that follows and the labels are differently
interpreted depending on the command-lines options used.  And we want
code produced to be always the same.

Call `md_flush_pending_output' unconditionally then in `s_mips_end' and
add such a call from `ecoff_directive_end' as well, as long as the macro
is defined.  While `ecoff_directive_end' is shared among targets, the
only one other than `mips*-*-*' actually using it is `alpha*-*-*' and it
does not define `md_flush_pending_output'.  So the semantics isn't going
to change for it and neither it has to have its `s_alpha_end' updated
or have code in `ecoff_directive_end' conditionalized.

	gas/
	* ecoff.c (ecoff_directive_end) [md_flush_pending_output]: Call
	`md_flush_pending_output'.
	* config/tc-mips.c (s_mips_end) [md_flush_pending_output]: Call
	`md_flush_pending_output' unconditionally.
	* testsuite/gas/mips/debug-label-end-1.d: New test.
	* testsuite/gas/mips/debug-label-end-2.d: New test.
	* testsuite/gas/mips/debug-label-end-3.d: New test.
	* testsuite/gas/mips/debug-label-end.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.
 2017-02-22 18:15:33 +00:00
Maciej W. Rozycki
8b10b0b3e1 MIPS: Add options to control branch ISA checks 
Complement commit 9d862524f6 ("MIPS: Verify the ISA mode and alignment
of branch and jump targets") and add GAS and LD options to control the
checks for invalid branches between ISA modes introduced there, to help
with some handwritten code lacking `.insn' annotation for labels used as
branch targets and code produced by older versions of GCC which suffers
from the issue with branches to code that has been optimized away,
addressed with GCC commit 242424 ("MIPS/GCC: Mark trailing labels with
`.insn'"), <https://gcc.gnu.org/ml/gcc-patches/2016-11/msg01061.html>.

	bfd/
	* elfxx-mips.h (_bfd_mips_elf_insn32): Rename prototype to...
	(_bfd_mips_elf_linker_flags): ... this.  Add another parameter.
	* elfxx-mips.c (mips_elf_link_hash_table): Add
	`ignore_branch_isa' member.
	(mips_elf_perform_relocation): Do not treat an ISA mode mismatch
	in branch relocation calculation as an error if
	`ignore_branch_isa' has been set.
	(_bfd_mips_elf_insn32): Rename to...
	(_bfd_mips_elf_linker_flags): ... this.  Rename the `on'
	parameter to `insn32' and add an `ignore_branch_isa' parameter.
	Handle the new parameter.

	gas/
	* config/tc-mips.c (mips_ignore_branch_isa): New variable.
	(options): Add OPTION_IGNORE_BRANCH_ISA and
	OPTION_NO_IGNORE_BRANCH_ISA enum values.
	(md_longopts): Add "mignore-branch-isa" and
	"mno-ignore-branch-isa" options.
	(md_parse_option): Handle OPTION_IGNORE_BRANCH_ISA and
	OPTION_NO_IGNORE_BRANCH_ISA.
	(fix_bad_cross_mode_branch_p): Return FALSE if
	`mips_ignore_branch_isa' has been set.
	(md_show_usage): Add `-mignore-branch-isa' and
	`-mno-ignore-branch-isa'.

	* doc/as.texinfo (Target MIPS options): Add
	`-mignore-branch-isa' and `-mno-ignore-branch-isa' options.
	(-mignore-branch-isa, -mno-ignore-branch-isa): New options.
	* doc/c-mips.texi (MIPS Options): Add `-mignore-branch-isa' and
	`-mno-ignore-branch-isa' options.

	* testsuite/gas/mips/branch-local-ignore-2.d: New test.
	* testsuite/gas/mips/branch-local-ignore-3.d: New test.
	* testsuite/gas/mips/branch-local-ignore-n32-2.d: New test.
	* testsuite/gas/mips/branch-local-ignore-n32-3.d: New test.
	* testsuite/gas/mips/branch-local-ignore-n64-2.d: New test.
	* testsuite/gas/mips/branch-local-ignore-n64-3.d: New test.
	* testsuite/gas/mips/mips.exp: Run the new tests.

	ld/
	* emultempl/mipself.em (ignore_branch_isa): New variable.
	(mips_create_output_section_statements): Rename
	`_bfd_mips_elf_insn32' called to `_bfd_mips_elf_linker_flags',
	add `ignore_branch_isa' argument.
	(PARSE_AND_LIST_PROLOGUE): Add OPTION_IGNORE_BRANCH_ISA and
	OPTION_NO_IGNORE_BRANCH_ISA enum values.
	(PARSE_AND_LIST_LONGOPTS): Add "ignore-branch-isa" and
	"no-ignore-branch-isa" options.
	(PARSE_AND_LIST_OPTIONS): Add `--ignore-branch-isa' and
	`--no-ignore-branch-isa'.
	(PARSE_AND_LIST_ARGS_CASES): Handle OPTION_IGNORE_BRANCH_ISA and
	OPTION_NO_IGNORE_BRANCH_ISA.

	* ld.texinfo (Options specific to MIPS targets): Add
	`--ignore-branch-isa' and `--no-ignore-branch-isa' options.
	(ld and the MIPS family): Likewise.

	* testsuite/ld-mips-elf/bal-jalx-pic-ignore.d: New test.
	* testsuite/ld-mips-elf/bal-jalx-pic-ignore-n32.d: New test.
	* testsuite/ld-mips-elf/bal-jalx-pic-ignore-n64.d: New test.
	* testsuite/ld-mips-elf/unaligned-branch-ignore-2.d: New test.
	* testsuite/ld-mips-elf/unaligned-branch-ignore-r6-1: New test.
	* testsuite/ld-mips-elf/unaligned-branch-ignore-mips16: New
	test.
	* testsuite/ld-mips-elf/unaligned-branch-ignore-micromips: New
	test.
	* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
 2017-01-30 17:16:01 +00:00
Nick Clifton
33eaf5de31 Fix spelling mistakes and typos in the GAS sources. 
PR gas/21072
	* asintl.h: Fix spelling mistakes and typos.
	* atof-generic.c: Likewise.
	* bit_fix.h: Likewise.
	* config/atof-ieee.c: Likewise.
	* config/bfin-defs.h: Likewise.
	* config/bfin-parse.y: Likewise.
	* config/obj-coff-seh.h: Likewise.
	* config/obj-coff.c: Likewise.
	* config/obj-evax.c: Likewise.
	* config/obj-macho.c: Likewise.
	* config/rx-parse.y: Likewise.
	* config/tc-aarch64.c: Likewise.
	* config/tc-alpha.c: Likewise.
	* config/tc-arc.c: Likewise.
	* config/tc-arm.c: Likewise.
	* config/tc-avr.c: Likewise.
	* config/tc-bfin.c: Likewise.
	* config/tc-cr16.c: Likewise.
	* config/tc-cris.c: Likewise.
	* config/tc-crx.c: Likewise.
	* config/tc-d10v.c: Likewise.
	* config/tc-d30v.c: Likewise.
	* config/tc-dlx.c: Likewise.
	* config/tc-epiphany.c: Likewise.
	* config/tc-frv.c: Likewise.
	* config/tc-hppa.c: Likewise.
	* config/tc-i370.c: Likewise.
	* config/tc-i386-intel.c: Likewise.
	* config/tc-i386.c: Likewise.
	* config/tc-i960.c: Likewise.
	* config/tc-ia64.c: Likewise.
	* config/tc-m32r.c: Likewise.
	* config/tc-m68hc11.c: Likewise.
	* config/tc-m68k.c: Likewise.
	* config/tc-mcore.c: Likewise.
	* config/tc-mep.c: Likewise.
	* config/tc-mep.h: Likewise.
	* config/tc-metag.c: Likewise.
	* config/tc-microblaze.c: Likewise.
	* config/tc-mips.c: Likewise.
	* config/tc-mmix.c: Likewise.
	* config/tc-mn10200.c: Likewise.
	* config/tc-mn10300.c: Likewise.
	* config/tc-msp430.c: Likewise.
	* config/tc-msp430.h: Likewise.
	* config/tc-nds32.c: Likewise.
	* config/tc-nds32.h: Likewise.
	* config/tc-nios2.c: Likewise.
	* config/tc-nios2.h: Likewise.
	* config/tc-ns32k.c: Likewise.
	* config/tc-pdp11.c: Likewise.
	* config/tc-ppc.c: Likewise.
	* config/tc-pru.c: Likewise.
	* config/tc-rx.c: Likewise.
	* config/tc-s390.c: Likewise.
	* config/tc-score.c: Likewise.
	* config/tc-score7.c: Likewise.
	* config/tc-sh.c: Likewise.
	* config/tc-sh64.c: Likewise.
	* config/tc-sparc.c: Likewise.
	* config/tc-tic4x.c: Likewise.
	* config/tc-tic54x.c: Likewise.
	* config/tc-v850.c: Likewise.
	* config/tc-vax.c: Likewise.
	* config/tc-visium.c: Likewise.
	* config/tc-xgate.c: Likewise.
	* config/tc-xtensa.c: Likewise.
	* config/tc-z80.c: Likewise.
	* config/tc-z8k.c: Likewise.
	* config/te-vms.c: Likewise.
	* config/xtensa-relax.c: Likewise.
	* doc/as.texinfo: Likewise.
	* doc/c-arm.texi: Likewise.
	* doc/c-hppa.texi: Likewise.
	* doc/c-i370.texi: Likewise.
	* doc/c-i386.texi: Likewise.
	* doc/c-m32r.texi: Likewise.
	* doc/c-m68k.texi: Likewise.
	* doc/c-mmix.texi: Likewise.
	* doc/c-msp430.texi: Likewise.
	* doc/c-nds32.texi: Likewise.
	* doc/c-ns32k.texi: Likewise.
	* doc/c-riscv.texi: Likewise.
	* doc/c-rx.texi: Likewise.
	* doc/c-s390.texi: Likewise.
	* doc/c-tic6x.texi: Likewise.
	* doc/c-tilegx.texi: Likewise.
	* doc/c-tilepro.texi: Likewise.
	* doc/c-v850.texi: Likewise.
	* doc/c-xgate.texi: Likewise.
	* doc/c-xtensa.texi: Likewise.
	* dwarf2dbg.c: Likewise.
	* ecoff.c: Likewise.
	* itbl-ops.c: Likewise.
	* listing.c: Likewise.
	* macro.c: Likewise.
	* po/gas.pot: Likewise.
	* read.c: Likewise.
	* struc-symbol.h: Likewise.
	* symbols.h: Likewise.
	* testsuite/gas/arc/relocs-errors.err: Likewise.
	* write.c: Likewise.
 2017-01-23 15:23:07 +00:00
Maciej W. Rozycki
9e009953a5 PR gas/20649: MIPS: Fix GOT16/LO16 reloc pairing with comdat sections 
Correct a regression from commit 8614eeee67 ("Traditional MIPS
patches"), <https://sourceware.org/ml/binutils/2000-07/msg00018.html>,
which caused symbols in linkonce or what is these days known as comdat
sections to be treated as external for the purpose of PIC relocation
generation even if their binding remains STB_LOCAL.  This in turn
disabled GOT16/LO16 relocation pairing with references to such symbols,
as no complementing LO16 relocation is expected for external GOT16
references in the o32 ABI, which ultimately leads to link errors, e.g.:

ld: comdat-reloc.o: Can't find matching LO16 reloc against `foo' for R_MIPS_GOT16 at 0x24 in section `.text.bar[bar]'

as with the LD test case included with this change.

Revert the special case for symbols in comdat sections then, making code
actually match `adjust_reloc_syms' as indicated in its explanatory
comment, and adjust calling code accordingly.  Also bring back the
corresponding description of what now is `s_is_linkonce', lost with
commit 5f0fe04bc5 ("Improved MIPS16/MIPS32 code intermixing for
gas."), <https://www.sourceware.org/ml/binutils/2006-07/msg00039.html>.

	gas/
	PR gas/20649
	* config/tc-mips.c (pic_need_relax): Don't check for linkonce
	symbols, remove the `segtype' parameter.
	(mips_frob_file, md_estimate_size_before_relax): Adjust
	accordingly.
	(s_is_linkonce): Add an explanatory comment.
	* testsuite/gas/mips/comdat-reloc.d: New test.
	* testsuite/gas/mips/comdat-reloc.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new test.

	ld/
	PR gas/20649
	* testsuite/ld-mips-elf/mips-elf.exp: Add PIC comdat GOT16/LO16
	relocation pairing link test.
 2017-01-18 18:24:08 +00:00
Alan Modra
2571583aed Update year range in copyright notice of all files. 2017-01-02 14:08:56 +10:30
Maciej W. Rozycki
bdd152861c MIPS16: Simplify extended operand handling 
Simplify extended operand handling and only specially process immediates
which require bit shuffling, using the generic operand insertion and
extraction handlers for the '<' (5-bit shift amount) operand code in
particular.  Require the least significant bit of all extended operand
forms to be (artificially) set to 0 for their special processing to
trigger.

	gas/
	* config/tc-mips.c (mips16_immed): Limit `mips16_immed_extend'
	use to operands whose LSB position is zero.

	opcodes/
	* mips-dis.c (print_mips16_insn_arg): Simplify processing of
	extended operands.
	* mips16-opc.c (decode_mips16_operand): Switch the extended
	form of the `<' operand type to LSB position 22.
 2016-12-23 19:42:28 +00:00
Maciej W. Rozycki
1da43accb4 MIPS16/GAS: Clean up invalid unextended operand handling 
Bail out right away when an unextended instruction encoding is required
either with the use of a `.t' suffix or by means of `.set noautoextend',
however an operand supplied requires the extended instruction form to be
used.

This is to avoid messing up with the internal state of the assembler,
even though no actual failures are known to happen as a result.  Add
test cases for the situation concerned.

	gas/
	* config/tc-mips.c (match_mips16_insn): Don't update
	`forced_insn_length' or the instruction opcode if an operand
	requires an extended instruction form, but an unextended one
	has been requested.
	* testsuite/gas/mips/mips16-relax-unextended-1.d: New test.
	* testsuite/gas/mips/mips16-relax-unextended-2.d: New test.
	* testsuite/gas/mips/mips16-relax-unextended-1.l: New stderr
	output.
	* testsuite/gas/mips/mips16-relax-unextended-2.l: New stderr
	output.
	* testsuite/gas/mips/mips16-relax-unextended-1.s: New test
	source.
	* testsuite/gas/mips/mips16-relax-unextended-2.s: New test
	source.
	* testsuite/gas/mips/mips.exp: Run the new tests.
 2016-12-23 19:38:41 +00:00
Maciej W. Rozycki
d8722d7641 MIPS16: Reassign 0' and 4' operand codes 
Replace `0' and `4' operand codes with `.' and `F' respectively to free
up the `0'-`4' consecutive range.  No functional change.

	gas/
	* config/tc-mips.c (mips16_macro_build): Replace `0' and `4'
	operand codes with `.' and `F' respectively.
	(mips16_macro): Likewise.

	include/
	* opcode/mips.h: Replace `0' and `4' operand codes with `.' and
	`F' respectively.

	opcodes/
	* mips16-opc.c (decode_mips16_operand): Replace `0' and `4'
	operand codes with `.' and `F' respectively.
	(mips16_opcodes): Likewise.
 2016-12-23 19:37:13 +00:00
Maciej W. Rozycki
0674ee5dad MIPS16: Handle non-extensible instructions correctly 
Identify non-extensible instructions in the MIPS16 opcode table and
disallow their use with the `.e' instruction size suffix in assembly and
do not interpret any EXTEND prefix present as a part of the instruction
in disassembly.

According to all versions of the MIPS16 ASE specifications the following
instructions encodings are not extensible [1][2][3][4][5][6]: I8/MOV32R,
I8/MOVR32, all RRR minor opcodes, all RR minor opcodes except from DSRA
and DSRL, and EXTEND itself, and as from revision 2.50 of the MIPS16e
ASE specifications it has been further clarified what was previously
implied, that non-extesiable instructions when preceded with an EXTEND
prefix must cause a Reserved Instruction exception [3][5].

Therefore in the presence of an EXTEND prefix none of these instructions
are supposed to be handled as extended instructions and supporting these
forms in disassembly causes confusion, and in the case of the RRR major
opcode it also clashes with the ASMACRO encoding.

References:

[1] "Product Description, MIPS16 Application-Specific Extension",
    Version 1.3, MIPS Technologies, Inc., 970130, Table 3. "MIPS16
    Instruction Set Summary", p. 5

[2] same, Table 5 "RR Minor Opcodes (RR-type instructions)", p.10

[3] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e
    Application-Specific Extension to the MIPS32 Architecture", MIPS
    Technologies, Inc., Document Number: MD00076, Revision 2.63, July
    16, 2013, Section 3.9 "MIPS16e Instruction Summaries", pp. 37-39

[4] same, Section 3.15 "Instruction Bit Encoding", pp. 46-49

[5] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e
    Application-Specific Extension to the MIPS64 Architecture", MIPS
    Technologies, Inc., Document Number: MD00077, Revision 2.60, June
    25, 2008, Section 1.9 "MIPS16e Instruction Summaries", pp. 38-41

[6] same, Section 1.15 "Instruction Bit Encoding", pp. 48-51

	include/
	* opcode/mips.h (INSN2_SHORT_ONLY): New macro.

	gas/
	* config/tc-mips.c (is_size_valid_16): Disallow a `.e' suffix
	instruction size override for INSN2_SHORT_ONLY opcode table
	entries.
	* testsuite/gas/mips/mips16-extend-swap.d: Adjust output.
	* testsuite/gas/mips/mips16-macro-e.l: Adjust error messages.
	* testsuite/gas/mips/mips16-32@mips16-macro-e.l: Adjust error
	messages.
	* testsuite/gas/mips/mips16e-32@mips16-macro-e.l: Adjust error
	messages.
	* testsuite/gas/mips/mips16-insn-e.d: New test.
	* testsuite/gas/mips/mips16-insn-t.d: New test.
	* testsuite/gas/mips/mips16-32@mips16-insn-e.d: New test.
	* testsuite/gas/mips/mips16-64@mips16-insn-e.d: New test.
	* testsuite/gas/mips/mips16e-32@mips16-insn-e.d: New test.
	* testsuite/gas/mips/mips16-32@mips16-insn-t.d: New test.
	* testsuite/gas/mips/mips16-64@mips16-insn-t.d: New test.
	* testsuite/gas/mips/mips16e-32@mips16-insn-t.d: New test.
	* testsuite/gas/mips/mips16-insn-e.l: New stderr output.
	* testsuite/gas/mips/mips16-insn-t.l: New stderr output.
	* testsuite/gas/mips/mips16-32@mips16-insn-e.l: New stderr
	output.
	* testsuite/gas/mips/mips16-64@mips16-insn-e.l: New stderr
	output.
	* testsuite/gas/mips/mips16e-32@mips16-insn-e.l: New stderr
	output.
	* testsuite/gas/mips/mips16-32@mips16-insn-t.l: New stderr
	output.
	* testsuite/gas/mips/mips16-64@mips16-insn-t.l: New stderr
	output.
	* testsuite/gas/mips/mips16e-32@mips16-insn-t.l: New stderr
	output.
	* testsuite/gas/mips/mips16-insn-e.s: New test source.
	* testsuite/gas/mips/mips16-insn-t.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.

	opcodes/
	* mips-dis.c (print_insn_mips16): Disallow EXTEND prefix
	matching for INSN2_SHORT_ONLY opcode table entries.
	* mips16-opc.c (SH): New macro.
	(mips16_opcodes): Set SH in `pinfo2' for non-extensible
	instruction entries: "nop", "addu", "and", "break", "cmp",
	"daddu", "ddiv", "ddivu", "div", "divu", "dmult", "dmultu",
	"drem", "dremu", "dsllv", "dsll", "dsrav", "dsra", "dsrlv",
	"dsrl", "dsubu", "exit", "entry", "jalr", "jal", "jr", "j",
	"jalrc", "jrc", "mfhi", "mflo", "move", "mult", "multu", "neg",
	"not", "or", "rem", "remu", "sllv", "sll", "slt", "sltu",
	"srav", "sra", "srlv", "srl", "subu", "xor", "sdbbp", "seb",
	"seh", "sew", "zeb", "zeh", "zew" and "extend".

	binutils/
	* testsuite/binutils-all/mips/mips16-extend-insn.d: New test.
	* testsuite/binutils-all/mips/mips16-extend-insn.s: New test
	source.
	* testsuite/binutils-all/mips/mips.exp: Run the new tests.
 2016-12-23 19:33:45 +00:00
Maciej W. Rozycki
b2805ed554 MIPS16: Remove "extended" BREAK/SDBBP handling 
Remove special casing for the `6' operand code used for the embedded
trap code of the BREAK and the SDBBP instructions to support supposedly
extended forms of these instructions.

According to all versions of the MIPS16 ASE specifications these
instructions are not extensible [1][2][3][4][5][7][8][10][11], and as
from revision 2.50 of the MIPS16e ASE specifications it has been further
clarified what was previously implied, that non-extesiable instructions
when preceded with an EXTEND prefix must cause a Reserved Instruction
exception [5][6][9][10].

Therefore supposedly extended BREAK and SDBBP instructions do not serve
their purpose anymore as they do not cause a Bp and a Debug exception
respectively and supporting these forms in disassembly only causes
confusion.

References:

[1] "Product Description, MIPS16 Application-Specific Extension",
    Version 1.3, MIPS Technologies, Inc., 970130, Table 3. "MIPS16
    Instruction Set Summary", p. 5

[2] same, Table 5 "RR Minor Opcodes (RR-type instructions)", p.10

[3] same, Table 18. "Extendable MIPS16 Instructions", p. 24

[4] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e
    Application-Specific Extension to the MIPS32 Architecture", MIPS
    Technologies, Inc., Document Number: MD00076, Revision 2.63, July
    16, 2013, Table 3.8 "MIPS16e Special Instructions", p. 38

[5] same, Section 3.11 "MIPS16e Extensible Instructions, p. 41

[6] same, Table 3.15 "MIPS16e Extensible Instructions", p. 41

[7] same, Table 3.24 "MIPS16e RR Encoding of the Funct Field", p. 49

[8] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e
    Application-Specific Extension to the MIPS64 Architecture", MIPS
    Technologies, Inc., Document Number: MD00077, Revision 2.60, June
    25, 2008, Table 1.8 "MIPS16e Special Instructions", p. 39

[9] same, Section 1.11 "MIPS16e Extensible Instructions", p. 42

[10] same, Table 1.15 "MIPS16e Extensible Instructions", pp. 42-43

[11] same, Table 1.24 "MIPS16e RR Encoding of the Funct Field", p. 50

	gas/
	* config/tc-mips.c (match_mips16_insn): Remove the `6' operand
	code special case and its associated comment.

	opcodes/
	* mips16-opc.c (decode_mips16_operand) <'6'>: Remove extended
	encoding support.
 2016-12-23 19:30:39 +00:00
Maciej W. Rozycki
3fb4970943 MIPS16/GAS: Fix forced size suffixes with argumentless instructions 
Correct the handling of `.e' and `.t' instruction size suffixes with
instruction mnemonics which are not followed by any text on the same
line, such as arguments or white space, e.g.:

$ cat test.s
	.set	mips16
foo:
	entry.t		# comment
	entry.t
	exit.t		# comment
	exit.t
	nop.t		# comment
	nop.t
$ as -32 -o test.o test.s
test.s: Assembler messages:
test.s:4: Error: unrecognized opcode `entry.t'
test.s:6: Error: unrecognized opcode `exit.t'
test.s:8: Error: unrecognized opcode `nop.t'
$

	gas/
	* config/tc-mips.c (mips16_ip): Handle `.e' and `.t' instruction
	suffixes followed by a null character rather than a space too.
	* testsuite/gas/mips/mips16-insn-length-noargs.d: New test.
	* testsuite/gas/mips/mips16-insn-length-noargs.s: New test
	source.
	* testsuite/gas/mips/mips.exp: Run the new test.
 2016-12-23 19:28:23 +00:00
Maciej W. Rozycki
7fd5392005 MIPS16: Switch to 32-bit opcode table interpretation 
Switch to 32-bit MIPS16 opcode table entry interpretation, similar to
how the microMIPS opcode table is handled, for both the `match' and
`mask' fields, removing special casing for JAL and JALX instructions and
their `a' and `i' operand codes throughout, while retaining automatic
processing of extendable opcodes in assembly and disassembly.

In assembly disallow size enforcement suffixes as appropriate: `.t' for
both 32-bit instructions and macros and `.e' for macros only, making
macro handling consistent with the microMIPS instruction set.

In disassembly fully decode EXTEND prefixes prepended to unsupported
instruction encodings (according to the ISA selection) rather than
dumping them as hexadecimal data along with the following instruction,
removing all special casing for the EXTEND prefix and making its
handling rely on its opcode table entry, except where it is considered a
part of an extendable instruction.

	include/
	* opcode/mips.h (mips_opcode_32bit_p): New inline function.

	gas/
	* config/tc-mips.c (micromips_insn_length): Use
	`mips_opcode_32bit_p'.
	(is_size_valid): Adjust description.
	(is_size_valid_16): New function.
	(validate_mips_insn): Use `mips_opcode_32bit_p' in MIPS16
	operand decoding.
	(validate_mips16_insn): Remove `a' and `i' operand code special
	casing, use `mips_opcode_32bit_p' to determine instruction
	width.
	(append_insn): Adjust forced MIPS16 instruction size
	determination.
	(match_mips16_insn): Likewise.  Don't shift the instruction's
	opcode with the `a' and `i' operand codes.  Use
	`mips_opcode_32bit_p' in operand decoding.
	(match_mips16_insns): Check for forced instruction size's
	validity.
	(mips16_ip): Don't force instruction size in the `noautoextend'
	mode.
	* testsuite/gas/mips/mips16-jal-e.d: New test.
	* testsuite/gas/mips/mips16-jal-t.d: New test.
	* testsuite/gas/mips/mips16-macro-e.d: New test.
	* testsuite/gas/mips/mips16-macro-t.d: New test.
	* testsuite/gas/mips/mips16-jal-t.l: New stderr output.
	* testsuite/gas/mips/mips16-macro-e.l: New stderr output.
	* testsuite/gas/mips/mips16-macro-t.l: New stderr output.
	* testsuite/gas/mips/mips16-jal-e.s: New test source.
	* testsuite/gas/mips/mips16-jal-t.s: New test source.
	* testsuite/gas/mips/mips16-macro-e.s: New test source.
	* testsuite/gas/mips/mips16-macro-t.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.

	opcodes/
	* mips-dis.c (print_mips16_insn_arg): Always handle `extend' and
	`insn' together, with `extend' as the high-order 16 bits.
	(match_kind): New enum.
	(print_insn_mips16): Rework for 32-bit instruction matching.
	Do not dump EXTEND prefixes here.
	* mips16-opc.c (mips16_opcodes): Move "extend" entry to the end.
	Recode `match' and `mask' fields as 32-bit in absolute "jal" and
	"jalx" entries.

	binutils/
	* testsuite/binutils-all/mips/mips16-extend-noinsn.d: Adjust
	test for separate EXTEND prefix disassembly.
 2016-12-20 11:56:32 +00:00
Maciej W. Rozycki
eefc336583 MIPS16/GAS: Fix assertion failures with relocations on 16-bit instructions 
Complement commit c9775dde32 ("MIPS16: Add R_MIPS16_PC16_S1 branch
relocation support)" and report an assembly error when a relocation is
required for an instruction, currently a branch only, that has been
forced to use its unextended encoding, either with the use of an
explicit `.t' mnemonic suffix, or by means of `.set noautoextend' being
active, fixing an assertion failure currently caused instead.

	gas/
	* config/tc-mips.c (md_convert_frag): Report an error instead of
	asserting on `ext'.
	* testsuite/gas/mips/mips16-branch-unextended-1.d: New test.
	* testsuite/gas/mips/mips16-branch-unextended-2.d: New test.
	* testsuite/gas/mips/mips16-branch-unextended-1.s: New test
	source.
	* testsuite/gas/mips/mips16-branch-unextended-2.s: New test.
	* testsuite/gas/mips/mips16-branch-unextended.l: New stderr
	output.
	* testsuite/gas/mips/mips.exp: Run the new tests.
 2016-12-14 22:05:38 +00:00
Maciej W. Rozycki
64c1118340 MIPS16: Remove unused `>' operand code 
This code has never been used throughout the repository history, and
likely not before either, as due to the assymetry of MIPS16 instruction
set encoding there are no 32-bit shift operations having their immediate
shift count placed in the position of the usual `rx' instruction field.

	gas/
	* config/tc-mips.c (mips16_macro_build) <'>'>: Remove case.

	include/
	* opcode/mips.h: Remove references to `>' operand code.

	opcodes/
	* mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
 2016-12-09 23:21:40 +00:00
Maciej W. Rozycki
be0fcbee1d MIPS/GAS: Use local isa' consistently in is_opcode_valid' 
Replace a global `mips_opts.isa' reference in `is_opcode_valid' and use
a local copy just made in `isa'.  No functional change.

	gas/
	* config/tc-mips.c (is_opcode_valid): Use local `isa'
	consistently.
 2016-12-07 12:24:39 +00:00
Ambrogino Modigliani
2b0f37619f Fix spelling in comments in C source files (gas) 
* as.h: Fix spelling in comments.
	* config/obj-ecoff.c: Fix spelling in comments.
	* config/obj-macho.c: Fix spelling in comments.
	* config/tc-aarch64.c: Fix spelling in comments.
	* config/tc-arc.c: Fix spelling in comments.
	* config/tc-arm.c: Fix spelling in comments.
	* config/tc-avr.c: Fix spelling in comments.
	* config/tc-cr16.c: Fix spelling in comments.
	* config/tc-epiphany.c: Fix spelling in comments.
	* config/tc-frv.c: Fix spelling in comments.
	* config/tc-hppa.c: Fix spelling in comments.
	* config/tc-hppa.h: Fix spelling in comments.
	* config/tc-i370.c: Fix spelling in comments.
	* config/tc-m68hc11.c: Fix spelling in comments.
	* config/tc-m68k.c: Fix spelling in comments.
	* config/tc-mcore.c: Fix spelling in comments.
	* config/tc-mep.c: Fix spelling in comments.
	* config/tc-metag.c: Fix spelling in comments.
	* config/tc-mips.c: Fix spelling in comments.
	* config/tc-mn10200.c: Fix spelling in comments.
	* config/tc-mn10300.c: Fix spelling in comments.
	* config/tc-nds32.c: Fix spelling in comments.
	* config/tc-nios2.c: Fix spelling in comments.
	* config/tc-ns32k.c: Fix spelling in comments.
	* config/tc-pdp11.c: Fix spelling in comments.
	* config/tc-ppc.c: Fix spelling in comments.
	* config/tc-riscv.c: Fix spelling in comments.
	* config/tc-rx.c: Fix spelling in comments.
	* config/tc-score.c: Fix spelling in comments.
	* config/tc-score7.c: Fix spelling in comments.
	* config/tc-sparc.c: Fix spelling in comments.
	* config/tc-tic54x.c: Fix spelling in comments.
	* config/tc-vax.c: Fix spelling in comments.
	* config/tc-xgate.h: Fix spelling in comments.
	* config/tc-xtensa.c: Fix spelling in comments.
	* config/tc-z80.c: Fix spelling in comments.
	* dwarf2dbg.c: Fix spelling in comments.
	* input-file.h: Fix spelling in comments.
	* itbl-ops.c: Fix spelling in comments.
	* read.c: Fix spelling in comments.
	* stabs.c: Fix spelling in comments.
	* symbols.c: Fix spelling in comments.
	* write.c: Fix spelling in comments.
	* testsuite/gas/all/itbl-test.c: Fix spelling in comments.
	* testsuite/gas/tic4x/opclasses.h: Fix spelling in comments.
 2016-11-27 15:02:09 +10:30
Alan Modra
1a0670f374 -Wimplicit-fallthrough warning fixes 
Comment changes.

bfd/
	* coff-h8300.c: Spell fall through comments consistently.
	* coffgen.c: Likewise.
	* elf32-hppa.c: Likewise.
	* elf32-ppc.c: Likewise.
	* elf32-score.c: Likewise.
	* elf32-score7.c: Likewise.
	* elf64-ppc.c: Likewise.
	* elfxx-aarch64.c: Likewise.
	* elfxx-mips.c: Likewise.
	* cpu-ns32k.c: Add missing fall through comments.
	* elf-m10300.c: Likewise.
	* elf32-arm.c: Likewise.
	* elf32-avr.c: Likewise.
	* elf32-bfin.c: Likewise.
	* elf32-frv.c: Likewise.
	* elf32-i386.c: Likewise.
	* elf32-microblaze.c: Likewise.
	* elf32-nds32.c: Likewise.
	* elf32-ppc.c: Likewise.
	* elf32-rl78.c: Likewise.
	* elf32-rx.c: Likewise.
	* elf32-s390.c: Likewise.
	* elf32-sh.c: Likewise.
	* elf32-tic6x.c: Likewise.
	* elf64-ia64-vms.c: Likewise.
	* elf64-ppc.c: Likewise.
	* elf64-s390.c: Likewise.
	* elf64-x86-64.c: Likewise.
	* elflink.c: Likewise.
	* elfnn-aarch64.c: Likewise.
	* elfnn-ia64.c: Likewise.
	* ieee.c: Likewise.
	* oasys.c: Likewise.
	* pdp11.c: Likewise.
	* srec.c: Likewise.
	* versados.c: Likewise.
opcodes/
	* aarch64-opc.c: Spell fall through comments consistently.
	* i386-dis.c: Likewise.
	* aarch64-dis.c: Add missing fall through comments.
	* aarch64-opc.c: Likewise.
	* arc-dis.c: Likewise.
	* arm-dis.c: Likewise.
	* i386-dis.c: Likewise.
	* m68k-dis.c: Likewise.
	* mep-asm.c: Likewise.
	* ns32k-dis.c: Likewise.
	* sh-dis.c: Likewise.
	* tic4x-dis.c: Likewise.
	* tic6x-dis.c: Likewise.
	* vax-dis.c: Likewise.
binutils/
	* dlltool.c: Spell fall through comments consistently.
	* objcopy.c: Likewise.
	* readelf.c: Likewise.
	* dwarf.c: Add missing fall through comments.
	* elfcomm.c: Likewise.
	* sysinfo.y: Likewise.
	* readelf.c: Likewise.  Also remove extraneous comments.
gas/
	* app.c: Add missing fall through comments.
	* dw2gencfi.c: Likewise.
	* expr.c: Likewise.
	* config/tc-alpha.c: Likewise.
	* config/tc-arc.c: Likewise.
	* config/tc-arm.c: Likewise.
	* config/tc-cr16.c: Likewise.
	* config/tc-crx.c: Likewise.
	* config/tc-dlx.c: Likewise.
	* config/tc-h8300.c: Likewise.
	* config/tc-hppa.c: Likewise.
	* config/tc-i370.c: Likewise.
	* config/tc-i386.c: Likewise.
	* config/tc-i960.c: Likewise.
	* config/tc-ia64.c: Likewise.
	* config/tc-m68hc11.c: Likewise.
	* config/tc-m68k.c: Likewise.
	* config/tc-mep.c: Likewise.
	* config/tc-metag.c: Likewise.
	* config/tc-microblaze.c: Likewise.
	* config/tc-mips.c: Likewise.
	* config/tc-ns32k.c: Likewise.
	* config/tc-rx.c: Likewise.
	* config/tc-score.c: Likewise.
	* config/tc-score7.c: Likewise.
	* config/tc-sh.c: Likewise.
	* config/tc-tic4x.c: Likewise.
	* config/tc-vax.c: Likewise.
	* config/tc-xstormy16.c: Likewise.
	* config/tc-z80.c: Likewise.
	* config/tc-z8k.c: Likewise.
	* config/obj-elf.c: Likewise.
	* config/tc-i386.c: Likewise.
	* depend.c: Spell fall through comments consistently.
	* config/tc-arm.c: Likewise.
	* config/tc-d10v.c: Likewise.
	* config/tc-i960.c: Likewise.
	* config/tc-ia64.c: Likewise.
	* config/tc-m68k.c: Likewise.
	* config/tc-mcore.c: Likewise.
	* config/tc-mep.c: Likewise.
	* config/tc-ns32k.c: Likewise.
	* config/tc-visium.c: Likewise.
	* config/tc-xstormy16.c: Likewise.
	* config/tc-z8k.c: Likewise.
gprof/
	* gprof.c: Add missing fall through comments.
ld/
	* lexsup.c: Spell fall through comments consistently and add
	missing fall through comments.
 2016-10-06 10:13:15 +10:30
Maciej W. Rozycki
7bd374a44d MIPS/GAS: Implement microMIPS branch/jump compaction 
Convert microMIPS branches and jumps whose delay slot would be filled by
a generated NOP instruction to the corresponding compact form where one
exists, in a manner similar to MIPS16 JR->JRC and JALR->JALRC swap.

Do so even where the transformation switches from a 16-bit to a 32-bit
branch encoding for no benefit in code size reduction, as this is still
advantageous.  This is because a branch/NOP pair takes 2 pipeline slots
or a 2-cycle completion latency except in superscalar implementations.
Whereas a compact branch may or may not stall on its target fetch, so it
will at most have a 2-cycle completion latency and may have only 1 even
in scalar implementations, and in superscalar implementations it is
expected to have no worse latency as a branch/NOP pair has.  Also it
won't stall and therefore take the extra latency cycle in the not-taken
case.

Technically this is the same as MIPS16 compaction: for the qualifying
instruction encodings the APPEND_ADD_COMPACT machine code generation
method is selected where APPEND_ADD_WITH_NOP otherwise would and tells
the code generator in `append_insn' to convert the regular form of an
instruction to its corresponding compact form.  For this the opcode is
tweaked as necessary and the microMIPS opcode table is scanned for the
matching updated instruction.  A non-$0 `rt' operand to BEQ and BNE
instructions is moved to the `rs' operand field of BEQZC and BNEZC
encodings as required.

Unlike with MIPS16 compaction however we need to handle out-of-distance
branch relaxation as well.  We do this by deferring the generation of
any delay-slot NOP required to relaxation made in `md_convert_frag', by
converting the APPEND_ADD_WITH_NOP machine code generation to APPEND_ADD
where a relaxed instruction is recorded.  Relaxation then, depending on
actual code produced, chooses between either using a compact branch or
jump encoding and emitting the NOP outstanding if no compact encoding is
possible.

For code simplicity's sake the relaxation pass is retained even if the
principle of preferring a compact encoding to a 16-bit branch/NOP pair
means, in the absence of out-of-range branch relaxation, that a single
compact branch machine code instruction will eventually be produced from
a given assembly source instruction.

	gas/
	* config/tc-mips.c (RELAX_MICROMIPS_ENCODE): Add `nods' flag.
	(RELAX_MICROMIPS_RELAX32, RELAX_MICROMIPS_TOOFAR16)
	(RELAX_MICROMIPS_MARK_TOOFAR16, RELAX_MICROMIPS_CLEAR_TOOFAR16)
	(RELAX_MICROMIPS_TOOFAR32, RELAX_MICROMIPS_MARK_TOOFAR32)
	(RELAX_MICROMIPS_CLEAR_TOOFAR32): Shift bits.
	(get_append_method): Also return APPEND_ADD_COMPACT for
	microMIPS instructions.
	(find_altered_mips16_opcode): Exclude macros from matching.
	Factor code out...
	(find_altered_opcode): ... to this new function.
	(find_altered_micromips_opcode): New function.
	(frag_branch_delay_slot_size): Likewise.
	(append_insn): Handle microMIPS branch/jump compaction.
	(macro_start): Likewise.
	(relaxed_micromips_32bit_branch_length): Likewise.
	(md_convert_frag): Likewise.
	* testsuite/gas/mips/micromips.s: Add conditional explicit NOPs
	for delay slot filling.
	* testsuite/gas/mips/micromips-b16.s: Add explicit NOPs for
	delay slot filling.
	* testsuite/gas/mips/micromips-size-1.s: Likewise.
	* testsuite/gas/mips/micromips.l: Adjust line numbers.
	* testsuite/gas/mips/micromips-warn.l: Likewise.
	* testsuite/gas/mips/micromips-size-1.l: Likewise.
	* testsuite/gas/mips/micromips.d: Adjust padding.
	* testsuite/gas/mips/micromips-trap.d: Likewise.
	* testsuite/gas/mips/micromips-insn32.d: Likewise.
	* testsuite/gas/mips/micromips-noinsn32.d: Likewise.
	* testsuite/gas/mips/micromips@beq.d: Update patterns for
	branch/jump compaction.
	* testsuite/gas/mips/micromips@bge.d: Likewise.
	* testsuite/gas/mips/micromips@bgeu.d: Likewise.
	* testsuite/gas/mips/micromips@blt.d: Likewise.
	* testsuite/gas/mips/micromips@bltu.d: Likewise.
	* testsuite/gas/mips/micromips@branch-misc-4.d: Likewise.
	* testsuite/gas/mips/micromips@branch-misc-4-64.d: Likewise.
	* testsuite/gas/mips/micromips@branch-misc-5.d: Likewise.
	* testsuite/gas/mips/micromips@branch-misc-5pic.d: Likewise.
	* testsuite/gas/mips/micromips@branch-misc-5-64.d: Likewise.
	* testsuite/gas/mips/micromips@branch-misc-5pic-64.d: Likewise.
	* testsuite/gas/mips/micromips@jal-svr4pic-local.d: Likewise.
	* testsuite/gas/mips/micromips@jal-svr4pic-local-n32.d:
	Likewise.
	* testsuite/gas/mips/micromips@jal-svr4pic-local-n64.d:
	Likewise.
	* testsuite/gas/mips/micromips@loc-swap.d: Likewise.
	* testsuite/gas/mips/micromips@loc-swap-dis.d: Likewise.
	* testsuite/gas/mips/micromips@relax.d: Likewise.
	* testsuite/gas/mips/micromips@relax-at.d: Likewise.
	* testsuite/gas/mips/micromips@relax-swap3.d: Likewise.
	* testsuite/gas/mips/branch-extern-2.d: Likewise.
	* testsuite/gas/mips/branch-extern-4.d: Likewise.
	* testsuite/gas/mips/branch-section-2.d: Likewise.
	* testsuite/gas/mips/branch-section-4.d: Likewise.
	* testsuite/gas/mips/branch-weak-2.d: Likewise.
	* testsuite/gas/mips/branch-weak-5.d: Likewise.
	* testsuite/gas/mips/micromips-branch-absolute.d: Likewise.
	* testsuite/gas/mips/micromips-branch-absolute-n32.d: Likewise.
	* testsuite/gas/mips/micromips-branch-absolute-n64.d: Likewise.
	* testsuite/gas/mips/micromips-branch-absolute-addend.d:
	Likewise.
	* testsuite/gas/mips/micromips-branch-absolute-addend-n32.d:
	Likewise.
	* testsuite/gas/mips/micromips-branch-absolute-addend-n64.d:
	Likewise.
	* testsuite/gas/mips/micromips-compact.d: New test.
	* testsuite/gas/mips/mips.exp: Run the new test.

	ld/
	* testsuite/ld-mips-elf/micromips-branch-absolute.d: Update
	patterns for branch compaction.
	* testsuite/ld-mips-elf/micromips-branch-absolute-addend.d:
	Likewise.

	opcodes/
	* micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
	"beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
	"j".
 2016-07-27 17:38:31 +01:00