This patch adds support for PLB invalidate operation (PLBI) instruction
and the corresponding system registers as operand (<plbi_op>).
Syntax: PLBI <plbi_op>{, <Xt>}
This instruction is an alias to "SYS #<op1>, C10, <Cm>, #<op2>{, <Xt>}"
and PLBI being the preferred disassembly.
The following list of system registers are supported in this patch for the
PLBI instructions enabled by "+poe2" flag and also the "nxs" variants of
these system registers are enabled by "+poe2+xs" flag.
* alle1
* alle1is
* alle1os
* alle2
* alle2is
* alle2os
* alle3
* alle3is
* alle3os
* aside1
* aside1is
* aside1os
* permae1
* permae1is
* permae1os
* perme1
* perme1is
* perme1os
* perme2
* perme2is
* perme2os
* perme3
* perme3is
* perme3os
* vmalle1
* vmalle1is
* vmalle1os
This patch adds support for FEAT_TEV feature enabled by "+tev"
flag along with support for following instructions.
* TENTER
* TEXIT
TENTER instruction uses the existing AARCH64_OPND_NOT_BALANCED_17 operand
to handle the not_balanced (NB) argument , where as a new operand
AARCH64_OPND_NOT_BALANCED_10 is added to support the NB (not_balanced)
argument in TEXIT instruction.
This patch adds support for FEAT_S1POE2 feature enabled by "+poe2"
flag along with support for following instructions.
* TCHANGEB (immediate)
* TCHANGEB (register)
* TCHANGEF (immediate)
* TCHANGEF (register)
A new operand AARCH64_OPND_NOT_BALANCED_17 is added to the code in this
patch to support the new optional argument "NB" (not_balanced) which
is a 1-bit field in the encoding for all the above mentioned
instructions.
Co-authored-by: Matthew Malcomson <matthew.malcomson@arm.com>
Avoid warnings about invalid escapes in etc/update-copyright.py by
using raw strings, add BinutilsFilter to skip psql.rc and add
"Kalray SA." as another copyright holder.
This patch includes:
- The feature flag for the FEAT_F16F32MM feature.
- Instruction FMMLA Half-precision matrix multiply-accumulate to single-precision.
This includes the instructions for the F16F32DOT feature:
- FDOT half-precision to single-precision, by element
- FDOT half-precision to single-precision, vector
This improves "nearby" section choice when memory regions are active,
preferring a section in the same region as the excluded section over
other sections.
PR 33726
include/
* bfdlink.h (struct bfd_link_callbacks): Add nearby_section.
(_bfd_nearby_section): Delete.
(bfd_fix_excluded_sec_syms): Rename and remove bfd param from
_bfd_fix_excluded_sec_syms.
bfd/
* linker.c (_bfd_nearby_section): Delete.
(fix_syms): Use linker callback.
* elflink.c (elf_link_input_bfd): Likewise.
(_bfd_elf_final_link): Update.
ld/
* ldemul.c (finish_default): Update.
* ldlang.c (lang_output_section_get): Delete.
(ldlang_nearby_section): New function.
* ldlang.h (ldlang_nearby_section): Declare.
(lang_output_section_get): New static inline.
* ldmain.c (link_callbacks): Add ldlang_nearby_section.
sframe_encoder_add_funcdesc () was added for SFRAME_VERSION_1. This has
since been obsoleted by introduction of SFRAME_VERSION_2 and its
corresponding sframe_decoder_add_funcdesc_v2 API.
Refactor the functionality into an internal-only API:
sframe_encoder_add_funcdesc_internal (). Ensure it returns the error
code for the caller to take necessary action or pass to user.
Keep only two args for sframe_encoder_add_funcdesc: function size and
function start addr. This simple barebone API will be used in a
subsequent commit to adjust the link-time behaviour of SFrame sections.
Reviewed-by: Jens Remus <jremus@linux.ibm.com>
include/
* sframe-api.h (sframe_encoder_add_funcdesc): Remove args to
create the barebone API.
libsframe/
* sframe.c (sframe_encoder_add_funcdesc): Refactor out into
sframe_encoder_add_funcdesc_internal. Change args.
(sframe_encoder_add_funcdesc_v2): Use the new internal API.
* libsframe.ver: Move sframe_encoder_add_funcdesc to 2.1 node.
Such a change for readability only. SFrame V1 is now obsolete, and with
newer versions like V3 or later, its likely better to have macro names
reflect the applicable version.
Add new macro names for FDE information related macros.
Reviewed-by: Jens Remus <jremus@linux.ibm.com>
include/
* sframe.h (SFRAME_V2_FUNC_INFO): New definition.
(SFRAME_V2_FUNC_FRE_TYPE): Likewise.
(SFRAME_V2_FUNC_PC_TYPE): Likewise.
(SFRAME_V2_FUNC_PAUTH_KEY): Likewise.
(SFRAME_V2_FUNC_INFO_UPDATE_PAUTH_KEY): Likewise.
... between specification and implmentation.
Move to definition in the implementation (gas/ld/libsframe) and not the
specification (include/sframe.h). At this time the implementation in
gas and ld generate the sections in the latest SFrame version only.
Reviewed-by: Jens Remus <jremus@linux.ibm.com>
bfd/
* elf-sframe.c: Add definition here.
gas/
* gen-sframe.c: Likewise.
libsframe/
* sframe.c: Likewise.
include/
* sframe.h: Remove the definition.
Currently, when SFrame sections are emitted after linking the input
SFrame sections, the SFrame FDEs are sorted on start PC. Doing so for
relocatable links has no effect (SFrame FDEs remain in place), because
the start PC is unrelocated data. For relocatable links, then, the
emitted SFrame FDEs in the output section remain in the same order as
that in the respective input BFD.
The assembler does not guarantee the emission of SFrame FDEs in the same
order as the placement of the associated .text* sections,
(SFRAME_F_FDE_SORTED is not set in the ET_REL objs generated by GAS).
This means setting SFRAME_F_FDE_SORTED by the linker was wrong when:
- doing relocatable link, and
- the input bfds contain multiple .text sections, say .text.hot,
.text.init, .text.unlikely etc.
For relocatable links, skip sorting the SFrame FDEs. Do not set
SFRAME_F_FDE_SORTED for relocatable links.
This is achieved by adding an explicit argument (bool sort_fde_p) to the
sframe_encoder_write API. Move the API from 2.0 to the 2.1 node as this
is an ABI-incompatible change. Skip bumping the "current" in
libsframe/libtool-version ATM, we will do so closer to release.
When writing of SFrame data for PLT entries, indicate sort_fde_p to
false: these sections are like the other SFrame sections for any other
ET_REL binary.
Add a test in ld/testsuite/ld-sframe/sframe.exp, these tests are run for
all ABIs supported for SFrame. In this test, for object file generated
for pr32789-1a.c:
- the emitted SFrame FDEs by GAS are in the order of the .text* in the
input assembly (i.e., .text.init, .text, .text.exit)
- the emitted .text* sections by GAS are placed in the following order
.text, .text.init, .text.exit.
- GAS does not set SFRAME_F_FDE_SORTED, as expected.
Reviewed-by: Jens Remus <jremus@linux.ibm.com>
bfd/
PR ld/32789
* elf-sframe.c (_bfd_elf_write_section_sframe): Skip sorting the
SFrame FDEs for relocatable links.
* elf64-s390.c (_bfd_s390_elf_write_sframe_plt): Additional
argument to sframe_encoder_write.
* elfxx-x86.c (_bfd_x86_elf_write_sframe_plt): Likewise.
libsframe/
* libsframe.ver: Move from 2.0 node to 2.1.
* sframe.c (sframe_encoder_write_sframe): Conditionalize based
on argument sort_fde_p.
(sframe_encoder_write): New argument to indicate whether SFrame
FDEs are to be sorted in output.
include/
* sframe-api.h (sframe_encoder_write): New argument.
ld/testsuite/
PR ld/32789
* ld/testsuite/ld-sframe/sframe.exp: New test.
* ld/testsuite/ld-sframe/pr32789-1.rd: New test.
* ld/testsuite/ld-sframe/pr32789-1.sd: New test.
* ld/testsuite/ld-sframe/pr32789-1a.c: New test.
* ld/testsuite/ld-sframe/pr32789-1b.c: New test.
* ld/testsuite/ld-x86-64/sframe-reloc-1.d: Remove
SFRAME_F_FDE_SORTED.
ud ui5, also known as amswap.w rd,$r1,rj(rd==rj), is displayed as
"ud ui5" by default during disassembly. Alternatively, the original
instruction can be printed using the objdump -M no-aliases.
To implement this support, a format specifier "ru0:5,ru5:5" for ud is
applied exclusively during disassembly. This specifier indicates that
registers should be printed using their corresponding numeric values,
and when the instruction is identified as ud, only a single parameter
is displayed.
binutils/
* testsuite/binutils-all/loongarch64/dis-amswap-ud-noaliases.d:
New test.
* testsuite/binutils-all/loongarch64/dis-amswap-ud.d: New test.
* testsuite/binutils-all/loongarch64/dis-amswap-ud.s: New test.
gas/
* testsuite/gas/loongarch/macro_ud.d: Update test.
include/
* opcode/loongarch.h: New macro.
opcodes/
* loongarch-dis.c (get_loongarch_opcode_by_binfmt): Correct match `ud`.
(dis_one_arg): Disassemble the `ud` parameter.
* loongarch-opc.c: Add opcode for "ud" alias.
This patch adds support for new BTI <target> "r" (instruction: bti r),
which is an alias to "bti" (with no target), for both "bti" and "bti r"
the preferred disassembly is "bti r". This "bti r" instruction is by
default available from Armv8-A architecture.
The HINT_OPD_F_NOPRINT macro has become redundant with these changes
and has been removed.
There's no need to have a separate reloc per arch; just like for other
more or less generic ones a single one will (mostly) do. Arm64, C-Sky,
and KVX - sadly - are exceptions.
There's no need to have a separate reloc per arch; just like for other
more or less generic ones a single one will (mostly) do. Arm64, C-Sky,
and KVX - sadly - are exceptions.
There's no need to have a separate reloc per arch; just like for other
more or less generic ones a single one will (mostly) do. Arm64, C-Sky,
and KVX - sadly - are exceptions.
There's no need to have a separate reloc per arch; just like for other
more or less generic ones a single one will (mostly) do. Arm64, C-Sky,
and KVX - sadly - are exceptions.
LA32 and LA32R do not have pcaddu18i.
LA32R does not have pcalau12i.
Add R_LARCH_CALL30 for pcaddu12i + jirl used in LA32 and LA32R.
Add R_LARCH_*_PCADD_HI20 for pcaddu12i used in LA32R.
Add R_LARCH_*_PCADD_LO12 for addi.w/ld.w used in LA32R.
In the "ud ui5" macro, the value of ui5 must be in the range 0–31. It
expands to "amswap.w $rd, $r1, $rj", where ui5 specifies the register
number for $rd in the amswap.w instruction, and $rd == $rj.
The test case have been adjusted to no longer report errors for illegal
operands of the amswap.w instruction.
gas/
* config/tc-loongarch.c (check_this_insn_before_appending): No
longer check amswap.w.
* testsuite/gas/loongarch/illegal-operand.l: Update.
* testsuite/gas/loongarch/illegal-operand.s: Update.
* testsuite/gas/loongarch/macro_ud.d: New test.
* testsuite/gas/loongarch/macro_ud.s: New test.
include/
* opcode/loongarch.h: Add new macro for amswap.w.
opcodes/
* loongarch-opc.c: Add macro for ud.
On Solaris 11.4, there is SHT_SUNW_symnsort and no SHT_SUNW_symtabnsort.
SHT_SUNW_symnsort is defined to 0x6fffffec, which is the same as
SHT_SUNW_symtabnsort. There is also SHT_SUNW_ctf. Add SHT_SUNW_ctf and
rename SHT_SUNW_symtabnsort to SHT_SUNW_symnsort. Move SHT_SUNW_phname
after SHT_SUNW_symnsort.
binutils/
* readelf.c (get_solaris_section_type): Add SHT_SUNW_ctf and
SHT_SUNW_symnsort. Move SHT_SUNW_phname after SHT_SUNW_symnsort.
Remove SHT_SUNW_symtabnsort.
include/
* elf/common.h (SHT_SUNW_ctf): New.
(SHT_SUNW_symtabnsort): Renamed to ...
(SHT_SUNW_symnsort): This.
(SHT_SUNW_phname): Moved after SHT_SUNW_symnsort.
Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
This field is used differently during assembly and disassembly. It
would be nice if we could make this more consistent, but for now just
extend the comment to explain what is going on.
Currently some of the instructions in bitmanip extensions can not be obtained
using DECLARE_INSN macros. I generated them using riscv-opcodes and added to
other opcodes.
Approved-By: Nelson Chu <nelson@rivosinc.com>
The Floating Point Mode Register is a new register which controls the
behaviour of FP8 instructions. This is handled by the Linux kernel
through a new NT_ARM_FPMR register set.
This patch adds required code to support core file dumps with
NT_ARM_FPMR in them.
Addressing (an old) review comment suggesting this housekeeping item.
Use consistent naming style in libsframe. sframe_decoder_ctx objects
are named 'dctx', so use 'ectx' for sframe_encoder_ctx objects.
Make necessary changes in all the applicable declarations and definitions.
Reviewed-by: Jens Remus <jremus@linux.ibm.com>
Update readelf to display the base symbol version as
Symbol table for image contains 5 entries:
Num: Value Size Type Bind Vis Ndx Name
0: 0000000000000000 0 NOTYPE LOCAL DEFAULT UND
1: 0000000000003008 0 OBJECT GLOBAL DEFAULT 10 bar@@
2: 0000000000000000 0 OBJECT GLOBAL DEFAULT ABS VERS_1
3: 0000000000003008 0 OBJECT GLOBAL DEFAULT 10 bar@@VERS_1
4: 0000000000003000 0 OBJECT GLOBAL DEFAULT 10 foo@
instead of
Symbol table for image contains 5 entries:
Num: Value Size Type Bind Vis Ndx Name
0: 0000000000000000 0 NOTYPE LOCAL DEFAULT UND
1: 0000000000003008 0 OBJECT GLOBAL DEFAULT 10 bar
2: 0000000000000000 0 OBJECT GLOBAL DEFAULT ABS VERS_1
3: 0000000000003008 0 OBJECT GLOBAL DEFAULT 10 bar@@VERS_1
4: 0000000000003000 0 OBJECT GLOBAL DEFAULT 10 foo
That is bar@@ and foo@ vs bar and foo.
binutils/
PR binutils/33599
* readelf.c (process_version_sections): Replace 0x8001 with
(VERSYM_HIDDEN | VERSYM_BASE).
(get_symbol_version_string): Likewise. Return "" for the base
version.
include/
PR binutils/33599
* elf/common.h (VERSYM_BASE): New.
ld/
PR binutils/33599
* testsuite/ld-elf/pr33599.d: New file.
* testsuite/ld-elf/pr33599.map: Likewise.
* testsuite/ld-elf/pr33599.s: Likewise.
Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
Change argument names (in declaration) to SF_BUF and SF_SIZE (instead of
the current CF_BUF and CF_SIZE respectively).
include/
* sframe-api.h (sframe_decode): Fix typos. Use same name as
used for the definition.
There's no need for a hook; what needs doing is uniform, the question is
only whether to perform any merging (i.e. whether other parts of a backend
are capable of dealing with the effects).
Where _bfd_nolink_bfd_merge_sections() was used, false is hardcoded. For
ELF no real target override is permitted; true is hardcoded except for the
cases where bfd_generic_merge_sections() was used as the hook function
before.
As SFrame format evolves, this will be useful to refer to v2 on-disk
layout directly as the format evolves.
Reviewed-by: Jens Remus <jremus@linux.ibm.com>
include/
* sframe.h (struct sframe_func_desc_entry): Rename to tag v2.
In DWARF CFI an "undefined" register rule for the return address (RA)
register indicates that there is no return address and the stack trace
is complete.
Represent DW_CFA_undefined as SFrame FRE without any offsets, so that a
stack tracer implementation can use this as indication that an outermost
frame has been reached and the stack trace is complete.
This representation is backward compatible, as existing stack tracers
should already deal with the case, that an SFrame FRE a so far invalid
offset count of zero and stop the trace.
include/
* sframe.h (SFRAME_V2_FRE_RA_UNDEFINED_P): New macro to test
FRE info word for RA undefined (FRE without any offsets).
binutils/
* NEWS: Mention SFrame can represent an undefined RA as FRE
without any offsets.
gas/
* gen-sframe.h (struct sframe_row_entry): Add ra_undefined_p
flag.
* gen-sframe.c (sframe_row_entry_new): Initialize ra_undefined_p
flag to not set.
(sframe_row_entry_initialize): Treat ra_undefined_p flag as
sticky.
(sframe_fre_set_ra_track): Reset ra_undefined_p flag.
(sframe_xlate_do_restore): Reset ra_undefined_p flag to saved
state.
(sframe_xlate_do_same_value): Reset ra_undefined_p flag.
(sframe_xlate_do_cfi_undefined): For RA set ra_undefined_p flag.
(output_sframe_row_entry): Represent RA undefined as SFrame FRE
without any offsets and FRE info word fields zeroed.
* NEWS: Mention assembler represents .cfi_undefined RA in SFrame
as FRE without any offsets.
libsframe/
* doc/sframe-spec.texi (Changes from Version 1 to Version 2):
Mention that a SFrame FRE without any offsets flag indicates an
outermost frame with an undefined RA.
(fre_offset_count): Document that a FRE offset count of zero
indicates an outermost frame with an undefined RA.
* sframe.c (sframe_get_fre_ra_undefined_p): Use macro
SFRAME_V2_FRE_RA_UNDEFINED_P.
(sframe_fre_get_fp_offset, sframe_fre_get_ra_offset): Do not
return fixed FP/RA offset if RA undefined.
* sframe-dump.c (dump_sframe_func_with_fres): Show FRE without
any offsets as "RA undefined".
gas/testsuite/
* gas/cfi-sframe/cfi-sframe.exp: Run tests for .cfi_undefined RA
on AArch64, s390x, and x86-64.
* gas/cfi-sframe/cfi-sframe-aarch64-ra-undefined-1.d: Add test
for .cfi_undefined RA on AArch64.
* gas/cfi-sframe/cfi-sframe-aarch64-ra-undefined-1.s: Likewise.
* as/cfi-sframe/cfi-sframe-s390x-ra-undefined-1.d: Add test
for .cfi_undefined RA on s390x.
* gas/cfi-sframe/cfi-sframe-s390x-ra-undefined-1.s: Likewise.
* gas/cfi-sframe/cfi-sframe-x86_64-ra-undefined-1.d: Add test
for .cfi_undefined RA on x86-64.
* gas/cfi-sframe/cfi-sframe-x86_64-ra-undefined-1.s: Likewise.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
SFrame FREs without any offsets will later be used to represent an
undefined return address (RA) in SFrame. This API can then be used,
for instance by libsframe when dumping SFrame stack trace information
(e.g. in objdump and readelf), to test for RA undefined. Other users
of libsframe need the same capability.
include/
* sframe-api.h (sframe_fre_get_ra_undefined_p): New declaration.
libsframe/
* libsframe.ver (sframe_fre_get_ra_undefined_p): List new API.
* sframe.c (sframe_fre_get_ra_undefined_p): New definition.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
A check in print_insn_aarch64_word asserted that part of the encoding
space couldn't contain any valid encodings, and then returned ERR_NYI
("Not Yet Implemented", perhaps?) for these values. However, some of
the new FEAT_MOP4 instructions will trigger the assert. The check seems
to be outdated, and is clearly no longer valid, so it can just be
deleted.
Additionally, there are no other assignments of ERR_NYI, so delete all
remaining references to this error type.
Add new instructions from the Generic Interrupt Controller, GICv5,
extension. These instructions are aliases to system instructions and are
the following:
* gic <operation>, <reg>
* gicr <reg>, <operation>
* gsb <operation>
Generic Interrupt Controller v5, GICv5, adds new system registers
and system instructions. These are enabled with the +gcie flag, where
gcie stands for GICv5 (Generic Interrupt Controller) CPU Interrupt
Extension.
