I got a request said that the JDK multi-thread compiler may be broken
if two or more threads are trying to print/disassemble stuff, and filling
the disassemble_info, setting callbacks, and grabbing the function pointer
to disasm at the same time. Since such as the target global static stuff,
including subset of extensions and mapping symbol stuff, seems to only be
one globally. Ideally, for dis-assembler, all global static target stuff
should/can be better to be defined into the target private data, since they
are target-dependency.
opcodes/
* riscv-dis.c: Moved all global static target-dependency stuff into
riscv_private_data, including architecture and mapping symbol stuff.
(set_default_riscv_dis_options): Updated since global static target-
dependency stuff are moved into riscv_private_data.
(parse_riscv_dis_option_without_args): Likewise.
(parse_riscv_dis_option): Likewise.
(parse_riscv_dis_options): Likewise.
(maybe_print_address): Likewise.
(print_reg_list): Likewise.
(riscv_get_spimm): Likewise.
(print_insn_args): Likewise.
(riscv_disassemble_insn): Likewise.
(riscv_update_map_state): Likewise.
(riscv_search_mapping_symbol): Likewise.
(riscv_data_length): Likewise.
(print_insn_riscv): Likewise. Call the riscv_init_disasm_info before
parsing any disassembler options, since the related stuff are moved
into riscv_private_data.
(riscv_init_disasm_info): Likewise. Parse and set the architecture
string and privileged spec version since riscv_get_disassembler is
no longer needed.
(riscv_get_disassembler): Removed.
(disassemble_free_riscv): Only free the subset_list if
riscv_private_data exsits.
* disassemble.c (disassembler): Since riscv_get_disassembler is
removed, call to print_insn_riscv.
* disassemble.h: Removed extern riscv_get_disassembler.
As of commit e43d8768d9 ("RISC-V: Fix disassemble fetch fail return
value.") partial instructions are no longer displayed by objdump. While
that commit fixed the behavior of print_insn_riscv() returning the
arbitrary status value upon failure, it caused the behavior of dumping
instructions to change. Allow partial instructions to be displayed once
again and only return -1 if no part of the instruction was able to be
displayed.
Fixes: e43d8768d9 ("RISC-V: Fix disassemble fetch fail return
value.")
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Acked-By: Andrew Burgess <aburgess@redhat.com>
I build gdb on arm-linux and ran into:
...
CC riscv-dis.lo
opcodes/riscv-dis.c: In function ‘print_insn_args’:
opcodes/riscv-dis.c:743:29: error: format ‘%lu’ expects argument of type \
‘long unsigned int’, but argument 4 has type ‘insn_t’ \
{aka ‘long long unsigned int’} [-Werror=format=]
743 | "%lu", EXTRACT_ZCMT_INDEX (l));
| ~~^
| |
| long unsigned int
| %llu
...
Fix this by printing the insn_t value, which is a uint64_t, using PRIu64.
Tested by finishing the build.
This patch supports Zcmt[1] instruction 'cm.jt' and 'cm.jalt'.
Add new CSR jvt for tablejump using. Since 'cm.jt' and 'cm.jalt'
have the same instructiong encoding, use 'match_cm_jt' and 'match_cm_jalt'
check the 'zcmt_index' field to distinguish them.
[1] https://github.com/riscvarchive/riscv-code-size-reduction/releases
Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
Co-Authored by: Simon Cook <simon.cook@embecosm.com>
Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): New extension.
(riscv_multi_subset_supports_ext): Ditto.
gas/ChangeLog:
* config/tc-riscv.c (enum riscv_csr_class): New CSR.
(riscv_csr_address): Ditto.
(validate_riscv_insn): New operand.
(riscv_ip): Ditto.
* testsuite/gas/riscv/csr-version-1p10.d: New CSR.
* testsuite/gas/riscv/csr-version-1p10.l: Ditto.
* testsuite/gas/riscv/csr-version-1p11.d: Ditto.
* testsuite/gas/riscv/csr-version-1p11.l: Ditto.
* testsuite/gas/riscv/csr-version-1p12.d: Ditto.
* testsuite/gas/riscv/csr-version-1p12.l: Ditto.
* testsuite/gas/riscv/csr.s: Ditto.
* testsuite/gas/riscv/march-help.l: New extension.
* testsuite/gas/riscv/zcmt-fail.d: New test.
* testsuite/gas/riscv/zcmt-fail.l: New test.
* testsuite/gas/riscv/zcmt-fail.s: New test.
* testsuite/gas/riscv/zcmt.d: New test.
* testsuite/gas/riscv/zcmt.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_CM_JT): New opcode.
(MASK_CM_JT): New mask.
(MATCH_CM_JALT): New opcode.
(MASK_CM_JALT): New mask.
(CSR_JVT): New CSR.
(DECLARE_INSN): New declaration.
(DECLARE_CSR): Ditto.
* opcode/riscv.h (EXTRACT_ZCMT_INDEX): New marco.
(ENCODE_ZCMT_INDEX): Ditto.
(enum riscv_insn_class): New class.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): New operand.
* riscv-opc.c (match_cm_jt): New function.
(match_cm_jalt): Ditto.
Since QEMU have supported -Max option to to enable all normal extensions,
the dis-assembler should also add an option, -M,max to do the same thing.
For the instruction, which have overlapped encodings like zfinx, will not
be considered by the -M,max option.
opcodes/
* riscv-dis.c (all_ext): New static boolean. If set, disassemble
without checking architectire string.
(riscv_disassemble_insn): Likewise.
(parse_riscv_dis_option_without_args): Recognized -M,max option.
binutils/
* NEWS: Updated.
.insn or data emitted inside text sections can lead to positions not
being at insn granularity. In such situations using alignment
directives should reliably enforce the requested alignment.
Specifically requests to align back to insn granularity may not be
ignored (where, as a subcase thereof, the ordering of ".option norvc"
and e.g. ".p2align 2" should not matter; so far the alignment directive
needs to come first to have any effect). Similarly ahead of emitting
NOPs alignment first needs to be forced back to insn granularity.
The new testcases actually point out a corner case issue in the
disassembler as well, which is being corrected at the same time: We
don't want to print "0x" without any subsequent digits.
This patch supports Zcmp instruction 'cm.mva01s' and 'cm.mvsa01'.
All disassemble instructions use the sreg format.
Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
Co-Authored by: Simon Cook <simon.cook@embecosm.com>
Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>
gas/ChangeLog:
PR 32036
* NEWS: Updated.
* config/tc-riscv.c (validate_riscv_insn): New operators.
(riscv_ip): Ditto.
* testsuite/gas/riscv/zcmp-mv.d: New test.
* testsuite/gas/riscv/zcmp-mv.s: New test.
include/ChangeLog:
PR 32036
* opcode/riscv-opc.h (MATCH_CM_MVA01S): New opcode.
(MASK_CM_MVA01S): New mask.
(MATCH_CM_MVSA01): New opcode.
(MASK_CM_MVSA01): New mask.
(DECLARE_INSN): New declarations.
* opcode/riscv.h (OP_MASK_SREG1): New mask.
(OP_SH_SREG1): New operand code.
(OP_MASK_SREG2): New mask.
(OP_SH_SREG2): New operand code.
(X_A0): New reg number.
(X_A1): Ditto.
(X_S7): Ditto.
(RISCV_SREG_0_7): New macro function.
opcodes/ChangeLog:
PR 32036
* riscv-dis.c (riscv_zcmp_get_sregno): New function.
(print_insn_args): New operators.
* riscv-opc.c (match_sreg1_not_eq_sreg2): New match function.
The previous commit removed a use of disassemble_info::fprintf_func
which had been added to the RISC-V disassembler after the disassembler
had been switched to use ::fprintf_styled_func, for styled output.
To prevent future mistakes, I propose adding a #define to rename
fprintf_func to something which does not exist. If this had been in
place then the before the previous commit libopcodes would have failed
to compile, like this:
../../src/opcodes/riscv-dis.c: In function ‘print_reg_list’:
../../src/opcodes/riscv-dis.c:229:7: error: ‘disassemble_info’ {aka ‘struct disassemble_info’} has no member named ‘please_use_fprintf_styled_func_instead’
229 | info->fprintf_func (info->stream, "%s", riscv_gpr_names[X_RA]);
| ^~
If this commit is accepted then I'll follow up with another commit
that adds the same #define to every disassembler that has been
converted to use styled output.
As the RISC-V disassembler is now fully styled, this commit should
make no difference at all.
I noticed that some unstyled output had crept into the risc-v
disassembler in this commit:
commit 9132c8152b
Date: Tue Feb 27 11:48:11 2024 +0800
RISC-V: Support Zcmp push/pop instructions.
this commit adds styling support. The risc-v disassembler is now once
again, fully styled.
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
Contributors:
Mary Bennett <mary.bennett682@gmail.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
Helene Chelin <helene.chelin@embecosm.com>
Nazareno Bruschi <nazareno.bruschi@embecosm.com>
Lin Sinan
include/ChangeLog:
* opcode/riscv-opc.h: Add corresponding MATCH and MASK
macros for XCVbi.
* opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros
for XCVbi.
(enum riscv_insn_class): Add the XCVbi instruction class.
gas/ChangeLog:
* config/tc-riscv.c (validate_riscv_insn): Add the necessary
operands for the extension.
(riscv_ip): Likewise.
* doc/c-riscv.texi: Note XCVbi as an additional ISA extension
for CORE-V.
* testsuite/gas/riscv/cv-bi-beqimm.d: New test.
* testsuite/gas/riscv/cv-bi-beqimm.s: New test.
* testsuite/gas/riscv/cv-bi-bneimm.d: New test.
* testsuite/gas/riscv/cv-bi-bneimm.s: New test.
* testsuite/gas/riscv/cv-bi-fail-march.d: New test.
* testsuite/gas/riscv/cv-bi-fail-march.l: New test.
* testsuite/gas/riscv/cv-bi-fail-march.s: New test.
* testsuite/gas/riscv/cv-bi-fail-operand-01.d: New test.
* testsuite/gas/riscv/cv-bi-fail-operand-01.l: New test.
* testsuite/gas/riscv/cv-bi-fail-operand-01.s: New test.
* testsuite/gas/riscv/cv-bi-fail-operand-02.d: New test.
* testsuite/gas/riscv/cv-bi-fail-operand-02.l: New test.
* testsuite/gas/riscv/cv-bi-fail-operand-02.s: New test.
* testsuite/gas/riscv/cv-bi-fail-operand-03.d: New test.
* testsuite/gas/riscv/cv-bi-fail-operand-03.l: New test.
* testsuite/gas/riscv/cv-bi-fail-operand-03.s: New test.
* testsuite/gas/riscv/march-help.l: Add xcvbi string.
include/ChangeLog:
* opcode/riscv-opc.h: Add corresponding MATCH and MASK
macros for XCVbi.
* opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros
for XCVbi.
(enum riscv_insn_class): Add the XCVbi instruction class.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Add disassembly for new operand.
* riscv-opc.c: Add XCVbi instructions.
With previous behaviour, multiple mapping symbols within the same
function would result in all the mapping symbols being searched.
This could slow down disassembly dramatically.
Multiple mapping symbols within a function can be a result of encoding
instructions as data, like sometimes seen in random instruction
generators.
opcodes/ChangeLog:
* riscv-dis.c (riscv_search_mapping_symbol): Use last mapping
symbol if it exists.
Support zcmp extension push/pop/popret and popret zero instructions.
The `reg_list' is a list containing 1 to 13 registers, we can use:
"{ra}, {ra, s0}, {ra, s0-s1}, {ra, s0-s2} ... {ra, s0-sN}"
to present this feature.
Passed gcc/binutils regressions of riscv-gnu-toolchain.
Most of work was finished by Sinan Lin.
Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
Co-Authored by: Simon Cook <simon.cook@embecosm.com>
Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_implicit_subset): Imply zca for zcmp.
(riscv_supported_std_z_ext): Added zcmp with version 1.0.
(riscv_parse_check_conflicts): Zcmp conflicts with d/zcd.
(riscv_multi_subset_supports): Handle zcmp.
(riscv_multi_subset_supports_ext): Ditto.
gas/ChangeLog:
* NEWS: Updated.
* config/tc-riscv.c (regno_to_reg_list): New function, used to map
register to reg_list number.
(reglist_lookup): Called reglist_lookup_internal. Return false if
reg_list number is zero, which is an invalid value.
(reglist_lookup_internal): Parse register list, and return the last
register by regno_to_reg_list.
(validate_riscv_insn): New operators.
(riscv_ip): Ditto.
* testsuite/gas/riscv/march-help.l: Updated.
* testsuite/gas/riscv/zcmp-push-pop-fail.d: New test.
* testsuite/gas/riscv/zcmp-push-pop-fail.l: New test.
* testsuite/gas/riscv/zcmp-push-pop-fail.s: New test.
* testsuite/gas/riscv/zcmp-push-pop.d: New test.
* testsuite/gas/riscv/zcmp-push-pop.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH/MASK_CM_PUSH): New macros for zcmp.
(MATCH/MASK_CM_POP): Ditto.
(MATCH/MASK_CM_POPRET): Ditto.
(MATCH/MASK_CM_POPRETZ): Ditto.
(DECLARE_INSN): New declarations for zcmp.
* opcode/riscv.h (EXTRACT/ENCODE/VALID_ZCMP_SPIMM): Handle spimm
operand for zcmp.
(OP_MASK_REG_LIST): Handle operand for zcmp register list.
(OP_SH_REG_LIST): Ditto.
(ZCMP_SP_ALIGNMENT): New argument, used in riscv_get_sp_base.
(X_S0, X_S1, X_S2, X_S10, X_S11): New register numbers.
(enum riscv_insn_class): Added INSN_CLASS_ZCMP.
(extern riscv_get_sp_base): Added.
opcodes/ChangeLog:
* riscv-dis.c (print_reg_list): New function, used to get zcmp
reg_list field.
(riscv_get_spimm): New function, used to get zcmp sp adjustment
immediate.
(print_insn_args): Handle new operands for zcmp.
* riscv-opc.c (riscv_get_sp_base): New function, used by gas and
objdump. Get sp base adjustment.
(riscv_opcodes): Added zcmp instructions.
Since the particularity of "th.vsetvli" was not taken into account in the
initial support patches for XTheadVector, the program operation failed
due to instruction coding errors. According to T-Head SPEC ([1]), the
"vsetvl" in the XTheadVector extension consists of SEW, LMUL and EDIV,
which is quite different from the "V" extension. Therefore, we cannot
simply reuse the processing of vsetvl in V extension.
We have set up tens of thousands of test cases to ensure that no
further encoding issues are there, and and execute all compiled test
files on real HW and make sure they don't trigger SIGILL.
Ref:
[1] https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
gas/ChangeLog:
* config/tc-riscv.c (validate_riscv_insn): Add handling for
th.vsetvli.
(my_getThVsetvliExpression): New function.
(riscv_ip): Likewise.
* testsuite/gas/riscv/x-thead-vector.d: Likewise.
* testsuite/gas/riscv/x-thead-vector.s: Likewise.
include/ChangeLog:
* opcode/riscv.h (OP_MASK_XTHEADVLMUL): New macro.
(OP_SH_XTHEADVLMUL): Likewise.
(OP_MASK_XTHEADVSEW): Likewise.
(OP_SH_XTHEADVSEW): Likewise.
(OP_MASK_XTHEADVEDIV): Likewise.
(OP_SH_XTHEADVEDIV): Likewise.
(OP_MASK_XTHEADVTYPE_RES): Likewise.
(OP_SH_XTHEADVTYPE_RES): Likewise.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Likewise.
* riscv-opc.c: Likewise.
Adds two new external authors to etc/update-copyright.py to cover
bfd/ax_tls.m4, and adds gprofng to dirs handled automatically, then
updates copyright messages as follows:
1) Update cgen/utils.scm emitted copyrights.
2) Run "etc/update-copyright.py --this-year" with an extra external
author I haven't committed, 'Kalray SA.', to cover gas testsuite
files (which should have their copyright message removed).
3) Build with --enable-maintainer-mode --enable-cgen-maint=yes.
4) Check out */po/*.pot which we don't update frequently.
riscv_is_mapping_symbol currently accepts any symbol that starts with $x
or $d. This patch makes the check more strict, requiring exactly $x, $d,
or $xrv. It also makes use of this stricter mapping in
riscv_is_valid_mapping_symbol.
ChangeLog:
* bfd/cpu-riscv.c (riscv_elf_is_mapping_symbols): Match only
strings that are exactly $x, $d, or $xrv.
* opcodes/riscv-dis.c (riscv_is_valid_mapping_symbol): Use
riscv_elf_is_mapping_symbols.
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
SiFive has define as set of flexible instruction for extending vector
coprocessor, it able to encoding opcode like .insn but with predefined
format.
List of instructions:
sf.vc.x
sf.vc.i
sf.vc.vv
sf.vc.xv
sf.vc.iv
sf.vc.fv
sf.vc.vvv
sf.vc.xvv
sf.vc.ivv
sf.vc.fvv
sf.vc.vvw
sf.vc.xvw
sf.vc.ivw
sf.vc.fvw
sf.vc.v.x
sf.vc.v.i
sf.vc.v.vv
sf.vc.v.xv
sf.vc.v.iv
sf.vc.v.fv
sf.vc.v.vvv
sf.vc.v.xvv
sf.vc.v.ivv
sf.vc.v.fvv
sf.vc.v.vvw
sf.vc.v.xvw
sf.vc.v.ivw
sf.vc.v.fvw
Spec of Xsfvcp
https://www.sifive.com/document-file/sifive-vector-coprocessor-interface-vcix-software
Co-authored-by: Hau Hsu <hau.hsu@sifive.com>
Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
Currently objdump gets and updates the map state once per symbol. Updating the
state (partiularly riscv_parse_subset) is expensive and grows quadratically
since we iterate over all symbols. By deferring this until once we've found the
symbol of interest, we can reduce the time to dump a 4k insn file of .norvc and
.rvc insns from ~47 seconds to ~0.13 seconds.
opcodes/ChangeLog:
* riscv-dis.c (riscv_get_map_state): Remove state updating logic
and rename to riscv_is_valid_mapping_symbol.
(riscv_update_map_state): Add state updating logic to seperate function.
(riscv_search_mapping_symbol): Use new riscv_update_map_state.
(riscv_data_length): Ditto.
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
While for some of the macro insns using x0 is kind of okay, as they
would merely resolve to a sequence of hint insns (and hence not cause
misbehavior at runtime), several of them have the degenerate AUIPC
followed by a load, store, or branch using other than the designated
symbol as address and hence causing runtime issues. Refuse to assemble
those, leveraging that the matching function so far wasn't really used
for macro insns: NULL is now allowed, indicating a match (which imo is
preferable over converting match_never() to match_always()), while
other matching functions now (also) used for macro insns need to avoid
calling match_opcode().
Note that for LA the restriction is slightly too strict: In non-PIC mode
using x0 would be okay-ish as per above (as it's just LLA there). Yet
libopcodes doesn't know what mode gas is presently assembling for, so we
want to err on the safe side.
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the CSRs for XTheadVector. Because of the
conflict between encoding and teh 'V' extension, it is implemented
by alias. The 'th' prefix and the "XTheadVector" extension are
documented in a PR for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
gas/ChangeLog:
* config/tc-riscv.c (enum riscv_csr_class): Add the class for
the CSRs of the "XTheadVector" extension.
(riscv_csr_address): Likewise.
* testsuite/gas/riscv/x-thead-vector-csr-warn.d: New test.
* testsuite/gas/riscv/x-thead-vector-csr-warn.l: New test.
* testsuite/gas/riscv/x-thead-vector-csr.d: New test.
* testsuite/gas/riscv/x-thead-vector-csr.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (DECLARE_CSR_ALIAS): Likewise.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Prefix the CSRs disassembly with 'th'.
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
Contributors:
Mary Bennett <mary.bennett@embecosm.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
Helene Chelin <helene.chelin@embecosm.com>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Added `xcvalu`
instruction class.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* config/tc-riscv.c (validate_riscv_insn): Added the necessary
operands for the extension.
(riscv_ip): Likewise.
* doc/c-riscv.texi: Noted XCValu as an additional ISA extension
for CORE-V.
* testsuite/gas/riscv/cv-alu-boundaries.d: New test.
* testsuite/gas/riscv/cv-alu-boundaries.l: New test.
* testsuite/gas/riscv/cv-alu-boundaries.s: New test.
* testsuite/gas/riscv/cv-alu-fail-march.d: New test.
* testsuite/gas/riscv/cv-alu-fail-march.l: New test.
* testsuite/gas/riscv/cv-alu-fail-march.s: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-01.d: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-01.l: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-01.s: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-02.d: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-02.l: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-02.s: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-03.d: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-03.l: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-03.s: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-04.d: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-04.l: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-04.s: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-05.d: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-05.l: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-05.s: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-06.d: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-06.l: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-06.s: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-07.d: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-07.l: New test.
* testsuite/gas/riscv/cv-alu-fail-operand-07.s: New test.
* testsuite/gas/riscv/cv-alu-insns.d: New test.
* testsuite/gas/riscv/cv-alu-insns.s: New test.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Disassemble xcb operand.
* riscv-opc.c: Defined the MASK and added XCValu instructions.
include/ChangeLog:
* opcode/riscv-opc.h: Added corresponding MATCH and MASK macros
for XCValu.
* opcode/riscv.h: Added corresponding EXTRACT and ENCODE macros
for XCValu.
(enum riscv_insn_class): Added the XCValu instruction class.
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
Contributors:
Mary Bennett <mary.bennett@embecosm.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
Helene Chelin <helene.chelin@embecosm.com>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Added `xcvmac`
instruction class.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* config/tc-riscv.c (validate_riscv_insn): Added the necessary
operands for the extension.
(riscv_ip): Likewise.
* doc/c-riscv.texi: Noted XCVmac as an additional ISA extension
for CORE-V.
* testsuite/gas/riscv/cv-mac-fail-march.d: New test.
* testsuite/gas/riscv/cv-mac-fail-march.l: New test.
* testsuite/gas/riscv/cv-mac-fail-march.s: New test.
* testsuite/gas/riscv/cv-mac-fail-operand.d: New test.
* testsuite/gas/riscv/cv-mac-fail-operand.l: New test.
* testsuite/gas/riscv/cv-mac-fail-operand.s: New test.
* testsuite/gas/riscv/cv-mac-insns.d: New test.
* testsuite/gas/riscv/cv-mac-insns.s: New test.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Disassemble information with
the EXTRACT macro implemented.
* riscv-opc.c: Defined the MASK and added
XCVmac instructions.
include/ChangeLog:
* opcode/riscv-opc.h: Added corresponding MATCH and MASK macros
for XCVmac.
* opcode/riscv.h: Added corresponding EXTRACT and ENCODE macros
for uimm.
(enum riscv_insn_class): Added the XCVmac instruction class.
The elf psabi allows for mapping symbols to be of the form $x<ISA>.<any>
opcodes/
* riscv-dis.c (riscv_get_map_state): allow mapping symbol to
be suffixed by a unique identifier .<any>
The vendor operands should be named starting with `X', and preferably the
second letter (or multiple following letters) is enough to differentiate
them from other vendors.
Therefore, added letter `t' after `X' for t-head operands, to differentiate
from future different vendor's operands.
bfd/
* elfxx-riscv.c (riscv_supported_vendor_x_ext): Removed the vendor
document link since it should already be recorded in the
gas/doc/c-riscv.texi.
gas/
* config/tc-riscv.c (validate_riscv_insn): Added `t' after `X' for
t-head operands. Minor updates for indents and comments.
(riscv_ip): Likewise.
* doc/c-riscv.texi: Minor updates.
opcodes/
* riscv-dis.c (print_insn_args): Added `t' after `X' for t-head
operands. Minor updates for indents and comments.
* riscv-opc.c (riscv_opcode): Likewise.
The longest register name is 4 characters (plus a nul one), so using a
4- or 8-byte pointer to get at it is neither space nor time efficient.
Embed the names right into the array. For PIE this also reduces the
number of base relocations in the final image.
To avoid old gcc, when generating 32-bit code, bogusly warning about
bounds being exceeded in the code processing Cs/Cw, Ct/Cx, and CD,
an adjustment to EXTRACT_BITS() is needed: This macro shouldn't supply
a 64-bit value, and it also doesn't need to - all operand fields to
date are far more narrow than 32 bits. This in turn allows dropping a
number of casts elsewhere.
This patch support Zcb extension, contains new compressed instructions,
some instructions depend on other existed extension, like 'zba', 'zbb'
and 'zmmul'. Zcb also imply Zca extension to enable the compressing
features.
Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
Co-Authored by: Simon Cook <simon.cook@embecosm.com>
Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): New extension.
(riscv_multi_subset_supports_ext): Ditto.
gas/ChangeLog:
* config/tc-riscv.c (validate_riscv_insn): New operators.
(riscv_ip): Ditto.
* testsuite/gas/riscv/zcb.d: New test.
* testsuite/gas/riscv/zcb.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_C_LBU): New opcode.
(MASK_C_LBU): New mask.
(MATCH_C_LHU): New opcode.
(MASK_C_LHU): New mask.
(MATCH_C_LH): New opcode.
(MASK_C_LH): New mask.
(MATCH_C_SB): New opcode.
(MASK_C_SB): New mask.
(MATCH_C_SH): New opcode.
(MASK_C_SH): New mask.
(MATCH_C_ZEXT_B): New opcode.
(MASK_C_ZEXT_B): New mask.
(MATCH_C_SEXT_B): New opcode.
(MASK_C_SEXT_B): New mask.
(MATCH_C_ZEXT_H): New opcode.
(MASK_C_ZEXT_H): New mask.
(MATCH_C_SEXT_H): New opcode.
(MASK_C_SEXT_H): New mask.
(MATCH_C_ZEXT_W): New opcode.
(MASK_C_ZEXT_W): New mask.
(MATCH_C_NOT): New opcode.
(MASK_C_NOT): New mask.
(MATCH_C_MUL): New opcode.
(MASK_C_MUL): New mask.
(DECLARE_INSN): New opcode.
* opcode/riscv.h (EXTRACT_ZCB_BYTE_UIMM): New inline func.
(EXTRACT_ZCB_HALFWORD_UIMM): Ditto.
(ENCODE_ZCB_BYTE_UIMM): Ditto.
(ENCODE_ZCB_HALFWORD_UIMM): Ditto.
(VALID_ZCB_BYTE_UIMM): Ditto.
(VALID_ZCB_HALFWORD_UIMM): Ditto.
(enum riscv_insn_class): New extension class.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): New operators.
* riscv-opc.c: New instructions.
This patch adds support for the RISC-V Zfa extension,
which introduces additional floating-point instructions:
* fli (load-immediate) with pre-defined immediates
* fminm/fmaxm (like fmin/fmax but with different NaN behaviour)
* fround/froundmx (round to integer)
* fcvtmod.w.d (Modular Convert-to-Integer)
* fmv* to access high bits of FP registers in case XLEN < FLEN
* fleq/fltq (quiet comparison instructions)
Zfa defines its instructions in combination with the following
extensions:
* single-precision floating-point (F)
* double-precision floating-point (D)
* quad-precision floating-point (Q)
* half-precision floating-point (Zfh)
This patch is based on an earlier version from Tsukasa OI:
https://sourceware.org/pipermail/binutils/2022-September/122939.html
Most significant change to that commit is the switch from the rs1-field
value to the actual floating-point value in the last operand of the fli*
instructions. Everything that strtof() can parse is accepted and
the '%a' printf specifier is used to output hex floating-point literals
in the disassembly.
The Zfa specification is frozen (and has passed public review). It is
available as a chapter in "The RISC-V Instruction Set Manual: Volume 1":
https://github.com/riscv/riscv-isa-manual/releases
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
class support for 'Zfa' extension.
(riscv_multi_subset_supports_ext): Likewise.
(riscv_implicit_subsets): Add 'Zfa' -> 'F' dependency.
gas/ChangeLog:
* config/tc-riscv.c (flt_lookup): New helper to lookup a float value
in an array.
(validate_riscv_insn): Add 'Wfv' as new format string directive.
(riscv_ip): Likewise.
* doc/c-riscv.texi: Add floating-point chapter and describe
limiations of the Zfa FP literal parsing.
* testsuite/gas/riscv/zfa-32.d: New test.
* testsuite/gas/riscv/zfa-32.s: New test.
* testsuite/gas/riscv/zfa-64.d: New test.
* testsuite/gas/riscv/zfa-64.s: New test.
* testsuite/gas/riscv/zfa-fail.d: New test.
* testsuite/gas/riscv/zfa-fail.l: New test.
* testsuite/gas/riscv/zfa-fail.s: New test.
* testsuite/gas/riscv/zfa.d: New test.
* testsuite/gas/riscv/zfa.s: New test.
* testsuite/gas/riscv/zfa.s: New test.
* opcode/riscv-opc.h (MATCH_FLI_H): New.
(MASK_FLI_H): New.
(MATCH_FMINM_H): New.
(MASK_FMINM_H): New.
(MATCH_FMAXM_H): New.
(MASK_FMAXM_H): New.
(MATCH_FROUND_H): New.
(MASK_FROUND_H): New.
(MATCH_FROUNDNX_H): New.
(MASK_FROUNDNX_H): New.
(MATCH_FLTQ_H): New.
(MASK_FLTQ_H): New.
(MATCH_FLEQ_H): New.
(MASK_FLEQ_H): New.
(MATCH_FLI_S): New.
(MASK_FLI_S): New.
(MATCH_FMINM_S): New.
(MASK_FMINM_S): New.
(MATCH_FMAXM_S): New.
(MASK_FMAXM_S): New.
(MATCH_FROUND_S): New.
(MASK_FROUND_S): New.
(MATCH_FROUNDNX_S): New.
(MASK_FROUNDNX_S): New.
(MATCH_FLTQ_S): New.
(MASK_FLTQ_S): New.
(MATCH_FLEQ_S): New.
(MASK_FLEQ_S): New.
(MATCH_FLI_D): New.
(MASK_FLI_D): New.
(MATCH_FMINM_D): New.
(MASK_FMINM_D): New.
(MATCH_FMAXM_D): New.
(MASK_FMAXM_D): New.
(MATCH_FROUND_D): New.
(MASK_FROUND_D): New.
(MATCH_FROUNDNX_D): New.
(MASK_FROUNDNX_D): New.
(MATCH_FLTQ_D): New.
(MASK_FLTQ_D): New.
(MATCH_FLEQ_D): New.
(MASK_FLEQ_D): New.
(MATCH_FLI_Q): New.
(MASK_FLI_Q): New.
(MATCH_FMINM_Q): New.
(MASK_FMINM_Q): New.
(MATCH_FMAXM_Q): New.
(MASK_FMAXM_Q): New.
(MATCH_FROUND_Q): New.
(MASK_FROUND_Q): New.
(MATCH_FROUNDNX_Q): New.
(MASK_FROUNDNX_Q): New.
(MATCH_FLTQ_Q): New.
(MASK_FLTQ_Q): New.
(MATCH_FLEQ_Q): New.
(MASK_FLEQ_Q): New.
(MATCH_FCVTMOD_W_D): New.
(MASK_FCVTMOD_W_D): New.
(MATCH_FMVH_X_D): New.
(MASK_FMVH_X_D): New.
(MATCH_FMVH_X_Q): New.
(MASK_FMVH_X_Q): New.
(MATCH_FMVP_D_X): New.
(MASK_FMVP_D_X): New.
(MATCH_FMVP_Q_X): New.
(MASK_FMVP_Q_X): New.
(DECLARE_INSN): New.
* opcode/riscv.h (enum riscv_insn_class): Add instruction
classes for the Zfa extension.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Add support for
new format string directive 'Wfv'.
* riscv-opc.c: Add Zfa instructions.
Co-Developed-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Co-Developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
* Extract all private_data initializations into riscv_init_disasm_info, which
called from print_insn_riscv rather than riscv_disassemble_insn.
* The disassemble_free_target seems like the right place to release all target
private_data, also including the internal data structures, like riscv_subsets.
Therefore, add a new function, disassemble_free_riscv, to release them for safe.
opcodes/
* disassemble.c (disassemble_free_target): Called disassemble_free_riscv
for riscv to release private_data and internal data structures.
* disassemble.h: Added extern disassemble_free_riscv.
* riscv-dis.c (riscv_init_disasm_info): New function, used to init
riscv_private_data.
(riscv_disassemble_insn): Moved riscv_private_data initializations
into riscv_init_disasm_info.
(print_insn_riscv): Called riscv_init_disasm_info to init
riscv_private_data once time.
(disassemble_free_riscv): New function, used to free the internal data
structures, like riscv_subsets.
This issue was reported from https://github.com/riscv-collab/riscv-gnu-toolchain/issues/1188
Current flow:
1) Scan any mapping symbol less than this instruciton.
2) If not found, did a backward search.
The flow seems not big issue, let run an example here:
$x:
0x0 a <--- Found at step 1
0x4 b <--- Not found in step 1, but found at step 2
0x8 c <--- Not found in step 1, but found at step 2
$d
0x12 .word 1234 <-- Found at step 1
The instruciton didn't have the same address with mapping symbol will
still did backward search again and again.
So the new flow is:
1) Use the last mapping symbol status if the address is still within the range
of the current mapping symbol.
2) Scan any mapping symbol less than this instruciton.
3) If not found, did a backward search.
4) If a proper mapping symbol is found in either step 2 or 3, find its boundary,
and cache that.
Use the same example to run the new flow again:
$x:
0x0 a <--- Found at step 2, the boundary is 0x12
0x4 b <--- Cache hit at step 1, within the boundary.
0x8 c <--- Cache hit at step 1, within the boundary.
$d
0x12 .word 1234 <-- Found at step 2, the boundary is the end of section.
The disassemble time of the test cases has been reduced from ~20 minutes to ~4
seconds.
opcode/ChangeLog
PR 30282
* riscv-dis.c (last_map_symbol_boundary): New.
(last_map_state): New.
(last_map_section): New.
(riscv_search_mapping_symbol): Cache the result of latest
mapping symbol.
This commit intends to move operands that require very special handling or
operand types that are so minor (e.g. only useful on a few instructions)
under "W". I also intend this "W" to be "temporary" operand storage until
we can find good two character (or less) operand type.
In this commit, prefetch offset operand "f" for 'Zicbop' extension is moved
to "Wif" because of its special handling (and allocating single character
"f" for this operand type seemed too much).
Current expected allocation guideline is as follows:
1. 'W'
2. The most closely related single-letter extension in lowercase
(strongly recommended but not mandatory)
3. Identify operand type
The author currently plans to allocate following three-character operand
types (for operands including instructions from unratified extensions).
1. "Wif" ('Zicbop': fetch offset)
2. "Wfv" (unratified 'Zfa': value operand from FLI.[HSDQ] instructions)
3. "Wfm" / "WfM"
'Zfh', 'F', 'D', 'Q': rounding modes "m" with special handling
solely for widening conversion instructions.
gas/ChangeLog:
* config/tc-riscv.c (validate_riscv_insn, riscv_ip): Move from
"f" to "Wif".
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Move from "f" to "Wif".
* riscv-opc.c (riscv_opcodes): Reflect new operand type.
Insn width granularity being 16 bits, producing byte granular output
isn't very useful. With there being a way to specific otherwise
unknown insns to the assembler, use that same representation (to be
precise: its <length>,<encoding> flavor) for disassembly.
The newer update-copyright.py fixes file encoding too, removing cr/lf
on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and
embedded cr in binutils/testsuite/binutils-all/ar.exp string match.
Commit bb996692bd ("RISC-V/gas: allow generating up to 176-bit
instructions with .insn") tried to start supporting long instructions but
it was insufficient.
On the disassembler, correct ".byte" output was limited to the first 64-bits
of an instruction. After that, zeroes are incorrectly printed.
Note that, it only happens on ".byte" output (instruction part) and not on
hexdump (data) part. For example, before this commit, hexdump and ".byte"
produces different values:
Assembly:
.insn 22, 0xfedcba98765432100123456789abcdef55aa33cc607f
objdump output example (before the fix):
10: 607f 33cc 55aa cdef .byte 0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
18: 89ab 4567 0123 3210
20: 7654 ba98 fedc
Note that, after 0xcd (after first 64-bits of the target instruction), all
".byte" values are incorrectly printed as zero while hexdump prints correct
instruction bits.
To resolve this, this commit adds "packet" argument to support dumping
instructions longer than 64-bits (to print correct instruction bits on
".byte"). This commit will be tested on the separate commit.
Assembly:
.insn 22, 0xfedcba98765432100123456789abcdef55aa33cc607f
objdump output example (after the fix):
10: 607f 33cc 55aa cdef .byte 0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0xfe
18: 89ab 4567 0123 3210
20: 7654 ba98 fedc
opcodes/ChangeLog:
* riscv-dis.c (riscv_disassemble_insn): Print unknown instruction
using the new argument packet.
(riscv_disassemble_data): Add unused argument packet.
(print_insn_riscv): Pass packet to the disassemble function.
RISC-V Psabi pr196,
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/196
bfd/
* elfxx-riscv.c (riscv_release_subset_list): Free arch_str if needed.
(riscv_copy_subset_list): Copy arch_str as well.
* elfxx-riscv.h (riscv_subset_list_t): Store arch_str for each subset list.
gas/
* config/tc-riscv.c (riscv_reset_subsets_list_arch_str): Update the
architecture string in the subset_list.
(riscv_set_arch): Call riscv_reset_subsets_list_arch_str after parsing new
architecture string.
(s_riscv_option): Likewise.
(need_arch_map_symbol): New boolean, used to indicate if .option
directives do affect instructions.
(make_mapping_symbol): New boolean parameter reset_seg_arch_str. Need to
generate $x+arch for MAP_INSN, and then store it into tc_segment_info_data
if reset_seg_arch_str is true.
(riscv_mapping_state): Decide if we need to add $x+arch for MAP_INSN. For
now, only add $x+arch if the architecture strings in subset list and segment
are different. Besides, always add $x+arch at the start of section, and do
not add $x+arch for code alignment, since rvc for alignment can be judged
from addend of R_RISCV_ALIGN.
(riscv_remove_mapping_symbol): If current and previous mapping symbol have
same value, then remove the current $x only if the previous is $x+arch;
Otherwise, always remove previous.
(riscv_add_odd_padding_symbol): Updated.
(riscv_check_mapping_symbols): Don't need to add any $x+arch if
need_arch_map_symbol is false, so changed them to $x.
(riscv_frag_align_code): Updated since riscv_mapping_state is changed.
(riscv_init_frag): Likewise.
(s_riscv_insn): Likewise.
(riscv_elf_final_processing): Call riscv_release_subset_list to release
subset_list of riscv_rps_as, rather than only release arch_str in the
riscv_write_out_attrs.
(riscv_write_out_attrs): No need to call riscv_arch_str, just get arch_str
from subset_list of riscv_rps_as.
* config/tc-riscv.h (riscv_segment_info_type): Record current $x+arch mapping
symbol of each segment.
* testsuite/gas/riscv/mapping-0*: Merged and replaced by mapping.s.
* testsuite/gas/riscv/mapping.s: New testcase, to test most of the cases in
one file.
* testsuite/gas/riscv/mapping-symbols.d: Likewise.
* testsuite/gas/riscv/mapping-dis.d: Likewise.
* testsuite/gas/riscv/mapping-non-arch.s: New testcase for the case that
does need any $x+arch.
* testsuite/gas/riscv/mapping-non-arch.d: Likewise.
* testsuite/gas/riscv/option-arch-01a.d: Updated.
opcodes/
* riscv-dis.c (riscv_disassemble_insn): Set riscv_fpr_names back to
riscv_fpr_names_abi or riscv_fpr_names_numeric when zfinx is disabled
for some specfic code region.
(riscv_get_map_state): Recognized mapping symbols $x+arch, and then reset
the architecture string once the ISA is different.
Before changing the core disassembler, we take care of minor code clarity
issues and improve readability.
This commit removes unused variable last_map_state (set by the
print_insn_riscv function but not read anywhere else).
opcodes/ChangeLog:
* riscv-dis.c (last_map_state): Remove.
(print_insn_riscv): Remove setting last_map_state.
Before changing the core disassembler, we take care of minor code clarity
issues and improve readability.
Since xlen variable is not (and should not) used outside riscv-dis.c,
this commit makes this variable static.
opcodes/ChangeLog:
* riscv-dis.c (xlen): Make this variable static.
Before changing the core disassembler, we take care of minor code clarity
issues and improve readability.
This commit replaces uses of int with bool whenever possible.
opcodes/ChangeLog:
* riscv-dis.c (no_aliases) Change type to bool.
(set_default_riscv_dis_options): Use boolean.
(parse_riscv_dis_option_without_args): Likewise.
(riscv_disassemble_insn): Use boolean keywords.
Before changing the core disassembler, we take care of minor code clarity
issues and improve readability.
This commit takes care of improper spacing for code clarity.
opcodes/ChangeLog:
* riscv-dis.c (riscv_disassemble_insn): Tidying with spacing.
Before changing the core disassembler, we take care of minor code clarity
issues and improve readability.
First, we need to clarify the roles of variables and code portions.
opcodes/ChangeLog:
* riscv-dis.c (xlen): Move before default_isa_spec. Add comment.
(default_isa_spec, default_priv_spec): Add comment.
(riscv_gpr_names, riscv_fpr_names): Likewise.
(parse_riscv_dis_option_without_args): Likewise.
(parse_riscv_dis_option, parse_riscv_dis_options): Likewise.
(maybe_print_address): Likewise.
(riscv_disassemble_insn): Fix comment about the Zfinx "extension".
Add comment about the riscv_multi_subset_supports call.
The operand type "Xl(...)" denotes that (...) is a literal. Specifically,
they are intended to be a constant immediate value.
This commit prints "Xl(...)" operand with dis_style_immediate style,
not dis_style_text.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Use dis_style_immediate on
the constant literal of the "Xl..." operand.
This commit fixes two minor typing-related issues for
T-Head immediate operands.
1. A signed type must be specified when printing with %i.
2. unsigned/signed int is not portable enough for max 32-bit immediates.
Instead, we should use unsigned/signed long.
The format string is changed accordingly.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Fix T-Head immediate types on
printing.
On the RISC-V disassembler, some separators have non-text style when
printed with another word with another style.
This commit splits those, making sure that those comma and tabs are printed
with the "text" style.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Split and print the comma as
text. (riscv_disassemble_insn): Split and print tabs as text.
(riscv_disassemble_data): Likewise.
This commit makes types of printf arguments on riscv_disassemble_data
as small as possible (as long as we can preserve the portability) to reduce
the cost of printf (especially on 32-bit host).
opcodes/ChangeLog:
* riscv-dis.c (riscv_disassemble_data): Use smallest possible type
to printing data.
