A number of instructions in the regular MIPS opcode table are assembly
idioms for the MT thread context move MFTR and MTTR instructions, so
mark them as aliases accordingly. Add suitable test cases, which also
cover the PAUSE assembly idiom.
PAUSE is an assembly idiom for 'sll $0,$0,5', so mark it as an alias in
the regular MIPS opcode table, matching the microMIPS opcode table. A
test case will be supplied separately.
A number of coprocessor move encodings have been randomly sprinkled over
the regular MIPS and microMIPS opcode tables rather than where they'd be
expected following the alphabetic order. Fix the ordering, taking into
account precedence where it has to be observed for correct disassembly.
No functional change.
Make AL a shorthand for INSN2_ALIAS with the regular MIPS and microMIPS
opcode tables, just as with the MIPS16 opcode table, and use it
throughout. No functional change.
The semantics of the regular MIPS "+t" operand code is exactly the same
as that of the "E" operand code, so replace the former with the latter
in the single MFTC0 instruction with implicit 'sel' == 0 encoding where
it's used, matching the encoding with explicit 'sel' as well as other
instructions.
We print MFTR and MTTR instructions' thread context register operand in
disassembly using the ABI name the register number would correspond to
should the targeted register be a general-purpose register.
However in most cases it is wrong, because general-purpose registers are
only referred when the 'u' and 'sel' operands are 1 and 0 respectively.
And even in these cases the MFGPR and MTGPR aliases take precedence over
the corresponding generic instruction encodings, so you won't see the
valid case to normally trigger.
Conversely decoding the thread context register operand numerically is
always valid, so switch to using it. Adjust test coverage accordingly.
The "-x" operand type is used for the reverse encoding of the BOVC and
BNVC instructions, where 'rs' and 'rt' have been supplied as the second
and the first operand respectively rather than the order the instruction
expects.
In this case we require the register associated with the "-x" operand to
have a higher number than the register associated with the preceding "t"
operand, which precludes the use of $0. The case where 'rs' and 'rt'
both refer to the same register is handled by the straight encoding of
the BOVC and BNVC instructions, which come in the opcode table ahead of
the corresponding reverse encoding.
Therefore clear the ZERO_OK flag for the "-x" operand. No need for an
extra test case as the encodings involved are already covered by "r6"
and its associated GAS tests.
Adds two new external authors to etc/update-copyright.py to cover
bfd/ax_tls.m4, and adds gprofng to dirs handled automatically, then
updates copyright messages as follows:
1) Update cgen/utils.scm emitted copyrights.
2) Run "etc/update-copyright.py --this-year" with an extra external
author I haven't committed, 'Kalray SA.', to cover gas testsuite
files (which should have their copyright message removed).
3) Build with --enable-maintainer-mode --enable-cgen-maint=yes.
4) Check out */po/*.pot which we don't update frequently.
Allegrex supports some MIPS32 and MIPS32r2 instructions (albeit with
some encoding differences) such as bit manipulation (ins/ext) and MLA
(madd/msub). It also features some new instructions like wsbw and
min/max or device-specific ones such as mfic.
Signed-off-by: David Guillen Fandos <david@davidgf.net>
The Allegrex CPU supports bit rotation instructions as described in the
MIPS32 release 2 CPU (even though it is a MIPS-2 based CPU).
Signed-off-by: David Guillen Fandos <david@davidgf.net>
The Allegrex CPU was created by Sony Interactive Entertainment to power
their portable console, the PlayStation Portable.
The pspdev organization maintains all sorts of tools to create software
for said device including documentation.
Signed-off-by: David Guillen Fandos <david@davidgf.net>
We should try our best to make mips32 using the same
oprand char with micromips. So for mips32, we use:
^ is added for 5bit sa oprand for some new DSPr2 instructions:
APPEND, PREPEND, PRECR_SRA[_R].PH.W
the LSB bit is 11, like RD.
+t is removed for coprocessor 0 destination register.
'E' does the samething.
+t is now used for RX oprand for MFTR/MTTR (MT ASE)
? is added for sel oprand for MFTR/MTTR (MT ASE)
For mips32, the position of sel in MFTR/MTTR is same with mfc0 etc,
while for micromips, they are different.
We also add an extesion format of cftc2/cttc2/mftc2/mfthc2/mttc2/mtthc2:
concatenating rs with rx as the index of control or data.
The newer update-copyright.py fixes file encoding too, removing cr/lf
on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and
embedded cr in binutils/testsuite/binutils-all/ar.exp string match.
Correct issues with INSN2_ALIAS annotation for branch instructions:
- regular MIPS BEQZ/L and BNEZ/L assembly instructions are idioms for
BEQ/L and BNE/L respectively with the `rs' operand equal to $0,
- microMIPS 32-bit BEQZ and BNEZ assembly instructions are idioms for
BEQ and BNE respectively with the `rt' operand equal to $0,
- regular MIPS BAL assembly instruction is an idiom for architecture
levels of up to the MIPSr5 ISA and a machine instruction on its own
from the MIPSr6 ISA up.
Add missing annotation to BEQZ/L and BNEZ/L accordingly then and add a
new entry for BAL for the MIPSr6 ISA, correcting a disassembly bug:
$ mips-linux-gnu-objdump -m mips:isa64r6 -M no-aliases -d bal.o
bal.o: file format elf32-tradlittlemips
Disassembly of section .text:
00000000 <foo>:
0: 04110000 0x4110000
...
$
Add test cases accordingly.
Parts for regular MIPS BEQZ/L and BNEZ/L instructions from Sagar Patel.
2022-03-06 Maciej W. Rozycki <macro@orcam.me.uk>
binutils/
* testsuite/binutils-all/mips/mips1-branch-alias.d: New test.
* testsuite/binutils-all/mips/mips1-branch-noalias.d: New test.
* testsuite/binutils-all/mips/mips2-branch-alias.d: New test.
* testsuite/binutils-all/mips/mips2-branch-noalias.d: New test.
* testsuite/binutils-all/mips/mips32r6-branch-alias.d: New test.
* testsuite/binutils-all/mips/mips32r6-branch-noalias.d: New
test.
* testsuite/binutils-all/mips/micromips-branch-alias.d: New
test.
* testsuite/binutils-all/mips/micromips-branch-noalias.d: New
test.
* testsuite/binutils-all/mips/mips-branch-alias.s: New test
source.
* testsuite/binutils-all/mips/micromips-branch-alias.s: New test
source.
* testsuite/binutils-all/mips/mips.exp: Run the new tests.
2022-03-06 Sagar Patel <sagarmp@cs.unc.edu>
Maciej W. Rozycki <macro@orcam.me.uk>
opcodes/
* mips-opc.c (mips_builtin_opcodes): Fix INSN2_ALIAS annotation
for "bal", "beqz", "beqzl", "bnez" and "bnezl" instructions.
* micromips-opc.c (micromips_opcodes): Likewise for "beqz" and
"bnez" instructions.
The result of running etc/update-copyright.py --this-year, fixing all
the files whose mode is changed by the script, plus a build with
--enable-maintainer-mode --enable-cgen-maint=yes, then checking
out */po/*.pot which we don't update frequently.
The copy of cgen was with commit d1dd5fcc38ead reverted as that commit
breaks building of bfp opcodes files.
Group legacy instructions using the COP0, COP2, COP3 opcodes together
and by their coprocessor number, and move them towards the end of the
opcode table. No functional change.
With the addition of explicit ISA exclusions this is maybe not strictly
necessary anymore as the individual legacy instructions are not supposed
to match ISA levels or CPU implementations that have discarded them or
replaced with a new instruction each, but let's not have them scattered
randomly across blocks of unrelated instruction sets where someone chose
to put them previously. Perhaps they could be put back in alphabetical
order in the main instruction block, but let's leave it for another
occasion.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
COP3 opcode instructions.
Adjust opcode table entries for coprocessor instructions that have been
removed from certain ISA levels or CPU implementations as follows:
- remove CP0 memory access instructions from MIPS II up as the LWC0 and
SWC0 opcodes have been reused for the LL and SC instructions
respectively[1]; strictly speaking LWC0 and SWC0 have never really
been defined in the first place[2], but let's keep them for now in
case an odd implementation did,
- remove CP0 branch instructions from MIPS IV[3] and MIPS32[4] up, as
they have been removed as from those ISAs,
- remove CP0 control register move instructions from MIPS32 up, as they
have been removed as from that ISA[5],
- remove the RFE instruction from MIPS III[6] and MIPS32[7] up, as it
has been removed as from those ISAs in favour to ERET,
- remove CP2 instructions from Vr5400 CPUs as their encodings have been
reused for the multimedia instruction set extensions[8] and no CP2
registers exist[9],
- remove CP3 memory access instructions from MIPS III up as coprocessor
3 has been removed as from that ISA[10][11] and from MIPS32 up as the
LWC3 opcode has been reused for the PREF instruction and consequently
all the four memory access instructions removed from the ISA (though
the COP3 opcode has been retained)[12].
Update the testsuite accordingly.
References:
[1] Charles Price, "MIPS IV Instruction Set", MIPS Technologies, Inc.,
Revision 3.2, September, 1995, Table A-38 "CPU Instruction Encoding
- MIPS II Architecture", p. A-178
[2] same, Section A.2.5.1 "Coprocessor Load and Store", p. A-12
[3] "MIPS R10000 Microprocessor User's Manual", Version 2.0, MIPS
Technologies, Inc., January 29, 1997, Section 14.25 "CP0
Instructions", Subsection "Branch on Coprocessor 0", p. 285
[4] "MIPS32 Architecture For Programmers, Volume II: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number:
MD00086, Revision 1.00, June 9, 2003, Table A-9 "MIPS32 COP0
Encoding of rs Field", p. 242
[5] same
[6] Joe Heinrich, "MIPS R4000 Microprocessor User's Manual", Second
Edition, MIPS Technologies, Inc., April 1, 1994, Figure A-2 "R4000
Opcode Bit Encoding", p. A-182
[8] "Vr5432 64-bit MIPS RISC Microprocessor User's Manual, Volume 1",
NEC Electronics Inc., Document No. U13751EU5V0UM00, May 2000,
Section 1.2.3 "CPU Instruction Set Overview", p. 9
[9] "Vr5432 64-bit MIPS RISC Microprocessor User's Manual, Volume 2",
NEC Electronics Inc., Document No. U13751EU5V0UM00, May 2000,
Section 19.2 "Multimedia Instruction Format", p. 681
[10] Charles Price, "MIPS IV Instruction Set", MIPS Technologies, Inc.,
Revision 3.2, September, 1995, Section A 8.3.4 "Coprocessor 3 -
COP3 and CP3 load/store", p. A-176
[11] same, Table A-39 "CPU Instruction Encoding - MIPS III
Architecture", p. A-179
[12] "MIPS32 Architecture For Programmers, Volume II: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number:
MD00086, Revision 1.00, August 29, 2002, Table A-2 "MIPS32 Encoding
of the Opcode Field", p. 241
opcodes/
* mips-opc.c (mips_builtin_opcodes): Update exclusion list for
"ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
"swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
"bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
"bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
"mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
"cop2", and "cop3" entries.
gas/
* testsuite/gas/mips/mips32@isa-override-1.d: Update for LDC3
instruction removal.
* testsuite/gas/mips/mips32r2@isa-override-1.d: Likewise.
Coprocessor 3 has been removed from the MIPS ISA as from MIPS III[1][2]
with the LDC3 and SDC3 instructions having been replaced with LD and SD
instructions respectively and therefore the doubleword move instructions
from and to that coprocessor have never materialized (for 32-bit ISAs
coprocessor 3 has likewise been removed as from MIPS32r2[3]). Remove
the DMFC3 and DMTC3 instructions from the opcode table then to avoid
confusion.
References:
[1] Charles Price, "MIPS IV Instruction Set", MIPS Technologies, Inc.,
Revision 3.2, September, 1995, Section A 8.3.4 "Coprocessor 3 - COP3
and CP3 load/store", p. A-176
[2] same, Table A-39 "CPU Instruction Encoding - MIPS III Architecture",
p. A-179
[3] "MIPS32 Architecture For Programmers, Volume II: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00086,
Revision 2.00, June 9, 2003, Table A-2 "MIPS32 Encoding of the
Opcode Field", p. 317
opcodes/
* mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
entries and associated comments.
Fix a commit b015e599c7 ("[MIPS] Add new virtualization instructions"),
<https://sourceware.org/ml/binutils/2013-05/msg00118.html>, regression
and bring the disassembly of the RFE instruction back for the relevant
ISA levels.
It is because the "rfe" opcode table entry was incorrectly moved behind
the catch-all generic "c0" entry for CP0 instructions, causing output
like:
00: 42000010 c0 0x10
to be produced rather than:
00: 42000010 rfe
even for ISA levels that do include the RFE instruction.
Move the "rfe" entry ahead of "c0" then, correcting the problem. Add a
suitable test case.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
of "c0".
gas/
* testsuite/gas/mips/rfe.d: New test.
* testsuite/gas/mips/rfe.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
The CP0 control register set has never been defined, however encodings
for the CFC0 and CTC0 instructions remained available for implementers
up until the MIPS32 ISA declared them invalid and causing the Reserved
Instruction exception[1]. Therefore we handle them for both assembly
and disassembly, however in the latter case the names of CP0 registers
from the regular set are incorrectly printed if named registers are
requested. This is because we do not define separate operand classes
for coprocessor regular and control registers respectively, which means
the disassembler has no way to tell the two cases apart. Consequently
nonsensical disassembly is produced like:
cfc0 v0,c0_random
Later the MIPSr5 ISA reused the encodings for XPA ASE MFHC0 and MTHC0
instructions[2] although it failed to document them in the relevant
opcode table until MIPSr6 only.
Correct the issue then by defining a new register class, OP_REG_CONTROL,
and corresponding operand codes, `g' and `y' for the two positions in
the machine instruction a control register operand can take. Adjust the
test cases affected accordingly.
While at it swap the regular MIPS opcode table "cfc0" and "ctc0" entries
with each other so that they come in the alphabetical order.
References:
[1] "MIPS32 Architecture For Programmers, Volume II: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00086,
Revision 1.00, August 29, 2002, Table A-9 "MIPS32 COP0 Encoding of
rs Field", p. 242
[2] "MIPS Architecture For Programmers, Volume II-A: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00086,
Revision 5.04, December 11, 2013, Section 3.2 "Alphabetical List of
Instructions", pp. 195, 216
include/
* opcode/mips.h: Document `g' and `y' operand codes.
(mips_reg_operand_type): Add OP_REG_CONTROL enumeration
constant.
gas/
* tc-mips.c (convert_reg_type) <OP_REG_CONTROL>: New case.
(macro) <M_TRUNCWS, M_TRUNCWD>: Use the `g' rather than `G'
operand code.
opcodes/
* mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
handling code over to...
<OP_REG_CONTROL>: ... this new case.
* mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
(mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
"cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
replacing the `G' operand code with `g'. Update "cftc1" and
"cftc2" entries replacing the `E' operand code with `y'.
* micromips-opc.c (decode_micromips_operand) <'g'>: New case.
(micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
entries replacing the `G' operand code with `g'.
binutils/
* testsuite/binutils-all/mips/mips-xpa-virt-1.d: Correct CFC0
operand disassembly.
* testsuite/binutils-all/mips/mips-xpa-virt-3.d: Likewise.
In the operand handling rewrite made for the MIPS disassembler with
commit ab90248154 ("Add structures to describe MIPS operands"),
<https://sourceware.org/ml/binutils/2013-07/msg00135.html>, the `g'
operand code has become redundant for the regular MIPS instruction set
by duplicating the OP_REG_COPRO semantics of the `G' operand code.
Later commit 351cdf24d2 ("Implement O32 FPXX, FP64 and FP64A ABI
extensions") converted the CTTC1 instruction from the `g' to the `G'
operand code, but still left a few instructions behind.
Convert the three remaining instructions still using the `g' code then,
namely: CTTC2, MTTC2 and MTTHC2, and remove all traces of the operand
code, freeing it up for other use.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
and "mtthc2" to using the `G' rather than `g' operand code for
the coprocessor control register referred.
include/
* opcode/mips.h: Complement change made to opcodes and remove
references to the `g' regular MIPS ISA operand code.
The MIPS64R6 TRM requires that the source register for DAUI
not be r0.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS64
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00087, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 67-68.
gas/
* testsuite/gas/mips/r6-branch-constraints.s: Rename to ...
* testsuite/gas/mips/r6-reg-constraints.s: this and add test
case for DAUI.
* testsuite/gas/mips/r6-branch-constraints.l: Rename to ...
* testsuite/gas/mips/r6-reg-constraints.l: this and add test
for DAUI.
* testsuite/gas/mips/mips.exp: Rename test from
r6-branch-constraints to r6-reg-constraints.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Change source register
constraint for DAUI.
Release 6 of the MIPS architecture does not have an ADDI instruction.
ADD/SUB instructions with immediate operands can be expanded to load
and immediate value and then perform the operation.
gas/
* config/tc-mips.c (macro) <M_ADD_I, M_SUB_I, M_DADD_I, M_DSUB_I>:
Add expansions for MIPS r6.
* testsuite/gas/mips/add.s: Enable tests for R6.
* testsuite/gas/mips/daddi.s: Annotate to test DADD for R6.
* testsuite/gas/mips/mipsr6@add.d: Likewise.
* gas/testsuite/gas/mips/mipsr6@dadd.d: New test.
* gas/testsuite/gas/mips/mips.exp: Run the new test.
opcodes/
* mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
macros for R6.
Add paired load-link and store-conditional instructions to the
EVA ASE for MIPS32R6[1]. These instructions are optional within
the EVA ASE. Their presence is indicated by the XNP bit in the
Config5 register.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 230-231, pp. 357-360.
gas/
* config/tc-mips.c (mips_set_ase): Handle ASE_EVA_R6.
(macro) <M_LLWPE_AB, M_SCWPE_AB>: New cases.
(mips_after_parse_args): Translate EVA to EVA_R6.
* testsuite/gas/mips/ase-errors-1.s: Add new instructions.
* testsuite/gas/mips/eva.s: Likewise.
* testsuite/gas/mips/ase-errors-1.l: Check errors for
new instructions.
* testsuite/gas/mips/mipsr6@eva.d: Check new test cases.
include/
* opcode/mips.h (ASE_EVA_R6): New macro.
(M_LLWPE_AB, M_SCWPE_AB): New enum values.
opcodes/
* mips-dis.c (mips_calculate_combination_ases): Add ISA
argument and set ASE_EVA_R6 appropriately.
(set_default_mips_dis_options): Pass ISA to above.
(parse_mips_dis_option): Likewise.
* mips-opc.c (EVAR6): New macro.
(mips_builtin_opcodes): Add llwpe, scwpe.
Derived from patch authored by Andrew Bennett <andrew.bennett@imgtec.com>
Add several baseline MIPS32R6[1] and MIPS64R6[2] instructions
that were omitted from the initial spec. These instructions
are optional in implementations but not associated with any
ASE or pseudo-ASE. Their presence is indicated by the XNP bit
in the Config5 register.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 228-229, pp. 354-357.
[2] "MIPS Architecture for Programmers Volume II-A: The MIPS64
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00087, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 289-290 and pp. 458-460.
gas/
* config/tc-mips.c (macro) <M_LLWP_AB, M_LLDP_AB, M_SCWP_AB,
M_SCDP_AB>: New cases and expansions for paired instructions.
* testsuite/gas/mips/llpscp-32.s: New test source.
* testsuite/gas/mips/llpscp-64.s: Likewise.
* testsuite/gas/mips/llpscp-32.d: New test.
* testsuite/gas/mips/llpscp-64.d: Likewise.
* testsuite/gas/mips/mips.exp: Run the new tests.
* testsuite/gas/mips/r6.s: Add new instructions to test source.
* testsuite/gas/mips/r6-64.s: Likewise.
* testsuite/gas/mips/r6-64-n32.d: Check new instructions.
* testsuite/gas/mips/r6-64-n64.d: Likewise.
* testsuite/gas/mips/r6-n32.d: Likewise.
* testsuite/gas/mips/r6-n64.d: Likwwise.
* testsuite/gas/mips/r6.d: Likewise.
include/
* opcode/mips.h (M_LLWP_AB, M_LLDP_AB): New enum values.
(M_SCWP_AB, M_SCDP_AB): Likewise.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
In Release 6 of the MIPS architecture [1], instruction RDHWR supports
a 3rd operand to serve as the 3-bit select field for the hardware
register.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 332-334
opcodes/
* mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
gas/
* testsuite/gas/mips/mips.exp: Run hwr-names test.
* testsuite/gas/mips/hwr-names.s: Add test cases for RDHWR with
the SEL field.
* testsuite/gas/mips/mipsr6@hwr-names.d: New file.
The MMI instruction set has been implemented in many Loongson
processors. There is a lot of software optimized for MMI. This patch
splits MMI from loongson2f/3a, and adds GAS and disassembler options for
MMI instructions.
2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
Maciej W. Rozycki <macro@mips.com>
bfd/
* elfxx-mips.c (print_mips_ases): Add MMI extension.
binutils/
* readelf.c (print_mips_ases): Add MMI extension.
gas/
* NEWS: Mention MultiMedia extensions Instructions (MMI)
support.
* config/tc-mips.c (options): Add OPTION_LOONGSON_MMI and
OPTION_NO_LOONGSON_MMI.
(md_longopts): Likewise.
(mips_ases): Define availability for MMI.
(mips_convert_ase_flags): Map ASE_LOONGSON_MMI to
AFL_ASE_LOONGSON_MMI.
(mips_cpu_info_table): Add ASE_LOONGSON_MMI for loongson2f/3a.
(md_show_usage): Add help for -mloongson-mmi and
-mno-loongson-mmi.
* doc/as.texi: Document -mloongson-mmi, -mno-loongson-mmi.
* doc/c-mips.texi: Document -mloongson-mmi, -mno-loongson-mmi,
.set loongson-mmi and .set noloongson-mmi.
* testsuite/gas/mips/loongson-2f.d: Move mmi test to ...
* testsuite/gas/mips/loongson-2f-mmi.d: Here. Add ISA/ASE
flag verification.
* testsuite/gas/mips/loongson-2f.s: Move mmi test to ...
* testsuite/gas/mips/loongson-2f-mmi.s: Here.
* testsuite/gas/mips/loongson-3a.d: Move mmi test to ...
* testsuite/gas/mips/loongson-3a-mmi.d: Here. Add ISA/ASE
flag verification.
* testsuite/gas/mips/loongson-3a.s: Move mmi test to ...
* testsuite/gas/mips/loongson-3a-mmi.s: Here.
* testsuite/gas/mips/mips.exp: Run loongson-2f-mmi and
loongson-3a-mmi tests.
include/
* elf/mips.h (AFL_ASE_MMI): New macro.
(AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_MMI.
* opcode/mips.h (ASE_LOONGSON_MMI): New macro.
opcodes/
* mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
loongson3a descriptors.
(parse_mips_ase_option): Handle -M loongson-mmi option.
(print_mips_disassembler_options): Document -M loongson-mmi.
* mips-opc.c (LMMI): New macro.
(mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
instructions.
Add support for the Global INValidate Application Specific Extension
for Release 6 of the MIPS Architecture.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 187-191
bfd/
* elfxx-mips.c (print_mips_ases): Add GINV extension.
binutils/
* readelf.c (print_mips_ases): Add GINV extension.
gas/
* NEWS: Mention MIPS Global INValidate ASE support.
* config/tc-mips.c (options): Add OPTION_GINV and OPTION_NO_GINV.
(md_longopts): Likewise.
(mips_ases): Define availability for GINV.
(mips_convert_ase_flags): Map ASE_GINV to AFL_ASE_GINV.
(md_show_usage): Add help for -mginv and -mno-ginv.
* doc/as.texinfo: Document -mginv, -mno-ginv.
* doc/c-mips.texi: Document -mginv, -mno-ginv, .set ginv and
.set noginv.
* testsuite/gas/mips/ase-errors-1.s: Add error checks for GINV
ASE.
* testsuite/gas/mips/ase-errors-2.s: Likewise.
* testsuite/gas/mips/ase-errors-1.l: Likewise.
* testsuite/gas/mips/ase-errors-2.l: Likewise.
* testsuite/gas/mips/ginv.d: New test.
* testsuite/gas/mips/ginv-err.d: New test.
* testsuite/gas/mips/ginv-err.l: New test stderr output.
* testsuite/gas/mips/ginv.s: New test source.
* testsuite/gas/mips/ginv-err.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
include/
* elf/mips.h (AFL_ASE_GINV, AFL_ASE_RESERVED1): New macros.
(AFL_ASE_MASK): Update to include AFL_ASE_GINV.
* opcode/mips.h: Document "+\" operand format.
(ASE_GINV): New macro.
opcodes/
* mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
mips64r6 descriptors.
(parse_mips_ase_option): Handle -Mginv option.
(print_mips_disassembler_options): Document -Mginv.
* mips-opc.c (decode_mips_operand) <+\>: New operand format.
(GINV): New macro.
(mips_opcodes): Define ginvi and ginvt.
Add support for the CRC Application Specific Extension for Release 6 of
the MIPS Architecture.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 143-148
[2] "MIPS Architecture for Programmers Volume II-A: The MIPS64
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00087, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 165-170
ChangeLog:
bfd/
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
* elfxx-mips.c (print_mips_ases): Add CRC.
binutils/
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
* readelf.c (print_mips_ases): Add CRC.
gas/
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
Maciej W. Rozycki <macro@mips.com>
* config/tc-mips.c (options): Add OPTION_CRC and OPTION_NO_CRC.
(md_longopts): Likewise.
(md_show_usage): Add help for -mcrc and -mno-crc.
(mips_ases): Define availability for CRC and CRC64.
(mips_convert_ase_flags): Map ASE_CRC to AFL_ASE_CRC.
* doc/as.texinfo: Document -mcrc, -mno-crc.
* doc/c-mips.texi: Document -mcrc, -mno-crc, .set crc and
.set no-crc.
* testsuite/gas/mips/ase-errors-1.l: Add error checks for CRC
ASE.
* testsuite/gas/mips/ase-errors-2.l: Likewise.
* testsuite/gas/mips/ase-errors-1.s: Likewise.
* testsuite/gas/mips/ase-errors-2.s: Likewise.
* testsuite/gas/mips/crc.d: New test.
* testsuite/gas/mips/crc64.d: New test.
* testsuite/gas/mips/crc-err.d: New test.
* testsuite/gas/mips/crc64-err.d: New test.
* testsuite/gas/mips/crc-err.l: New test stderr output.
* testsuite/gas/mips/crc64-err.l: New test stderr output.
* testsuite/gas/mips/crc.s: New test source.
* testsuite/gas/mips/crc64.s: New test source.
* testsuite/gas/mips/crc-err.s: New test source.
* testsuite/gas/mips/crc64-err.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
include/
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
* elf/mips.h (AFL_ASE_CRC): New macro.
(AFL_ASE_MASK): Update to include AFL_ASE_CRC.
* opcode/mips.h (ASE_CRC): New macro.
* opcode/mips.h (ASE_CRC64): Likewise.
opcodes/
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
* mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
* mips-opc.c (CRC, CRC64): New macros.
(mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
crc32cd for CRC64.
The instruction encoding for the MIPS r6 sigrie instruction seems to be
incorrect. It's currently 0x4170xxxx (which overlaps with ei, di, evp,
and dvp), but should be 0x0417xxxx. See ISA reference[1][2].
References:
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies, Inc., Document
Number: MD00086, Revision 6.06, December 15, 2016, Table A.4 "MIPS32
REGIMM Encoding of rt Field", p. 452
[2] "MIPS Architecture For Programmers Volume II-A: The MIPS64
Instruction Set Reference Manual", Imagination Technologies, Inc.,
Document Number: MD00087, Revision 6.06, December 15, 2016, Table
A.4 "MIPS64 REGIMM Encoding of rt Field", p. 581
opcodes/
* mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
gas/
* testsuite/gas/mips/r6.d: Update for "sigrie" encoding fix.
* testsuite/gas/mips/r6-n32.d: Likewise.
* testsuite/gas/mips/r6-n64.d: Likewise.
Correct an issue introduced with commit 7361da2c95 ("Add support for
MIPS R6.") and move the LSA and DLSA instructions back to the MSA ASE
instruction block in the regular MIPS opcode table. Adjust formatting
around the "MIPS r6" heading.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
entries to the MSA ASE instruction block.
Correct a commit 7d64c587c1 ("Add support for the MIPS eXtended
Physical Address (XPA) ASE.") bug, causing XPA base and Virtualization
ASE instructions to be wrongly always enabled with the selection of the
MIPS32r2 or higher ISA.
For example this source assembles successfully as shown below:
$ cat xpa.s
mfhc0 $2, $1
$ as -32 -mips32 -o xpa.o xpa.s
xpa.s: Assembler messages:
xpa.s:1: Error: opcode not supported on this processor: mips32 (mips32) `mfhc0 $2,$1'
$ as -32 -mips32r2 -o xpa.o xpa.s
$ objdump -d xpa.o
xpa.o: file format elf32-tradbigmips
Disassembly of section .text:
00000000 <.text>:
0: 40420800 mfhc0 v0,c0_random
...
$
To address this issue remove the I33 (INSN_ISA32R2) marking from all XPA
instructions in the opcode table. Additionally, for XPA Virtualization
ASE instructions implement an XPAVZ (ASE_XPA_VIRT) combination ASE flag
and use it in place of IVIRT|XPA (ASE_VIRT|ASE_XPA).
Now the same source is correctly rejected unless the `-mxpa' option is
also used:
$ as -32 -mips32r2 -o xpa.o xpa.s
xpa.s: Assembler messages:
xpa.s:1: Error: opcode not supported on this processor: mips32r2 (mips32r2) `mfhc0 $2,$1'
$ as -32 -mips32r2 -mxpa -o xpa.o xpa.s
$
Add test cases for XPA base and XPA Virtualization ASE instructions.
Parts of this change by Andrew Bennett.
include/
* opcode/mips.h (ASE_XPA_VIRT): New macro.
opcodes/
* mips-dis.c (mips_calculate_combination_ases): Handle the
ASE_XPA_VIRT flag.
(parse_mips_ase_option): New function.
(parse_mips_dis_option): Factor out ASE option handling to the
new function. Call `mips_calculate_combination_ases'.
* mips-opc.c (XPAVZ): New macro.
(mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
"mfhgc0", "mthc0" and "mthgc0".
gas/
* config/tc-mips.c (mips_set_ase): Handle the ASE_XPA_VIRT flag.
* testsuite/gas/mips/xpa.d: Remove `xpa' from `-M' in `objdump'
flags. Add `-mvirt' to `as' flags.
* testsuite/gas/mips/xpa-err.d: New test.
* testsuite/gas/mips/xpa-virt-err.d: New test.
* testsuite/gas/mips/xpa-err.l: New stderr output.
* testsuite/gas/mips/xpa-virt-err.l: New stderr output.
* testsuite/gas/mips/xpa-err.s: New test source.
* testsuite/gas/mips/xpa-virt-err.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
binutils/
* testsuite/binutils-all/mips/mips-xpa-virt-1.d: New test.
* testsuite/binutils-all/mips/mips-xpa-virt-2.d: New test.
* testsuite/binutils-all/mips/mips-xpa-virt-3.d: New test.
* testsuite/binutils-all/mips/mips-xpa-virt-4.d: New test.
* testsuite/binutils-all/mips/mips-xpa-virt.s: New test source.
* testsuite/binutils-all/mips/mips.exp: Run the new tests.
