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* arc-opc.c (insertion fns): Pass pointer to value's table entry.
All uses changed. (extraction fns): Insn argument now array of two words. Return pointer to value's table entry. All uses changed. (arc_opcode_lookup_suffix): Exported for arc-dis.c. (insert_multshift, extract_multshift): New fns. (arc_operands): Add support for cache bypass suffix. Add support for predefined aux regs. Modifier bits moved to flags field. (arc_opcodes): Likewise. Add mul/mulu/shift insns. Syntax of zero/sign extension insns changed. New insn rlc. Update to syntax in programmer's manual. (arc_reg_names): Fix typo in lp_count. Add predefined aux regs. (arc_suffixes): New synonyms lo,hs for cs,cc. New suffix for cache bypass. (arc_opcode_init_tables): New argument to indicate cpu type. (insert_reg): Handle predefined aux regs. (extract_reg): Likewise. (lookup_register): New fn. * arc-dis.c (arc_condition_codes): Deleted. (print_insn_arc): Handle insns with 32 bit immediate constants better. Clean up modifier handling. Handle predefined aux regs.
This commit is contained in:
David Edelsohn
198
opcodes/arc-dis.c
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198
opcodes/arc-dis.c
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/* Instruction printing code for the ARC.
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Copyright (C) 1994 Free Software Foundation, Inc.
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Contributed by Doug Evans (dje@cygnus.com).
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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#include "dis-asm.h"
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#include "opcode/arc.h"
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/* Print one instruction from PC on INFO->STREAM.
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Return the size of the instruction (4 or 8 for the ARC). */
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int
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print_insn_arc (pc, info)
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bfd_vma pc;
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struct disassemble_info *info;
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{
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const struct arc_opcode *opcode,*opcode_end;
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bfd_byte buffer[4];
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void *stream = info->stream;
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fprintf_ftype func = info->fprintf_func;
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int status;
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/* First element is insn, second element is limm (if present). */
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arc_insn insn[2];
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int got_limm_p = 0;
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static int initialized = 0;
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if (!initialized)
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{
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/* ??? Hmmm... what do we pass here? */
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arc_opcode_init_tables (ARC_HAVE_MULT_SHIFT);
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initialized = 1;
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}
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status = (*info->read_memory_func) (pc, buffer, 4, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, pc, info);
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return -1;
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}
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insn[0] = bfd_getb32 (buffer);
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func (stream, "%08lx\t", insn[0]);
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opcode_end = arc_opcodes + arc_opcodes_count;
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for (opcode = arc_opcodes; opcode < opcode_end; opcode++)
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{
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char *syn;
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int mods,invalid;
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long value;
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const struct arc_operand *operand;
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const struct arc_operand_value *opval;
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if ((insn[0] & opcode->mask) != opcode->value)
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continue;
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/* Make two passes over the operands. First see if any of them
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have extraction functions, and, if they do, make sure the
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instruction is valid. */
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arc_opcode_init_extract ();
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invalid = 0;
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/* ??? Granted, this is slower than the `ppc' way. Maybe when this is
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done it'll be clear what the right way to do this is. */
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/* Instructions like "add.f r0,r1,1" are tricky because the ".f" gets
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printed first, but we don't know how to print it until we've processed
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the regs. Since we're scanning all the args before printing the insn
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anyways, it's quite easy. */
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for (syn = opcode->syntax; *syn; ++syn)
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{
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if (*syn != '%' || *++syn == '%')
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continue;
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mods = 0;
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while (ARC_MOD_P (arc_operands[arc_operand_map[*syn]].flags))
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{
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mods |= arc_operands[arc_operand_map[*syn]].flags & ARC_MOD_BITS;
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++syn;
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}
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operand = arc_operands + arc_operand_map[*syn];
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if (operand->extract)
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(*operand->extract) (insn, operand, mods,
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(const struct arc_operand_value **) NULL,
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&invalid);
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}
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if (invalid)
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continue;
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/* The instruction is valid. */
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/* If we have an insn with a limm, fetch it now. Scanning the insns
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twice lets us do this. */
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if (arc_opcode_limm_p (NULL))
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{
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status = (*info->read_memory_func) (pc + 4, buffer, 4, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, pc, info);
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return -1;
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}
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insn[1] = bfd_getb32 (buffer);
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got_limm_p = 1;
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}
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for (syn = opcode->syntax; *syn; ++syn)
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{
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if (*syn != '%' || *++syn == '%')
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{
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func (stream, "%c", *syn);
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continue;
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}
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/* We have an operand. Fetch any special modifiers. */
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mods = 0;
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while (ARC_MOD_P (arc_operands[arc_operand_map[*syn]].flags))
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{
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mods |= arc_operands[arc_operand_map[*syn]].flags & ARC_MOD_BITS;
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++syn;
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}
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operand = arc_operands + arc_operand_map[*syn];
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/* Extract the value from the instruction. */
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opval = NULL;
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if (operand->extract)
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{
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value = (*operand->extract) (insn, operand, mods,
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&opval, (int *) NULL);
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}
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else
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{
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value = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
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if ((operand->flags & ARC_OPERAND_SIGNED)
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&& (value & (1 << (operand->bits - 1))))
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value -= 1 << operand->bits;
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/* If this is a suffix operand, set `opval'. */
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if (operand->flags & ARC_OPERAND_SUFFIX)
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opval = arc_opcode_lookup_suffix (operand, value);
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}
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/* Print the operand as directed by the flags. */
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if (operand->flags & ARC_OPERAND_FAKE)
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; /* nothing to do (??? at least not yet) */
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else if (operand->flags & ARC_OPERAND_SUFFIX)
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{
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/* Default suffixes aren't printed. Fortunately, they all have
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zero values. Also, zero values for boolean suffixes are
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represented by the absence of text. */
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if (value != 0)
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{
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/* ??? OPVAL should have a value. If it doesn't just cope
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as we want disassembly to be reasonably robust.
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Also remember that several condition code values (16-31)
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aren't defined yet. For these cases just print the
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number suitably decorated. */
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if (opval)
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func (stream, "%s%s",
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mods & ARC_MOD_DOT ? "." : "",
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opval->name);
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else
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func (stream, "%s%c%d",
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mods & ARC_MOD_DOT ? "." : "",
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operand->fmt, value);
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}
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}
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else if (operand->flags & ARC_OPERAND_RELATIVE)
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(*info->print_address_func) (pc + value, info);
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/* ??? Not all cases of this are currently caught. */
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else if (operand->flags & ARC_OPERAND_ABSOLUTE)
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(*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
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else if (opval)
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/* Note that this case catches both normal and auxiliary regs. */
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func (stream, "%s", opval->name);
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else
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func (stream, "%ld", value);
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}
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/* We have found and printed an instruction; return. */
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return got_limm_p ? 8 : 4;
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}
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func (stream, "*unknown*");
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return 4;
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}
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