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[Morello] altbase: LDUR/STUR
gas/ChangeLog: 2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com> * config/tc-aarch64.c (parse_operands): Add Rsz2, Fsz, St and CAPADDR_SIMM9. (try_to_encode_as_unscaled_ldst): Add unscaled altbase loads. * testsuite/gas/aarch64/morello_ldst-c64.d: Add tests. * testsuite/gas/aarch64/morello_ldst.d: Likewise. * testsuite/gas/aarch64/morello_ldst.s: Likewise. include/ChangeLog: 2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com> * opcode/aarch64.h (aarch64_opnd): Add sz2, Fsz, St and CAPADDR_SIMM9. (aarch64_op): Add OP_STR_POS_3, OP_LDR_POS_3, OP_STR_POS_4, OP_LDR_POS_4, OP_LDUR_3, OP_STUR_3, OP_LDUR_4, OP_STUR_4. opcodes/ChangeLog: 2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com> * aarch64-asm.c (aarch64_ins_fregsz): New function. (aarch64_ins_addr_simm): Add ldst_altbase to assert. * aarch64-asm.h (ins_fregsz): New function declaration. * aarch64-dis.c (aarch64_ext_fregsz): New function. (aarch64_ext_addr_simm): Disable writeback for ldst_altbase. * aarch64-dis.h (ext_fregsz): New function declaration. * aarch64-opc.c (fields): Add altbase_sf2 and altbase_sf3. (operand_general_constraint_met_p): Add CAPADDR_SIMM9. (aarch64_print_operand): Add CAPADDR_SIMM9, Rsz2, Fsz, St. * aarch64-opc.h (aarch64_field_kind): Add FLD_altbase_sf2, FLD_altbase_sf3. * aarch64-tbl.h (aarch64_opcode_table): New instructions. (AARCH64_OPERANDS): New operands. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate.
This commit is contained in:
Siddhesh Poyarekar
committed by
Luis Machado
Luis Machado
parent
08da6e9376
commit
ec87fc0fff
@@ -1,3 +1,12 @@
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2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
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* config/tc-aarch64.c (parse_operands): Add Rsz2, Fsz, St and
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CAPADDR_SIMM9.
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(try_to_encode_as_unscaled_ldst): Add unscaled altbase loads.
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* testsuite/gas/aarch64/morello_ldst-c64.d: Add tests.
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* testsuite/gas/aarch64/morello_ldst.d: Likewise.
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* testsuite/gas/aarch64/morello_ldst.s: Likewise.
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2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
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* config/tc-aarch64.c (parse_operands): Add Rsz,
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@@ -5766,6 +5766,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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break;
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case AARCH64_OPND_Rsz:
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case AARCH64_OPND_Rsz2:
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case AARCH64_OPND_Rd:
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case AARCH64_OPND_Rn:
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case AARCH64_OPND_Rm:
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@@ -5807,6 +5808,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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}
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break;
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case AARCH64_OPND_Fsz:
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case AARCH64_OPND_Fd:
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case AARCH64_OPND_Fn:
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case AARCH64_OPND_Fm:
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@@ -5816,6 +5818,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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case AARCH64_OPND_Sd:
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case AARCH64_OPND_Sn:
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case AARCH64_OPND_Sm:
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case AARCH64_OPND_St:
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case AARCH64_OPND_SVE_VZn:
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case AARCH64_OPND_SVE_Vd:
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case AARCH64_OPND_SVE_Vm:
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@@ -6673,12 +6676,17 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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/* skip_p */ 0);
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break;
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case AARCH64_OPND_CAPADDR_SIMM9:
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po_misc_or_fail (parse_cap_address (&str, info, opcode->iclass));
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goto addr_simm;
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case AARCH64_OPND_A64C_ADDR_SIMM9:
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case AARCH64_OPND_ADDR_SIMM9:
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case AARCH64_OPND_ADDR_SIMM9_2:
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case AARCH64_OPND_ADDR_SIMM11:
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case AARCH64_OPND_ADDR_SIMM13:
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po_misc_or_fail (parse_address (&str, info));
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addr_simm:
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if (info->addr.pcrel || info->addr.offset.is_reg
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|| (!info->addr.preind && !info->addr.postind)
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|| (operands[i] == AARCH64_OPND_ADDR_SIMM9_2
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@@ -7976,8 +7984,12 @@ try_to_encode_as_unscaled_ldst (aarch64_inst *instr)
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case OP_LDRSH_POS: new_op = OP_LDURSH; break;
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case OP_LDR_POS: new_op = OP_LDUR; break;
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case OP_LDR_POS_2: new_op = OP_LDUR_2; break;
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case OP_LDR_POS_3: new_op = OP_LDUR_3; break;
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case OP_LDR_POS_4: new_op = OP_LDUR_4; break;
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case OP_STR_POS: new_op = OP_STUR; break;
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case OP_STR_POS_2: new_op = OP_STUR_2; break;
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case OP_STR_POS_3: new_op = OP_STUR_3; break;
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case OP_STR_POS_4: new_op = OP_STUR_4; break;
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case OP_LDRF_POS: new_op = OP_LDURV; break;
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case OP_STRF_POS: new_op = OP_STURV; break;
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case OP_LDRSW_POS: new_op = OP_LDURSW; break;
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@@ -262,3 +262,99 @@ Disassembly of section \.text:
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.*: 825ffbe4 str w4, \[sp, #2044\]
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.*: 82408be4 str w4, \[sp, #32\]
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.*: 82400be4 str w4, \[sp\]
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.*: e2cffd84 ldur c4, \[x12, #255\]
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.*: e2c20d84 ldur c4, \[x12, #32\]
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.*: e2d00d84 ldur c4, \[x12, #-256\]
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.*: e2cff584 ldur x4, \[x12, #255\]
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.*: e2c20584 ldur x4, \[x12, #32\]
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.*: e2d00584 ldur x4, \[x12, #-256\]
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.*: e28ff584 ldur w4, \[x12, #255\]
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.*: e2820584 ldur w4, \[x12, #32\]
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.*: e2900584 ldur w4, \[x12, #-256\]
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.*: e22ff584 ldur b4, \[x12, #255\]
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.*: e2220584 ldur b4, \[x12, #32\]
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.*: e2300584 ldur b4, \[x12, #-256\]
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.*: e26ff584 ldur h4, \[x12, #255\]
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.*: e2620584 ldur h4, \[x12, #32\]
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.*: e2700584 ldur h4, \[x12, #-256\]
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.*: e2aff584 ldur s4, \[x12, #255\]
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.*: e2a20584 ldur s4, \[x12, #32\]
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.*: e2b00584 ldur s4, \[x12, #-256\]
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.*: e2eff584 ldur d4, \[x12, #255\]
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.*: e2e20584 ldur d4, \[x12, #32\]
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.*: e2f00584 ldur d4, \[x12, #-256\]
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.*: e22ffd84 ldur q4, \[x12, #255\]
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.*: e2220d84 ldur q4, \[x12, #32\]
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.*: e2300d84 ldur q4, \[x12, #-256\]
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.*: e28ffd84 stur c4, \[x12, #255\]
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.*: e2820d84 stur c4, \[x12, #32\]
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.*: e2900d84 stur c4, \[x12, #-256\]
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.*: e2cff184 stur x4, \[x12, #255\]
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.*: e2c20184 stur x4, \[x12, #32\]
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.*: e2d00184 stur x4, \[x12, #-256\]
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.*: e28ff184 stur w4, \[x12, #255\]
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.*: e2820184 stur w4, \[x12, #32\]
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.*: e2900184 stur w4, \[x12, #-256\]
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.*: e22ff184 stur b4, \[x12, #255\]
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.*: e2220184 stur b4, \[x12, #32\]
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.*: e2300184 stur b4, \[x12, #-256\]
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.*: e26ff184 stur h4, \[x12, #255\]
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.*: e2620184 stur h4, \[x12, #32\]
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.*: e2700184 stur h4, \[x12, #-256\]
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.*: e2aff184 stur s4, \[x12, #255\]
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.*: e2a20184 stur s4, \[x12, #32\]
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.*: e2b00184 stur s4, \[x12, #-256\]
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.*: e2eff184 stur d4, \[x12, #255\]
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.*: e2e20184 stur d4, \[x12, #32\]
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.*: e2f00184 stur d4, \[x12, #-256\]
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.*: e22ff984 stur q4, \[x12, #255\]
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.*: e2220984 stur q4, \[x12, #32\]
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.*: e2300984 stur q4, \[x12, #-256\]
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.*: e2cfffe4 ldur c4, \[sp, #255\]
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.*: e2c20fe4 ldur c4, \[sp, #32\]
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.*: e2d00fe4 ldur c4, \[sp, #-256\]
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.*: e2cff7e4 ldur x4, \[sp, #255\]
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.*: e2c207e4 ldur x4, \[sp, #32\]
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.*: e2d007e4 ldur x4, \[sp, #-256\]
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.*: e28ff7e4 ldur w4, \[sp, #255\]
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.*: e28207e4 ldur w4, \[sp, #32\]
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.*: e29007e4 ldur w4, \[sp, #-256\]
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.*: e22ff7e4 ldur b4, \[sp, #255\]
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.*: e22207e4 ldur b4, \[sp, #32\]
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.*: e23007e4 ldur b4, \[sp, #-256\]
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.*: e26ff7e4 ldur h4, \[sp, #255\]
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.*: e26207e4 ldur h4, \[sp, #32\]
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.*: e27007e4 ldur h4, \[sp, #-256\]
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.*: e2aff7e4 ldur s4, \[sp, #255\]
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.*: e2a207e4 ldur s4, \[sp, #32\]
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.*: e2b007e4 ldur s4, \[sp, #-256\]
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.*: e2eff7e4 ldur d4, \[sp, #255\]
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.*: e2e207e4 ldur d4, \[sp, #32\]
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.*: e2f007e4 ldur d4, \[sp, #-256\]
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.*: e22fffe4 ldur q4, \[sp, #255\]
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.*: e2220fe4 ldur q4, \[sp, #32\]
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.*: e2300fe4 ldur q4, \[sp, #-256\]
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.*: e28fffe4 stur c4, \[sp, #255\]
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.*: e2820fe4 stur c4, \[sp, #32\]
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.*: e2900fe4 stur c4, \[sp, #-256\]
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.*: e2cff3e4 stur x4, \[sp, #255\]
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.*: e2c203e4 stur x4, \[sp, #32\]
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.*: e2d003e4 stur x4, \[sp, #-256\]
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.*: e28ff3e4 stur w4, \[sp, #255\]
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.*: e28203e4 stur w4, \[sp, #32\]
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.*: e29003e4 stur w4, \[sp, #-256\]
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.*: e22ff3e4 stur b4, \[sp, #255\]
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.*: e22203e4 stur b4, \[sp, #32\]
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.*: e23003e4 stur b4, \[sp, #-256\]
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.*: e26ff3e4 stur h4, \[sp, #255\]
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.*: e26203e4 stur h4, \[sp, #32\]
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.*: e27003e4 stur h4, \[sp, #-256\]
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.*: e2aff3e4 stur s4, \[sp, #255\]
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.*: e2a203e4 stur s4, \[sp, #32\]
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.*: e2b003e4 stur s4, \[sp, #-256\]
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.*: e2eff3e4 stur d4, \[sp, #255\]
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.*: e2e203e4 stur d4, \[sp, #32\]
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.*: e2f003e4 stur d4, \[sp, #-256\]
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.*: e22ffbe4 stur q4, \[sp, #255\]
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.*: e2220be4 stur q4, \[sp, #32\]
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.*: e2300be4 stur q4, \[sp, #-256\]
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@@ -261,3 +261,99 @@ Disassembly of section \.text:
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.*: 825ffbe4 str w4, \[csp, #2044\]
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.*: 82408be4 str w4, \[csp, #32\]
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.*: 82400be4 str w4, \[csp\]
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.*: e2cffea4 ldur c4, \[c21, #255\]
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.*: e2c20ea4 ldur c4, \[c21, #32\]
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.*: e2d00ea4 ldur c4, \[c21, #-256\]
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.*: e2cff6a4 ldur x4, \[c21, #255\]
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.*: e2c206a4 ldur x4, \[c21, #32\]
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.*: e2d006a4 ldur x4, \[c21, #-256\]
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.*: e28ff6a4 ldur w4, \[c21, #255\]
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.*: e28206a4 ldur w4, \[c21, #32\]
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.*: e29006a4 ldur w4, \[c21, #-256\]
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.*: e22ff6a4 ldur b4, \[c21, #255\]
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.*: e22206a4 ldur b4, \[c21, #32\]
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.*: e23006a4 ldur b4, \[c21, #-256\]
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.*: e26ff6a4 ldur h4, \[c21, #255\]
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.*: e26206a4 ldur h4, \[c21, #32\]
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.*: e27006a4 ldur h4, \[c21, #-256\]
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.*: e2aff6a4 ldur s4, \[c21, #255\]
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.*: e2a206a4 ldur s4, \[c21, #32\]
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.*: e2b006a4 ldur s4, \[c21, #-256\]
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.*: e2eff6a4 ldur d4, \[c21, #255\]
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.*: e2e206a4 ldur d4, \[c21, #32\]
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.*: e2f006a4 ldur d4, \[c21, #-256\]
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.*: e22ffea4 ldur q4, \[c21, #255\]
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.*: e2220ea4 ldur q4, \[c21, #32\]
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.*: e2300ea4 ldur q4, \[c21, #-256\]
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.*: e28ffea4 stur c4, \[c21, #255\]
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.*: e2820ea4 stur c4, \[c21, #32\]
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.*: e2900ea4 stur c4, \[c21, #-256\]
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.*: e2cff2a4 stur x4, \[c21, #255\]
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.*: e2c202a4 stur x4, \[c21, #32\]
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.*: e2d002a4 stur x4, \[c21, #-256\]
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.*: e28ff2a4 stur w4, \[c21, #255\]
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.*: e28202a4 stur w4, \[c21, #32\]
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.*: e29002a4 stur w4, \[c21, #-256\]
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.*: e22ff2a4 stur b4, \[c21, #255\]
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.*: e22202a4 stur b4, \[c21, #32\]
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.*: e23002a4 stur b4, \[c21, #-256\]
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.*: e26ff2a4 stur h4, \[c21, #255\]
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.*: e26202a4 stur h4, \[c21, #32\]
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.*: e27002a4 stur h4, \[c21, #-256\]
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.*: e2aff2a4 stur s4, \[c21, #255\]
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.*: e2a202a4 stur s4, \[c21, #32\]
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.*: e2b002a4 stur s4, \[c21, #-256\]
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.*: e2eff2a4 stur d4, \[c21, #255\]
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.*: e2e202a4 stur d4, \[c21, #32\]
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.*: e2f002a4 stur d4, \[c21, #-256\]
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.*: e22ffaa4 stur q4, \[c21, #255\]
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.*: e2220aa4 stur q4, \[c21, #32\]
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.*: e2300aa4 stur q4, \[c21, #-256\]
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.*: e2cfffe4 ldur c4, \[csp, #255\]
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.*: e2c20fe4 ldur c4, \[csp, #32\]
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.*: e2d00fe4 ldur c4, \[csp, #-256\]
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.*: e2cff7e4 ldur x4, \[csp, #255\]
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.*: e2c207e4 ldur x4, \[csp, #32\]
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.*: e2d007e4 ldur x4, \[csp, #-256\]
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.*: e28ff7e4 ldur w4, \[csp, #255\]
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.*: e28207e4 ldur w4, \[csp, #32\]
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.*: e29007e4 ldur w4, \[csp, #-256\]
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.*: e22ff7e4 ldur b4, \[csp, #255\]
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.*: e22207e4 ldur b4, \[csp, #32\]
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.*: e23007e4 ldur b4, \[csp, #-256\]
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.*: e26ff7e4 ldur h4, \[csp, #255\]
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.*: e26207e4 ldur h4, \[csp, #32\]
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.*: e27007e4 ldur h4, \[csp, #-256\]
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.*: e2aff7e4 ldur s4, \[csp, #255\]
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.*: e2a207e4 ldur s4, \[csp, #32\]
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.*: e2b007e4 ldur s4, \[csp, #-256\]
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.*: e2eff7e4 ldur d4, \[csp, #255\]
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.*: e2e207e4 ldur d4, \[csp, #32\]
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.*: e2f007e4 ldur d4, \[csp, #-256\]
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.*: e22fffe4 ldur q4, \[csp, #255\]
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.*: e2220fe4 ldur q4, \[csp, #32\]
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.*: e2300fe4 ldur q4, \[csp, #-256\]
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.*: e28fffe4 stur c4, \[csp, #255\]
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.*: e2820fe4 stur c4, \[csp, #32\]
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.*: e2900fe4 stur c4, \[csp, #-256\]
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.*: e2cff3e4 stur x4, \[csp, #255\]
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.*: e2c203e4 stur x4, \[csp, #32\]
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.*: e2d003e4 stur x4, \[csp, #-256\]
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.*: e28ff3e4 stur w4, \[csp, #255\]
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.*: e28203e4 stur w4, \[csp, #32\]
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.*: e29003e4 stur w4, \[csp, #-256\]
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.*: e22ff3e4 stur b4, \[csp, #255\]
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.*: e22203e4 stur b4, \[csp, #32\]
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.*: e23003e4 stur b4, \[csp, #-256\]
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.*: e26ff3e4 stur h4, \[csp, #255\]
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.*: e26203e4 stur h4, \[csp, #32\]
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.*: e27003e4 stur h4, \[csp, #-256\]
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.*: e2aff3e4 stur s4, \[csp, #255\]
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.*: e2a203e4 stur s4, \[csp, #32\]
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.*: e2b003e4 stur s4, \[csp, #-256\]
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.*: e2eff3e4 stur d4, \[csp, #255\]
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.*: e2e203e4 stur d4, \[csp, #32\]
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.*: e2f003e4 stur d4, \[csp, #-256\]
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.*: e22ffbe4 stur q4, \[csp, #255\]
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.*: e2220be4 stur q4, \[csp, #32\]
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.*: e2300be4 stur q4, \[csp, #-256\]
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@@ -195,3 +195,15 @@ morello_alt_uimm x4, ALTVAREG, #4088
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morello_alt_uimm x4, ALTSP, #4088
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morello_alt_uimm w4, ALTVAREG, #2044
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morello_alt_uimm w4, ALTSP, #2044
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|
||||
.macro morello_alt_imm cnsp
|
||||
.irp op, ldur, stur
|
||||
.irp rt, c4, x4, w4, b4, h4, s4, d4, q4
|
||||
\op \rt, [\cnsp, #255]
|
||||
\op \rt, [\cnsp, #32]
|
||||
\op \rt, [\cnsp, #-256]
|
||||
.endr
|
||||
.endr
|
||||
.endm
|
||||
morello_alt_imm ALTVAREG
|
||||
morello_alt_imm ALTSP
|
||||
|
||||
@@ -1,3 +1,10 @@
|
||||
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
|
||||
|
||||
* opcode/aarch64.h (aarch64_opnd): Add sz2, Fsz, St and
|
||||
CAPADDR_SIMM9.
|
||||
(aarch64_op): Add OP_STR_POS_3, OP_LDR_POS_3, OP_STR_POS_4,
|
||||
OP_LDR_POS_4, OP_LDUR_3, OP_STUR_3, OP_LDUR_4, OP_STUR_4.
|
||||
|
||||
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
|
||||
|
||||
* opcode/aarch64.c (aarch64.opnd): add Rsz, CAPADDR_REGOFF,
|
||||
|
||||
@@ -231,6 +231,7 @@ enum aarch64_opnd
|
||||
AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */
|
||||
AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */
|
||||
AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */
|
||||
AARCH64_OPND_St, /* AdvSIMD Scalar St. */
|
||||
|
||||
AARCH64_OPND_Va, /* AdvSIMD Vector Va. */
|
||||
AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */
|
||||
@@ -458,6 +459,8 @@ enum aarch64_opnd
|
||||
AARCH64_OPND_Can_SP, /* Capability register or Cap SP as source. */
|
||||
AARCH64_OPND_Cam_SP, /* Capability register or Cap SP as source. */
|
||||
AARCH64_OPND_Rsz, /* Integer register with a size field. */
|
||||
AARCH64_OPND_Rsz2, /* Integer register with a size field. */
|
||||
AARCH64_OPND_Fsz, /* SIMD register with a size field. */
|
||||
AARCH64_OPND_A64C_Rm_EXT, /* Integer Xm extended. */
|
||||
AARCH64_OPND_A64C_IMMV4, /* Immediate value #4 for BX. */
|
||||
AARCH64_OPND_A64C_CST_REG, /* Constant capability register c29 for
|
||||
@@ -477,6 +480,8 @@ enum aarch64_opnd
|
||||
altbase instructions. */
|
||||
AARCH64_OPND_CAPADDR_REGOFF, /* Register offset with capability base for
|
||||
altbase instructions. */
|
||||
AARCH64_OPND_CAPADDR_SIMM9, /* Signed immediate offset with capability base
|
||||
for altbase instructions. */
|
||||
};
|
||||
|
||||
/* Qualifier constrains an operand. It either specifies a variant of an
|
||||
@@ -687,6 +692,10 @@ enum aarch64_op
|
||||
OP_LDR_POS,
|
||||
OP_STR_POS_2,
|
||||
OP_LDR_POS_2,
|
||||
OP_STR_POS_3,
|
||||
OP_LDR_POS_3,
|
||||
OP_STR_POS_4,
|
||||
OP_LDR_POS_4,
|
||||
OP_STRF_POS,
|
||||
OP_LDRF_POS,
|
||||
OP_LDRSW_POS,
|
||||
@@ -702,6 +711,10 @@ enum aarch64_op
|
||||
OP_LDUR,
|
||||
OP_LDUR_2,
|
||||
OP_STUR_2,
|
||||
OP_LDUR_3,
|
||||
OP_STUR_3,
|
||||
OP_LDUR_4,
|
||||
OP_STUR_4,
|
||||
OP_STURV,
|
||||
OP_LDURV,
|
||||
OP_LDURSW,
|
||||
|
||||
@@ -1,3 +1,21 @@
|
||||
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
|
||||
|
||||
* aarch64-asm.c (aarch64_ins_fregsz): New function.
|
||||
(aarch64_ins_addr_simm): Add ldst_altbase to assert.
|
||||
* aarch64-asm.h (ins_fregsz): New function declaration.
|
||||
* aarch64-dis.c (aarch64_ext_fregsz): New function.
|
||||
(aarch64_ext_addr_simm): Disable writeback for ldst_altbase.
|
||||
* aarch64-dis.h (ext_fregsz): New function declaration.
|
||||
* aarch64-opc.c (fields): Add altbase_sf2 and altbase_sf3.
|
||||
(operand_general_constraint_met_p): Add CAPADDR_SIMM9.
|
||||
(aarch64_print_operand): Add CAPADDR_SIMM9, Rsz2, Fsz, St.
|
||||
* aarch64-opc.h (aarch64_field_kind): Add FLD_altbase_sf2, FLD_altbase_sf3.
|
||||
* aarch64-tbl.h (aarch64_opcode_table): New instructions.
|
||||
(AARCH64_OPERANDS): New operands.
|
||||
* aarch64-asm-2.c: Regenerate.
|
||||
* aarch64-dis-2.c: Regenerate.
|
||||
* aarch64-opc-2.c: Regenerate.
|
||||
|
||||
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
|
||||
|
||||
* aarch64-asm.c (aarch64_ins_regsz): New function.
|
||||
|
||||
@@ -435,167 +435,167 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
|
||||
case 1197: /* subs */
|
||||
value = 1197; /* --> subs. */
|
||||
break;
|
||||
case 1372: /* autibsp */
|
||||
case 1371: /* autibz */
|
||||
case 1370: /* autiasp */
|
||||
case 1369: /* autiaz */
|
||||
case 1368: /* pacibsp */
|
||||
case 1367: /* pacibz */
|
||||
case 1366: /* paciasp */
|
||||
case 1365: /* paciaz */
|
||||
case 1344: /* tsb */
|
||||
case 1343: /* psb */
|
||||
case 1342: /* esb */
|
||||
case 1341: /* autib1716 */
|
||||
case 1340: /* autia1716 */
|
||||
case 1339: /* pacib1716 */
|
||||
case 1338: /* pacia1716 */
|
||||
case 1337: /* xpaclri */
|
||||
case 1335: /* sevl */
|
||||
case 1334: /* sev */
|
||||
case 1333: /* wfi */
|
||||
case 1332: /* wfe */
|
||||
case 1331: /* yield */
|
||||
case 1330: /* bti */
|
||||
case 1329: /* csdb */
|
||||
case 1328: /* nop */
|
||||
case 1327: /* hint */
|
||||
value = 1327; /* --> hint. */
|
||||
case 1380: /* autibsp */
|
||||
case 1379: /* autibz */
|
||||
case 1378: /* autiasp */
|
||||
case 1377: /* autiaz */
|
||||
case 1376: /* pacibsp */
|
||||
case 1375: /* pacibz */
|
||||
case 1374: /* paciasp */
|
||||
case 1373: /* paciaz */
|
||||
case 1352: /* tsb */
|
||||
case 1351: /* psb */
|
||||
case 1350: /* esb */
|
||||
case 1349: /* autib1716 */
|
||||
case 1348: /* autia1716 */
|
||||
case 1347: /* pacib1716 */
|
||||
case 1346: /* pacia1716 */
|
||||
case 1345: /* xpaclri */
|
||||
case 1343: /* sevl */
|
||||
case 1342: /* sev */
|
||||
case 1341: /* wfi */
|
||||
case 1340: /* wfe */
|
||||
case 1339: /* yield */
|
||||
case 1338: /* bti */
|
||||
case 1337: /* csdb */
|
||||
case 1336: /* nop */
|
||||
case 1335: /* hint */
|
||||
value = 1335; /* --> hint. */
|
||||
break;
|
||||
case 1349: /* pssbb */
|
||||
case 1348: /* ssbb */
|
||||
case 1347: /* dfb */
|
||||
case 1346: /* dsb */
|
||||
value = 1346; /* --> dsb. */
|
||||
case 1357: /* pssbb */
|
||||
case 1356: /* ssbb */
|
||||
case 1355: /* dfb */
|
||||
case 1354: /* dsb */
|
||||
value = 1354; /* --> dsb. */
|
||||
break;
|
||||
case 1360: /* cpp */
|
||||
case 1359: /* dvp */
|
||||
case 1358: /* cfp */
|
||||
case 1357: /* tlbi */
|
||||
case 1356: /* ic */
|
||||
case 1355: /* dc */
|
||||
case 1354: /* at */
|
||||
case 1353: /* sys */
|
||||
value = 1353; /* --> sys. */
|
||||
case 1368: /* cpp */
|
||||
case 1367: /* dvp */
|
||||
case 1366: /* cfp */
|
||||
case 1365: /* tlbi */
|
||||
case 1364: /* ic */
|
||||
case 1363: /* dc */
|
||||
case 1362: /* at */
|
||||
case 1361: /* sys */
|
||||
value = 1361; /* --> sys. */
|
||||
break;
|
||||
case 2170: /* bic */
|
||||
case 1420: /* and */
|
||||
value = 1420; /* --> and. */
|
||||
case 2178: /* bic */
|
||||
case 1428: /* and */
|
||||
value = 1428; /* --> and. */
|
||||
break;
|
||||
case 1411: /* mov */
|
||||
case 1430: /* and */
|
||||
value = 1430; /* --> and. */
|
||||
break;
|
||||
case 1415: /* movs */
|
||||
case 1431: /* ands */
|
||||
value = 1431; /* --> ands. */
|
||||
break;
|
||||
case 2179: /* cmple */
|
||||
case 1466: /* cmpge */
|
||||
value = 1466; /* --> cmpge. */
|
||||
break;
|
||||
case 2182: /* cmplt */
|
||||
case 1469: /* cmpgt */
|
||||
value = 1469; /* --> cmpgt. */
|
||||
break;
|
||||
case 2180: /* cmplo */
|
||||
case 1471: /* cmphi */
|
||||
value = 1471; /* --> cmphi. */
|
||||
break;
|
||||
case 2181: /* cmpls */
|
||||
case 1474: /* cmphs */
|
||||
value = 1474; /* --> cmphs. */
|
||||
break;
|
||||
case 1408: /* mov */
|
||||
case 1496: /* cpy */
|
||||
value = 1496; /* --> cpy. */
|
||||
break;
|
||||
case 1410: /* mov */
|
||||
case 1497: /* cpy */
|
||||
value = 1497; /* --> cpy. */
|
||||
break;
|
||||
case 2189: /* fmov */
|
||||
case 1413: /* mov */
|
||||
case 1498: /* cpy */
|
||||
value = 1498; /* --> cpy. */
|
||||
break;
|
||||
case 1403: /* mov */
|
||||
case 1422: /* and */
|
||||
value = 1422; /* --> and. */
|
||||
case 1510: /* dup */
|
||||
value = 1510; /* --> dup. */
|
||||
break;
|
||||
case 1407: /* movs */
|
||||
case 1423: /* ands */
|
||||
value = 1423; /* --> ands. */
|
||||
break;
|
||||
case 2171: /* cmple */
|
||||
case 1458: /* cmpge */
|
||||
value = 1458; /* --> cmpge. */
|
||||
break;
|
||||
case 2174: /* cmplt */
|
||||
case 1461: /* cmpgt */
|
||||
value = 1461; /* --> cmpgt. */
|
||||
break;
|
||||
case 2172: /* cmplo */
|
||||
case 1463: /* cmphi */
|
||||
value = 1463; /* --> cmphi. */
|
||||
break;
|
||||
case 2173: /* cmpls */
|
||||
case 1466: /* cmphs */
|
||||
value = 1466; /* --> cmphs. */
|
||||
break;
|
||||
case 1400: /* mov */
|
||||
case 1488: /* cpy */
|
||||
value = 1488; /* --> cpy. */
|
||||
break;
|
||||
case 1402: /* mov */
|
||||
case 1489: /* cpy */
|
||||
value = 1489; /* --> cpy. */
|
||||
break;
|
||||
case 2181: /* fmov */
|
||||
case 1405: /* mov */
|
||||
case 1490: /* cpy */
|
||||
value = 1490; /* --> cpy. */
|
||||
case 1402: /* mov */
|
||||
case 1511: /* dup */
|
||||
value = 1511; /* --> dup. */
|
||||
break;
|
||||
case 1395: /* mov */
|
||||
case 1502: /* dup */
|
||||
value = 1502; /* --> dup. */
|
||||
case 2188: /* fmov */
|
||||
case 1407: /* mov */
|
||||
case 1512: /* dup */
|
||||
value = 1512; /* --> dup. */
|
||||
break;
|
||||
case 1397: /* mov */
|
||||
case 1394: /* mov */
|
||||
case 1503: /* dup */
|
||||
value = 1503; /* --> dup. */
|
||||
case 1406: /* mov */
|
||||
case 1513: /* dupm */
|
||||
value = 1513; /* --> dupm. */
|
||||
break;
|
||||
case 2180: /* fmov */
|
||||
case 1399: /* mov */
|
||||
case 1504: /* dup */
|
||||
value = 1504; /* --> dup. */
|
||||
case 2183: /* eon */
|
||||
case 1515: /* eor */
|
||||
value = 1515; /* --> eor. */
|
||||
break;
|
||||
case 1398: /* mov */
|
||||
case 1505: /* dupm */
|
||||
value = 1505; /* --> dupm. */
|
||||
case 1416: /* not */
|
||||
case 1517: /* eor */
|
||||
value = 1517; /* --> eor. */
|
||||
break;
|
||||
case 2175: /* eon */
|
||||
case 1507: /* eor */
|
||||
value = 1507; /* --> eor. */
|
||||
case 1417: /* nots */
|
||||
case 1518: /* eors */
|
||||
value = 1518; /* --> eors. */
|
||||
break;
|
||||
case 1408: /* not */
|
||||
case 1509: /* eor */
|
||||
value = 1509; /* --> eor. */
|
||||
case 2184: /* facle */
|
||||
case 1523: /* facge */
|
||||
value = 1523; /* --> facge. */
|
||||
break;
|
||||
case 1409: /* nots */
|
||||
case 1510: /* eors */
|
||||
value = 1510; /* --> eors. */
|
||||
case 2185: /* faclt */
|
||||
case 1524: /* facgt */
|
||||
value = 1524; /* --> facgt. */
|
||||
break;
|
||||
case 2176: /* facle */
|
||||
case 1515: /* facge */
|
||||
value = 1515; /* --> facge. */
|
||||
case 2186: /* fcmle */
|
||||
case 1537: /* fcmge */
|
||||
value = 1537; /* --> fcmge. */
|
||||
break;
|
||||
case 2177: /* faclt */
|
||||
case 1516: /* facgt */
|
||||
value = 1516; /* --> facgt. */
|
||||
case 2187: /* fcmlt */
|
||||
case 1539: /* fcmgt */
|
||||
value = 1539; /* --> fcmgt. */
|
||||
break;
|
||||
case 2178: /* fcmle */
|
||||
case 1529: /* fcmge */
|
||||
value = 1529; /* --> fcmge. */
|
||||
case 1400: /* fmov */
|
||||
case 1545: /* fcpy */
|
||||
value = 1545; /* --> fcpy. */
|
||||
break;
|
||||
case 2179: /* fcmlt */
|
||||
case 1531: /* fcmgt */
|
||||
value = 1531; /* --> fcmgt. */
|
||||
break;
|
||||
case 1392: /* fmov */
|
||||
case 1537: /* fcpy */
|
||||
value = 1537; /* --> fcpy. */
|
||||
break;
|
||||
case 1391: /* fmov */
|
||||
case 1560: /* fdup */
|
||||
value = 1560; /* --> fdup. */
|
||||
break;
|
||||
case 1393: /* mov */
|
||||
case 1891: /* orr */
|
||||
value = 1891; /* --> orr. */
|
||||
break;
|
||||
case 2182: /* orn */
|
||||
case 1892: /* orr */
|
||||
value = 1892; /* --> orr. */
|
||||
break;
|
||||
case 1396: /* mov */
|
||||
case 1894: /* orr */
|
||||
value = 1894; /* --> orr. */
|
||||
break;
|
||||
case 1406: /* movs */
|
||||
case 1895: /* orrs */
|
||||
value = 1895; /* --> orrs. */
|
||||
case 1399: /* fmov */
|
||||
case 1568: /* fdup */
|
||||
value = 1568; /* --> fdup. */
|
||||
break;
|
||||
case 1401: /* mov */
|
||||
case 1957: /* sel */
|
||||
value = 1957; /* --> sel. */
|
||||
case 1899: /* orr */
|
||||
value = 1899; /* --> orr. */
|
||||
break;
|
||||
case 2190: /* orn */
|
||||
case 1900: /* orr */
|
||||
value = 1900; /* --> orr. */
|
||||
break;
|
||||
case 1404: /* mov */
|
||||
case 1958: /* sel */
|
||||
value = 1958; /* --> sel. */
|
||||
case 1902: /* orr */
|
||||
value = 1902; /* --> orr. */
|
||||
break;
|
||||
case 1414: /* movs */
|
||||
case 1903: /* orrs */
|
||||
value = 1903; /* --> orrs. */
|
||||
break;
|
||||
case 1409: /* mov */
|
||||
case 1965: /* sel */
|
||||
value = 1965; /* --> sel. */
|
||||
break;
|
||||
case 1412: /* mov */
|
||||
case 1966: /* sel */
|
||||
value = 1966; /* --> sel. */
|
||||
break;
|
||||
default: return NULL;
|
||||
}
|
||||
@@ -640,7 +640,7 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 29:
|
||||
case 30:
|
||||
case 31:
|
||||
case 165:
|
||||
case 32:
|
||||
case 166:
|
||||
case 167:
|
||||
case 168:
|
||||
@@ -650,7 +650,7 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 172:
|
||||
case 173:
|
||||
case 174:
|
||||
case 189:
|
||||
case 175:
|
||||
case 190:
|
||||
case 191:
|
||||
case 192:
|
||||
@@ -659,9 +659,9 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 195:
|
||||
case 196:
|
||||
case 197:
|
||||
case 203:
|
||||
case 206:
|
||||
case 210:
|
||||
case 198:
|
||||
case 204:
|
||||
case 207:
|
||||
case 211:
|
||||
case 212:
|
||||
case 213:
|
||||
@@ -670,33 +670,33 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 216:
|
||||
case 217:
|
||||
case 218:
|
||||
case 219:
|
||||
return aarch64_ins_regno (self, info, code, inst, errors);
|
||||
case 15:
|
||||
case 220:
|
||||
case 223:
|
||||
return aarch64_ins_reg_extended (self, info, code, inst, errors);
|
||||
case 16:
|
||||
return aarch64_ins_reg_shifted (self, info, code, inst, errors);
|
||||
case 21:
|
||||
return aarch64_ins_ft (self, info, code, inst, errors);
|
||||
case 32:
|
||||
case 33:
|
||||
case 34:
|
||||
case 35:
|
||||
case 209:
|
||||
return aarch64_ins_reglane (self, info, code, inst, errors);
|
||||
case 36:
|
||||
return aarch64_ins_reglist (self, info, code, inst, errors);
|
||||
case 210:
|
||||
return aarch64_ins_reglane (self, info, code, inst, errors);
|
||||
case 37:
|
||||
return aarch64_ins_ldst_reglist (self, info, code, inst, errors);
|
||||
return aarch64_ins_reglist (self, info, code, inst, errors);
|
||||
case 38:
|
||||
return aarch64_ins_ldst_reglist_r (self, info, code, inst, errors);
|
||||
return aarch64_ins_ldst_reglist (self, info, code, inst, errors);
|
||||
case 39:
|
||||
return aarch64_ins_ldst_elemlist (self, info, code, inst, errors);
|
||||
return aarch64_ins_ldst_reglist_r (self, info, code, inst, errors);
|
||||
case 40:
|
||||
return aarch64_ins_ldst_elemlist (self, info, code, inst, errors);
|
||||
case 41:
|
||||
case 42:
|
||||
case 43:
|
||||
case 53:
|
||||
case 44:
|
||||
case 54:
|
||||
case 55:
|
||||
case 56:
|
||||
@@ -713,13 +713,13 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 67:
|
||||
case 68:
|
||||
case 69:
|
||||
case 81:
|
||||
case 70:
|
||||
case 82:
|
||||
case 83:
|
||||
case 84:
|
||||
case 162:
|
||||
case 164:
|
||||
case 181:
|
||||
case 85:
|
||||
case 163:
|
||||
case 165:
|
||||
case 182:
|
||||
case 183:
|
||||
case 184:
|
||||
@@ -727,104 +727,105 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 186:
|
||||
case 187:
|
||||
case 188:
|
||||
case 208:
|
||||
case 224:
|
||||
case 232:
|
||||
case 189:
|
||||
case 209:
|
||||
case 227:
|
||||
case 235:
|
||||
return aarch64_ins_imm (self, info, code, inst, errors);
|
||||
case 44:
|
||||
case 45:
|
||||
return aarch64_ins_advsimd_imm_shift (self, info, code, inst, errors);
|
||||
case 46:
|
||||
return aarch64_ins_advsimd_imm_shift (self, info, code, inst, errors);
|
||||
case 47:
|
||||
case 48:
|
||||
case 49:
|
||||
return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors);
|
||||
case 52:
|
||||
case 152:
|
||||
case 53:
|
||||
case 153:
|
||||
return aarch64_ins_fpimm (self, info, code, inst, errors);
|
||||
case 70:
|
||||
case 160:
|
||||
return aarch64_ins_limm (self, info, code, inst, errors);
|
||||
case 71:
|
||||
case 223:
|
||||
case 225:
|
||||
return aarch64_ins_aimm (self, info, code, inst, errors);
|
||||
case 161:
|
||||
return aarch64_ins_limm (self, info, code, inst, errors);
|
||||
case 72:
|
||||
return aarch64_ins_imm_half (self, info, code, inst, errors);
|
||||
case 226:
|
||||
case 228:
|
||||
return aarch64_ins_aimm (self, info, code, inst, errors);
|
||||
case 73:
|
||||
return aarch64_ins_imm_half (self, info, code, inst, errors);
|
||||
case 74:
|
||||
return aarch64_ins_fbits (self, info, code, inst, errors);
|
||||
case 75:
|
||||
case 76:
|
||||
case 157:
|
||||
return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
|
||||
case 77:
|
||||
case 156:
|
||||
case 158:
|
||||
return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
|
||||
return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
|
||||
case 78:
|
||||
case 157:
|
||||
case 159:
|
||||
return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
|
||||
case 79:
|
||||
case 80:
|
||||
return aarch64_ins_cond (self, info, code, inst, errors);
|
||||
case 85:
|
||||
case 94:
|
||||
case 229:
|
||||
return aarch64_ins_addr_simple (self, info, code, inst, errors);
|
||||
case 86:
|
||||
case 234:
|
||||
return aarch64_ins_addr_regoff (self, info, code, inst, errors);
|
||||
case 95:
|
||||
case 232:
|
||||
return aarch64_ins_addr_simple (self, info, code, inst, errors);
|
||||
case 87:
|
||||
case 237:
|
||||
return aarch64_ins_addr_regoff (self, info, code, inst, errors);
|
||||
case 88:
|
||||
case 89:
|
||||
case 91:
|
||||
case 93:
|
||||
case 228:
|
||||
case 230:
|
||||
case 231:
|
||||
return aarch64_ins_addr_simm (self, info, code, inst, errors);
|
||||
case 90:
|
||||
return aarch64_ins_addr_simm10 (self, info, code, inst, errors);
|
||||
case 92:
|
||||
case 94:
|
||||
case 231:
|
||||
case 233:
|
||||
case 234:
|
||||
case 238:
|
||||
return aarch64_ins_addr_simm (self, info, code, inst, errors);
|
||||
case 91:
|
||||
return aarch64_ins_addr_simm10 (self, info, code, inst, errors);
|
||||
case 93:
|
||||
case 236:
|
||||
return aarch64_ins_addr_uimm (self, info, code, inst, errors);
|
||||
case 95:
|
||||
return aarch64_ins_addr_offset (self, info, code, inst, errors);
|
||||
case 96:
|
||||
return aarch64_ins_simd_addr_post (self, info, code, inst, errors);
|
||||
return aarch64_ins_addr_offset (self, info, code, inst, errors);
|
||||
case 97:
|
||||
return aarch64_ins_sysreg (self, info, code, inst, errors);
|
||||
return aarch64_ins_simd_addr_post (self, info, code, inst, errors);
|
||||
case 98:
|
||||
return aarch64_ins_pstatefield (self, info, code, inst, errors);
|
||||
return aarch64_ins_sysreg (self, info, code, inst, errors);
|
||||
case 99:
|
||||
return aarch64_ins_pstatefield (self, info, code, inst, errors);
|
||||
case 100:
|
||||
case 101:
|
||||
case 102:
|
||||
case 103:
|
||||
return aarch64_ins_sysins_op (self, info, code, inst, errors);
|
||||
case 104:
|
||||
return aarch64_ins_sysins_op (self, info, code, inst, errors);
|
||||
case 105:
|
||||
return aarch64_ins_barrier (self, info, code, inst, errors);
|
||||
case 106:
|
||||
return aarch64_ins_prfop (self, info, code, inst, errors);
|
||||
return aarch64_ins_barrier (self, info, code, inst, errors);
|
||||
case 107:
|
||||
return aarch64_ins_none (self, info, code, inst, errors);
|
||||
return aarch64_ins_prfop (self, info, code, inst, errors);
|
||||
case 108:
|
||||
return aarch64_ins_hint (self, info, code, inst, errors);
|
||||
return aarch64_ins_none (self, info, code, inst, errors);
|
||||
case 109:
|
||||
return aarch64_ins_hint (self, info, code, inst, errors);
|
||||
case 110:
|
||||
return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
|
||||
case 111:
|
||||
return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
|
||||
case 112:
|
||||
case 113:
|
||||
case 114:
|
||||
return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
|
||||
case 115:
|
||||
return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
|
||||
return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
|
||||
case 116:
|
||||
return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
|
||||
return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
|
||||
case 117:
|
||||
return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
|
||||
case 118:
|
||||
case 119:
|
||||
case 120:
|
||||
return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
|
||||
case 121:
|
||||
return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
|
||||
case 122:
|
||||
case 123:
|
||||
case 124:
|
||||
@@ -838,8 +839,8 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 132:
|
||||
case 133:
|
||||
case 134:
|
||||
return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
|
||||
case 135:
|
||||
return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
|
||||
case 136:
|
||||
case 137:
|
||||
case 138:
|
||||
@@ -847,58 +848,62 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 140:
|
||||
case 141:
|
||||
case 142:
|
||||
return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
|
||||
case 143:
|
||||
return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
|
||||
case 144:
|
||||
case 145:
|
||||
case 146:
|
||||
return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
|
||||
case 147:
|
||||
return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
|
||||
return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
|
||||
case 148:
|
||||
return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
|
||||
return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
|
||||
case 149:
|
||||
return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
|
||||
return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
|
||||
case 150:
|
||||
return aarch64_ins_sve_aimm (self, info, code, inst, errors);
|
||||
return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
|
||||
case 151:
|
||||
return aarch64_ins_sve_aimm (self, info, code, inst, errors);
|
||||
case 152:
|
||||
return aarch64_ins_sve_asimm (self, info, code, inst, errors);
|
||||
case 153:
|
||||
return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
|
||||
case 154:
|
||||
return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
|
||||
return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
|
||||
case 155:
|
||||
return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
|
||||
case 156:
|
||||
return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors);
|
||||
case 159:
|
||||
case 160:
|
||||
return aarch64_ins_inv_limm (self, info, code, inst, errors);
|
||||
case 161:
|
||||
case 162:
|
||||
return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
|
||||
case 163:
|
||||
case 164:
|
||||
return aarch64_ins_sve_scale (self, info, code, inst, errors);
|
||||
case 175:
|
||||
case 176:
|
||||
case 177:
|
||||
return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
|
||||
case 178:
|
||||
return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
|
||||
case 179:
|
||||
case 180:
|
||||
case 181:
|
||||
return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
|
||||
case 198:
|
||||
case 199:
|
||||
case 200:
|
||||
case 201:
|
||||
case 202:
|
||||
case 203:
|
||||
return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
|
||||
case 204:
|
||||
return aarch64_ins_sve_index (self, info, code, inst, errors);
|
||||
case 205:
|
||||
case 207:
|
||||
return aarch64_ins_sve_index (self, info, code, inst, errors);
|
||||
case 206:
|
||||
case 208:
|
||||
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
|
||||
case 219:
|
||||
case 220:
|
||||
case 221:
|
||||
return aarch64_ins_regsz (self, info, code, inst, errors);
|
||||
case 226:
|
||||
case 222:
|
||||
return aarch64_ins_fregsz (self, info, code, inst, errors);
|
||||
case 229:
|
||||
return aarch64_ins_perm (self, info, code, inst, errors);
|
||||
case 227:
|
||||
case 230:
|
||||
return aarch64_ins_form (self, info, code, inst, errors);
|
||||
default: assert (0); abort ();
|
||||
}
|
||||
|
||||
@@ -596,6 +596,30 @@ aarch64_ins_regsz (const aarch64_operand *self, const aarch64_opnd_info *info,
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
/* Encode SIMD register and an additional field that specifies size.
|
||||
e.g. altbase instructions. */
|
||||
bfd_boolean
|
||||
aarch64_ins_fregsz (const aarch64_operand *self, const aarch64_opnd_info *info,
|
||||
aarch64_insn *code, const aarch64_inst *inst,
|
||||
aarch64_operand_error *errors)
|
||||
{
|
||||
aarch64_insn value = 0;
|
||||
|
||||
aarch64_ins_regno (self, info, code, inst, errors);
|
||||
|
||||
switch (info->qualifier)
|
||||
{
|
||||
case AARCH64_OPND_QLF_S_B: value = 0; break;
|
||||
case AARCH64_OPND_QLF_S_H: value = 1; break;
|
||||
case AARCH64_OPND_QLF_S_S: value = 2; break;
|
||||
case AARCH64_OPND_QLF_S_D: value = 3; break;
|
||||
default: assert (0);
|
||||
}
|
||||
|
||||
insert_field (self->fields[1], code, value, 0);
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
/* Encode Ft for e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]
|
||||
or LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>. */
|
||||
bfd_boolean
|
||||
@@ -745,7 +769,8 @@ aarch64_ins_addr_simm (const aarch64_operand *self,
|
||||
&& inst->opcode->iclass != ldstnapair_offs
|
||||
&& inst->opcode->iclass != ldstpair_off
|
||||
&& inst->opcode->iclass != ldst_unpriv
|
||||
&& inst->opcode->iclass != br_capaddr);
|
||||
&& inst->opcode->iclass != br_capaddr
|
||||
&& inst->opcode->iclass != ldst_altbase);
|
||||
assert (info->addr.preind != info->addr.postind);
|
||||
if (info->addr.preind)
|
||||
insert_field (self->fields[1], code, 1, 0);
|
||||
|
||||
@@ -45,6 +45,7 @@ bfd_boolean aarch64_insert_operand (const aarch64_operand *,
|
||||
AARCH64_DECL_OPD_INSERTER (ins_none);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_regno);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_regsz);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_fregsz);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_reglane);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_reglist);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_ldst_reglist);
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1027,6 +1027,34 @@ aarch64_ext_regsz (const aarch64_operand *self ATTRIBUTE_UNUSED,
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
/* Decode SIMD register using an additional field that specifies size.
|
||||
e.g. altbase instructions. */
|
||||
bfd_boolean
|
||||
aarch64_ext_fregsz (const aarch64_operand *self ATTRIBUTE_UNUSED,
|
||||
aarch64_opnd_info *info,
|
||||
const aarch64_insn code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED,
|
||||
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
|
||||
{
|
||||
|
||||
enum aarch64_opnd_qualifier qualifier;
|
||||
aarch64_insn value = extract_field (self->fields[1], code, 0);
|
||||
|
||||
info->reg.regno = extract_field (self->fields[0], code, 0);
|
||||
|
||||
switch (value)
|
||||
{
|
||||
case 0: qualifier = AARCH64_OPND_QLF_S_B; break;
|
||||
case 1: qualifier = AARCH64_OPND_QLF_S_H; break;
|
||||
case 2: qualifier = AARCH64_OPND_QLF_S_S; break;
|
||||
case 3: qualifier = AARCH64_OPND_QLF_S_D; break;
|
||||
default: return FALSE;
|
||||
}
|
||||
info->qualifier = qualifier;
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
/* Decode Ft for e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]
|
||||
or LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>. */
|
||||
bfd_boolean
|
||||
@@ -1190,7 +1218,8 @@ aarch64_ext_addr_simm (const aarch64_operand *self, aarch64_opnd_info *info,
|
||||
|| inst->opcode->iclass == ldstnapair_offs
|
||||
|| inst->opcode->iclass == ldstpair_off
|
||||
|| inst->opcode->iclass == ldst_unpriv
|
||||
|| inst->opcode->iclass == br_capaddr)
|
||||
|| inst->opcode->iclass == br_capaddr
|
||||
|| inst->opcode->iclass == ldst_altbase)
|
||||
info->addr.writeback = 0;
|
||||
else
|
||||
{
|
||||
|
||||
@@ -65,6 +65,7 @@ aarch64_extract_operand (const aarch64_operand *, aarch64_opnd_info *,
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_none);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_regno);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_regsz);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_fregsz);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_regno_pair);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_regrt_sysins);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_reglane);
|
||||
|
||||
@@ -50,6 +50,7 @@ const struct aarch64_operand aarch64_operands[] =
|
||||
{AARCH64_OPND_CLASS_SISD_REG, "Sd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a SIMD scalar register"},
|
||||
{AARCH64_OPND_CLASS_SISD_REG, "Sn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD scalar register"},
|
||||
{AARCH64_OPND_CLASS_SISD_REG, "Sm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD scalar register"},
|
||||
{AARCH64_OPND_CLASS_SIMD_REG, "St", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "a SIMD scalar register"},
|
||||
{AARCH64_OPND_CLASS_SIMD_REG, "Va", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Ra}, "a SIMD vector register"},
|
||||
{AARCH64_OPND_CLASS_SIMD_REG, "Vd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a SIMD vector register"},
|
||||
{AARCH64_OPND_CLASS_SIMD_REG, "Vn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector register"},
|
||||
@@ -244,6 +245,8 @@ const struct aarch64_operand aarch64_operands[] =
|
||||
{AARCH64_OPND_CLASS_CAP_REG, "Can_SP", OPD_F_MAYBE_CSP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Can}, "a Capability register or a capability stack pointer register"},
|
||||
{AARCH64_OPND_CLASS_CAP_REG, "Cam_SP", OPD_F_MAYBE_CSP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Cam}, "a Capability register or a capability stack pointer register"},
|
||||
{AARCH64_OPND_CLASS_INT_REG, "Rsz", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt, FLD_altbase_sf}, "an integer register"},
|
||||
{AARCH64_OPND_CLASS_INT_REG, "Rsz2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt, FLD_altbase_sf2}, "an integer register"},
|
||||
{AARCH64_OPND_CLASS_INT_REG, "Fsz", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt, FLD_altbase_sf3}, "an integer register"},
|
||||
{AARCH64_OPND_CLASS_MODIFIED_REG, "A64C_Rm_EXT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an integer register with extension"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "A64C_IMMV4", OPD_F_HAS_EXTRACTOR, {}, "4"},
|
||||
{AARCH64_OPND_CLASS_CAP_REG, "A64C_CST_REG", OPD_F_HAS_EXTRACTOR, {}, "capability register c29"},
|
||||
@@ -259,6 +262,7 @@ const struct aarch64_operand aarch64_operands[] =
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL17", OPD_F_SEXT | OPD_F_SHIFT_BY_4 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm17}, "17-bit PC-relative address"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "CAPADDR_UIMM9", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn, FLD_imm9}, "a capability address with 9-bit unsigned immediate offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "CAPADDR_REGOFF", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a capability address with register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "CAPADDR_SIMM9", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9}, "a capability address with 9-bit signed immediate offset"},
|
||||
{AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"},
|
||||
};
|
||||
|
||||
@@ -278,6 +282,10 @@ static const unsigned op_enum_table [] =
|
||||
898,
|
||||
1275,
|
||||
1274,
|
||||
1301,
|
||||
1296,
|
||||
1302,
|
||||
1297,
|
||||
892,
|
||||
893,
|
||||
899,
|
||||
@@ -292,6 +300,10 @@ static const unsigned op_enum_table [] =
|
||||
931,
|
||||
1282,
|
||||
1283,
|
||||
1306,
|
||||
1310,
|
||||
1307,
|
||||
1311,
|
||||
925,
|
||||
926,
|
||||
932,
|
||||
@@ -342,17 +354,17 @@ static const unsigned op_enum_table [] =
|
||||
391,
|
||||
413,
|
||||
415,
|
||||
1396,
|
||||
1401,
|
||||
1394,
|
||||
1393,
|
||||
1397,
|
||||
1404,
|
||||
1406,
|
||||
1407,
|
||||
1403,
|
||||
1409,
|
||||
1408,
|
||||
1402,
|
||||
1401,
|
||||
1405,
|
||||
1412,
|
||||
1414,
|
||||
1415,
|
||||
1411,
|
||||
1417,
|
||||
1416,
|
||||
1191,
|
||||
131,
|
||||
};
|
||||
|
||||
@@ -350,6 +350,8 @@ const aarch64_field fields[] =
|
||||
XXX We should make the SF fields into full fields throughout
|
||||
the code base and even identify capability registers that
|
||||
way. The OP in the altbase instructions allow that. */
|
||||
{ 22, 1 }, /* altbase_sf2: Size bit in altbase LDUR. */
|
||||
{ 22, 2 }, /* altbase_sf3: Size bits in altbase SIMD LDUR. */
|
||||
};
|
||||
|
||||
enum aarch64_operand_class
|
||||
@@ -1749,6 +1751,7 @@ operand_general_constraint_met_p (aarch64_feature_set features,
|
||||
}
|
||||
break;
|
||||
case AARCH64_OPND_ADDR_OFFSET:
|
||||
case AARCH64_OPND_CAPADDR_SIMM9:
|
||||
case AARCH64_OPND_ADDR_SIMM9:
|
||||
/* Unscaled signed 9 bits immediate offset. */
|
||||
if (!value_in_range_p (opnd->addr.offset.imm, -256, 255))
|
||||
@@ -3367,6 +3370,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
|
||||
switch (opnd->type)
|
||||
{
|
||||
case AARCH64_OPND_Rsz:
|
||||
case AARCH64_OPND_Rsz2:
|
||||
case AARCH64_OPND_Rd:
|
||||
case AARCH64_OPND_Rn:
|
||||
case AARCH64_OPND_Rm:
|
||||
@@ -3456,6 +3460,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
|
||||
opnd->shifter.amount);
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_Fsz:
|
||||
case AARCH64_OPND_Fd:
|
||||
case AARCH64_OPND_Fn:
|
||||
case AARCH64_OPND_Fm:
|
||||
@@ -3465,6 +3470,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
|
||||
case AARCH64_OPND_Sd:
|
||||
case AARCH64_OPND_Sn:
|
||||
case AARCH64_OPND_Sm:
|
||||
case AARCH64_OPND_St:
|
||||
case AARCH64_OPND_SVE_VZn:
|
||||
case AARCH64_OPND_SVE_Vd:
|
||||
case AARCH64_OPND_SVE_Vm:
|
||||
@@ -3884,9 +3890,11 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
|
||||
get_addr_sve_reg_name (opnd->addr.offset.regno, opnd->qualifier));
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_CAPADDR_SIMM9:
|
||||
case AARCH64_OPND_CAPADDR_SIMM7:
|
||||
print_immediate_offset_address
|
||||
(buf, size, opnd, get_cap_reg_name (opnd->addr.base_regno, 1));
|
||||
(buf, size, opnd,
|
||||
get_altbase_reg_name (features, opnd->addr.base_regno, 1, opcode));
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_A64C_ADDR_SIMM9:
|
||||
|
||||
@@ -170,6 +170,8 @@ enum aarch64_field_kind
|
||||
FLD_a64c_index2,
|
||||
FLD_imm17,
|
||||
FLD_altbase_sf,
|
||||
FLD_altbase_sf2,
|
||||
FLD_altbase_sf3,
|
||||
};
|
||||
|
||||
/* Field description. */
|
||||
|
||||
@@ -4077,16 +4077,24 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
||||
A64C_INSN ("stlr", 0x421f7c00, 0xfffffc00, ldstexcl, 0, OP2 (Cat, CAPADDR_SIMPLE), QL2_A64C_CA_ADDR, 0),
|
||||
A64C_INSN ("stlr", 0x423ffc00, 0xfffffc00, ldstexcl, 0, OP2 (Wt, CAPADDR_SIMPLE), QL2_A64C_W_CAPADDR, 0),
|
||||
A64C_INSN ("stlrb", 0x423f7c00, 0xfffffc00, ldstexcl, 0, OP2 (Wt, CAPADDR_SIMPLE), QL2_A64C_W_CAPADDR, 0),
|
||||
A64C_INSN ("ldr", 0x82600000, 0xffe00c00, ldst_altbase, 0, OP2 (Cat, CAPADDR_UIMM9), QL2_A64C_CA_CAPADDR, 0),
|
||||
A64C_INSN ("ldr", 0x82600800, 0xffe00800, ldst_altbase, 0, OP2 (Rsz, CAPADDR_UIMM9), QL2_A64C_R_CAPADDR, 0),
|
||||
A64C_INSN ("ldr", 0x82600000, 0xffe00c00, ldst_altbase, OP_LDR_POS_3, OP2 (Cat, CAPADDR_UIMM9), QL2_A64C_CA_CAPADDR, 0),
|
||||
A64C_INSN ("ldr", 0x82600800, 0xffe00800, ldst_altbase, OP_LDR_POS_4, OP2 (Rsz, CAPADDR_UIMM9), QL2_A64C_R_CAPADDR, 0),
|
||||
A64C_INSN ("ldr", 0xc2e00c00, 0xffe00c00, ldst_altbase, 0, OP2 (Cat, CAPADDR_REGOFF), QL2_A64C_CA_CAPADDR, 0),
|
||||
A64C_INSN ("ldr", 0x82e00000, 0xffe00800, ldst_altbase, 0, OP2 (Rsz, CAPADDR_REGOFF), QL2_A64C_R_CAPADDR, 0),
|
||||
A64C_INSN ("ldr", 0x82e00800, 0xffe00800, ldst_altbase, 0, OP2 (Ft, CAPADDR_REGOFF), QL2_A64C_FP_CAPADDR, 0),
|
||||
A64C_INSN ("str", 0x82400000, 0xffe00c00, ldst_altbase, 0, OP2 (Cat, CAPADDR_UIMM9), QL2_A64C_CA_CAPADDR, 0),
|
||||
A64C_INSN ("str", 0x82400800, 0xffe00800, ldst_altbase, 0, OP2 (Rsz, CAPADDR_UIMM9), QL2_A64C_R_CAPADDR, 0),
|
||||
A64C_INSN ("str", 0x82400000, 0xffe00c00, ldst_altbase, OP_STR_POS_3, OP2 (Cat, CAPADDR_UIMM9), QL2_A64C_CA_CAPADDR, 0),
|
||||
A64C_INSN ("str", 0x82400800, 0xffe00800, ldst_altbase, OP_STR_POS_4, OP2 (Rsz, CAPADDR_UIMM9), QL2_A64C_R_CAPADDR, 0),
|
||||
A64C_INSN ("str", 0xc2e00400, 0xffe00c00, ldst_altbase, 0, OP2 (Cat, CAPADDR_REGOFF), QL2_A64C_CA_CAPADDR, 0),
|
||||
A64C_INSN ("str", 0x82a00000, 0xffe00800, ldst_altbase, 0, OP2 (Rsz, CAPADDR_REGOFF), QL2_A64C_R_CAPADDR, 0),
|
||||
A64C_INSN ("str", 0x82a00800, 0xffe00800, ldst_altbase, 0, OP2 (Ft, CAPADDR_REGOFF), QL2_A64C_FP_CAPADDR, 0),
|
||||
A64C_INSN ("ldur", 0xe2c00c00, 0xffe00c00, ldst_altbase, OP_LDUR_3, OP2 (Cat, CAPADDR_SIMM9), QL2_A64C_CA_CAPADDR, 0),
|
||||
A64C_INSN ("ldur", 0xe2800400, 0xffa00c00, ldst_altbase, OP_LDUR_4, OP2 (Rsz2, CAPADDR_SIMM9), QL2_A64C_R_CAPADDR, 0),
|
||||
A64C_INSN ("ldur", 0xe2200400, 0xff200c00, ldst_altbase, 0, OP2 (Fsz, CAPADDR_SIMM9), QL_S_2SAME, 0),
|
||||
A64C_INSN ("ldur", 0xe2200c00, 0xffe00c00, ldst_altbase, 0, OP2 (St, CAPADDR_SIMM9), QL_I2SAMEQ, 0),
|
||||
A64C_INSN ("stur", 0xe2800c00, 0xffe00c00, ldst_altbase, OP_STUR_3, OP2 (Cat, CAPADDR_SIMM9), QL2_A64C_CA_CAPADDR, 0),
|
||||
A64C_INSN ("stur", 0xe2800000, 0xffa00c00, ldst_altbase, OP_STUR_4, OP2 (Rsz2, CAPADDR_SIMM9), QL2_A64C_R_CAPADDR, 0),
|
||||
A64C_INSN ("stur", 0xe2200000, 0xff200c00, ldst_altbase, 0, OP2 (Fsz, CAPADDR_SIMM9), QL_S_2SAME, 0),
|
||||
A64C_INSN ("stur", 0xe2200800, 0xffe00c00, ldst_altbase, 0, OP2 (St, CAPADDR_SIMM9), QL_I2SAMEQ, 0),
|
||||
|
||||
A64C_INSN ("ret", 0xc2c25000, 0xfffffc1f, a64c, 0, OP1 (Can), QL1_A64C_CA, F_OPD0_OPT | F_DEFAULT (30)),
|
||||
A64C_INSN ("retr", 0xc2c25003, 0xfffffc1f, a64c, 0, OP1 (Can), QL1_A64C_CA, 0),
|
||||
@@ -5456,6 +5464,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
||||
Y(SISD_REG, regno, "Sd", 0, F(FLD_Rd), "a SIMD scalar register") \
|
||||
Y(SISD_REG, regno, "Sn", 0, F(FLD_Rn), "a SIMD scalar register") \
|
||||
Y(SISD_REG, regno, "Sm", 0, F(FLD_Rm), "a SIMD scalar register") \
|
||||
Y(SIMD_REG, regno, "St", 0, F(FLD_Rt), "a SIMD scalar register") \
|
||||
Y(SIMD_REG, regno, "Va", 0, F(FLD_Ra), "a SIMD vector register") \
|
||||
Y(SIMD_REG, regno, "Vd", 0, F(FLD_Rd), "a SIMD vector register") \
|
||||
Y(SIMD_REG, regno, "Vn", 0, F(FLD_Rn), "a SIMD vector register") \
|
||||
@@ -5868,6 +5877,10 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
||||
"a Capability register or a capability stack pointer register") \
|
||||
Y(INT_REG, regsz, "Rsz", 0, F(FLD_Rt, FLD_altbase_sf), \
|
||||
"an integer register") \
|
||||
Y(INT_REG, regsz, "Rsz2", 0, F(FLD_Rt, FLD_altbase_sf2), \
|
||||
"an integer register") \
|
||||
Y(INT_REG, fregsz, "Fsz", 0, F(FLD_Rt, FLD_altbase_sf3), \
|
||||
"an integer register") \
|
||||
Y(MODIFIED_REG, reg_extended, "A64C_Rm_EXT", 0, F(), \
|
||||
"an integer register with extension") \
|
||||
X(IMMEDIATE, 0, ext_a64c_immv, "A64C_IMMV4", 0, F(), "4") \
|
||||
@@ -5899,4 +5912,6 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
||||
Y(ADDRESS, addr_uimm, "CAPADDR_UIMM9", 0, F(FLD_Rn, FLD_imm9), \
|
||||
"a capability address with 9-bit unsigned immediate offset") \
|
||||
Y(ADDRESS, addr_regoff, "CAPADDR_REGOFF", 0, F(), \
|
||||
"a capability address with register offset")
|
||||
"a capability address with register offset") \
|
||||
Y(ADDRESS, addr_simm, "CAPADDR_SIMM9", 0, F(FLD_imm9), \
|
||||
"a capability address with 9-bit signed immediate offset")
|
||||
|
||||
Reference in New Issue
Block a user