import gdb-2000-02-04 snapshot

sim/mips/ChangeLog

@@ -1,3 +1,8 @@
+Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
+
+	* sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
+	cache don't get ReservedInstruction traps.
+
 1999-11-29  Mark Salter  <msalter@cygnus.com>
 
 	* dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask

sim/mips/sim-main.c

@@ -463,6 +463,7 @@ cache_op (SIM_DESC SD,
       break;
 
     case 1: /* data cache */
+    case 3: /* secondary data cache */
       switch (op >> 2) {
         case 0: /* Index Writeback Invalidate */
         case 1: /* Index Load Tag */