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bfd/

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2011-02-25  Chao-ying Fu  <fu@mips.com>
            Ilie Garbacea  <ilie@mips.com>
            Maciej W. Rozycki  <macro@codesourcery.com>
            Joseph Myers  <joseph@codesourcery.com>
            Catherine Moore  <clm@codesourcery.com>
	    Richard Sandiford  <rdsandiford@googlemail.com>

	* archures.c (bfd_mach_mips_micromips): New macro.
	* cpu-mips.c (I_micromips): New enum value.
	(arch_info_struct): Add bfd_mach_mips_micromips.
	* elfxx-mips.h (_bfd_mips_elf_is_target_special_symbol): New
	prototype.
	(_bfd_mips_elf_relax_section): Likewise.
	(_bfd_mips16_elf_reloc_unshuffle): Rename to...
	(_bfd_mips_elf_reloc_unshuffle): ... this.  Handle microMIPS
	ASE.
	(_bfd_mips16_elf_reloc_shuffle): Rename to...
	(_bfd_mips_elf_reloc_shuffle): ... this.  Handle microMIPS ASE.
	(gprel16_reloc_p): Handle microMIPS ASE.
	(literal_reloc_p): New function.
	* elf32-mips.c (elf_micromips_howto_table_rel): New variable.
	(_bfd_mips_elf32_gprel16_reloc): Handle microMIPS ASE.
	(mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle
	and _bfd_mips_elf_reloc_shuffle changes.
	(mips_elf_gprel32_reloc): Update comment.
	(micromips_reloc_map): New variable.
	(bfd_elf32_bfd_reloc_type_lookup): Handle microMIPS ASE.
	(mips_elf32_rtype_to_howto): Likewise.
	(mips_info_to_howto_rel): Likewise.
	(bfd_elf32_bfd_is_target_special_symbol): Define.
	(bfd_elf32_bfd_relax_section): Likewise.
	* elf64-mips.c (micromips_elf64_howto_table_rel): New variable.
	(micromips_elf64_howto_table_rela): Likewise.
	(mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle
	and _bfd_mips_elf_reloc_shuffle changes.
	(micromips_reloc_map): Likewise.
	(bfd_elf64_bfd_reloc_type_lookup): Handle microMIPS ASE.
	(bfd_elf64_bfd_reloc_name_lookup): Likewise.
	(mips_elf64_rtype_to_howto): Likewise.
	(bfd_elf64_bfd_is_target_special_symbol): Define.
	* elfn32-mips.c (elf_micromips_howto_table_rel): New variable.
	(elf_micromips_howto_table_rela): Likewise.
	(mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle
	and _bfd_mips_elf_reloc_shuffle changes.
	(micromips_reloc_map): Likewise.
	(bfd_elf32_bfd_reloc_type_lookup): Handle microMIPS ASE.
	(bfd_elf32_bfd_reloc_name_lookup): Likewise.
	(mips_elf_n32_rtype_to_howto): Likewise.
	(bfd_elf32_bfd_is_target_special_symbol): Define.
	* elfxx-mips.c (LA25_LUI_MICROMIPS_1): New macro.
	(LA25_LUI_MICROMIPS_2): Likewise.
	(LA25_J_MICROMIPS_1, LA25_J_MICROMIPS_2): Likewise.
	(LA25_ADDIU_MICROMIPS_1, LA25_ADDIU_MICROMIPS_2): Likewise.
	(TLS_RELOC_P): Handle microMIPS ASE.
	(mips_elf_create_stub_symbol): Adjust value of stub symbol if
	target is a microMIPS function.
	(micromips_reloc_p): New function.
	(micromips_reloc_shuffle_p): Likewise.
	(got16_reloc_p, call16_reloc_p): Handle microMIPS ASE.
	(got_disp_reloc_p, got_page_reloc_p): New functions.
	(got_ofst_reloc_p): Likewise.
	(got_hi16_reloc_p, got_lo16_reloc_p): Likewise.
	(call_hi16_reloc_p, call_lo16_reloc_p): Likewise.
	(hi16_reloc_p, lo16_reloc_p, jal_reloc_p): Handle microMIPS ASE.
	(micromips_branch_reloc_p): New function.
	(tls_gd_reloc_p, tls_ldm_reloc_p): Likewise.
	(tls_gottprel_reloc_p): Likewise.
	(_bfd_mips16_elf_reloc_unshuffle): Rename to...
	(_bfd_mips_elf_reloc_unshuffle): ... this.  Handle microMIPS
	ASE.
	(_bfd_mips16_elf_reloc_shuffle): Rename to...
	(_bfd_mips_elf_reloc_shuffle): ... this.  Handle microMIPS ASE.
	(_bfd_mips_elf_lo16_reloc): Handle microMIPS ASE.
	(mips_tls_got_index, mips_elf_got_page): Likewise.
	(mips_elf_create_local_got_entry): Likewise.
	(mips_elf_relocation_needs_la25_stub): Likewise.
	(mips_elf_calculate_relocation): Likewise.
	(mips_elf_perform_relocation): Likewise.
	(_bfd_mips_elf_symbol_processing): Likewise.
	(_bfd_mips_elf_add_symbol_hook): Likewise.
	(_bfd_mips_elf_link_output_symbol_hook): Likewise.
	(mips_elf_add_lo16_rel_addend): Likewise.
	(_bfd_mips_elf_check_relocs): Likewise.
	(mips_elf_adjust_addend): Likewise.
	(_bfd_mips_elf_relocate_section): Likewise.
	(mips_elf_create_la25_stub): Likewise.
	(_bfd_mips_vxworks_finish_dynamic_symbol): Likewise.
	(_bfd_mips_elf_gc_sweep_hook): Likewise.
	(_bfd_mips_elf_is_target_special_symbol): New function.
	(mips_elf_relax_delete_bytes): Likewise.
	(opcode_descriptor): New structure.
	(RA): New macro.
	(OP32_SREG, OP32_TREG, OP16_VALID_REG): Likewise.
	(b_insns_32, bc_insn_32, bz_insn_32, bzal_insn_32): New variables.
	(beq_insn_32): Likewise.
	(b_insn_16, bz_insn_16): New variables.
	(BZC32_REG_FIELD): New macro.
	(bz_rs_insns_32, bz_rt_insns_32): New variables.
	(bzc_insns_32, bz_insns_16):Likewise.
	(BZ16_REG, BZ16_REG_FIELD): New macros.
	(jal_insn_32_bd16, jal_insn_32_bd32): New variables.
	(jal_x_insn_32_bd32): Likewise.
	(j_insn_32, jalr_insn_32): Likewise.
	(ds_insns_32_bd16, ds_insns_32_bd32): Likewise.
	(jalr_insn_16_bd16, jalr_insn_16_bd32, jr_insn_16): Likewise.
	(JR16_REG): New macro.
	(ds_insns_16_bd16): New variable.
	(lui_insn): Likewise.
	(addiu_insn, addiupc_insn): Likewise.
	(ADDIUPC_REG_FIELD): New macro.
	(MOVE32_RD, MOVE32_RS): Likewise.
	(MOVE16_RD_FIELD, MOVE16_RS_FIELD): Likewise.
	(move_insns_32, move_insns_16): New variables.
	(nop_insn_32, nop_insn_16): Likewise.
	(MATCH): New macro.
	(find_match): New function.
	(check_br16_dslot, check_br32_dslot): Likewise.
	(check_br16, check_br32): Likewise.
	(IS_BITSIZE): New macro.
	(check_4byte_branch): New function.
	(_bfd_mips_elf_relax_section): Likewise.
	(_bfd_mips_elf_merge_private_bfd_data): Disallow linking MIPS16
	and microMIPS modules together.
	(_bfd_mips_elf_print_private_bfd_data):	Handle microMIPS ASE.
	* reloc.c (BFD_RELOC_MICROMIPS_7_PCREL_S1): New relocation.
	(BFD_RELOC_MICROMIPS_10_PCREL_S1): Likewise.
	(BFD_RELOC_MICROMIPS_16_PCREL_S1): Likewise.
	(BFD_RELOC_MICROMIPS_GPREL16): Likewise.
	(BFD_RELOC_MICROMIPS_JMP, BFD_RELOC_MICROMIPS_HI16): Likewise.
	(BFD_RELOC_MICROMIPS_HI16_S): Likewise.
	(BFD_RELOC_MICROMIPS_LO16): Likewise.
	(BFD_RELOC_MICROMIPS_LITERAL): Likewise.
	(BFD_RELOC_MICROMIPS_GOT16): Likewise.
	(BFD_RELOC_MICROMIPS_CALL16): Likewise.
	(BFD_RELOC_MICROMIPS_GOT_HI16): Likewise.
	(BFD_RELOC_MICROMIPS_GOT_LO16): Likewise.
	(BFD_RELOC_MICROMIPS_CALL_HI16): Likewise.
	(BFD_RELOC_MICROMIPS_CALL_LO16): Likewise.
	(BFD_RELOC_MICROMIPS_SUB): Likewise.
	(BFD_RELOC_MICROMIPS_GOT_PAGE): Likewise.
	(BFD_RELOC_MICROMIPS_GOT_OFST): Likewise.
	(BFD_RELOC_MICROMIPS_GOT_DISP): Likewise.
	(BFD_RELOC_MICROMIPS_HIGHEST): Likewise.
	(BFD_RELOC_MICROMIPS_HIGHER): Likewise.
	(BFD_RELOC_MICROMIPS_SCN_DISP): Likewise.
	(BFD_RELOC_MICROMIPS_JALR): Likewise.
	(BFD_RELOC_MICROMIPS_TLS_GD): Likewise.
	(BFD_RELOC_MICROMIPS_TLS_LDM): Likewise.
	(BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16): Likewise.
	(BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16): Likewise.
	(BFD_RELOC_MICROMIPS_TLS_GOTTPREL): Likewise.
	(BFD_RELOC_MICROMIPS_TLS_TPREL_HI16): Likewise.
	(BFD_RELOC_MICROMIPS_TLS_TPREL_LO16): Likewise.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.

binutils/
2011-02-25  Chao-ying Fu  <fu@mips.com>
            Maciej W. Rozycki  <macro@codesourcery.com>

	* readelf.c (get_machine_flags): Handle microMIPS ASE.
	(get_mips_symbol_other): Likewise.

gas/
2011-02-25  Maciej W. Rozycki  <macro@codesourcery.com>
            Chao-ying Fu  <fu@mips.com>
	    Richard Sandiford  <rdsandiford@googlemail.com>

	* config/tc-mips.h (mips_segment_info): Add one bit for
	microMIPS.
	(TC_LABEL_IS_LOCAL): New macro.
	(mips_label_is_local): New prototype.
	* config/tc-mips.c (S0, S7): New macros.
	(emit_branch_likely_macro): New variable.
	(mips_set_options): Add micromips.
	(mips_opts): Initialise micromips to -1.
	(file_ase_micromips): New variable.
	(CPU_HAS_MICROMIPS): New macro.
	(hilo_interlocks): Set for microMIPS too.
	(gpr_interlocks): Likewise.
	(cop_interlocks): Likewise.
	(cop_mem_interlocks): Likewise.
	(HAVE_CODE_COMPRESSION): New macro.
	(micromips_op_hash): New variable.
	(micromips_nop16_insn, micromips_nop32_insn): New variables.
	(NOP_INSN): Handle microMIPS ASE.
	(mips32_to_micromips_reg_b_map): New macro.
	(mips32_to_micromips_reg_c_map): Likewise.
	(mips32_to_micromips_reg_d_map): Likewise.
	(mips32_to_micromips_reg_e_map): Likewise.
	(mips32_to_micromips_reg_f_map): Likewise.
	(mips32_to_micromips_reg_g_map): Likewise.
	(mips32_to_micromips_reg_l_map): Likewise.
	(mips32_to_micromips_reg_n_map): Likewise.
	(mips32_to_micromips_reg_h_map): New variable.
	(mips32_to_micromips_reg_m_map): Likewise.
	(mips32_to_micromips_reg_q_map): Likewise.
	(micromips_to_32_reg_h_map): New variable.
	(micromips_to_32_reg_i_map): Likewise.
	(micromips_to_32_reg_m_map): Likewise.
	(micromips_to_32_reg_q_map): Likewise.
	(micromips_to_32_reg_b_map): New macro.
	(micromips_to_32_reg_c_map): Likewise.
	(micromips_to_32_reg_d_map): Likewise.
	(micromips_to_32_reg_e_map): Likewise.
	(micromips_to_32_reg_f_map): Likewise.
	(micromips_to_32_reg_g_map): Likewise.
	(micromips_to_32_reg_l_map): Likewise.
	(micromips_to_32_reg_n_map): Likewise.
	(micromips_imm_b_map, micromips_imm_c_map): New macros.
	(RELAX_DELAY_SLOT_16BIT): New macro.
	(RELAX_DELAY_SLOT_SIZE_FIRST): Likewise.
	(RELAX_DELAY_SLOT_SIZE_SECOND): Likewise.
	(RELAX_MICROMIPS_ENCODE, RELAX_MICROMIPS_P): New macros.
	(RELAX_MICROMIPS_TYPE, RELAX_MICROMIPS_AT): Likewise.
	(RELAX_MICROMIPS_U16BIT, RELAX_MICROMIPS_UNCOND): Likewise.
	(RELAX_MICROMIPS_COMPACT, RELAX_MICROMIPS_LINK): Likewise.
	(RELAX_MICROMIPS_RELAX32, RELAX_MICROMIPS_TOOFAR16): Likewise.
	(RELAX_MICROMIPS_MARK_TOOFAR16): Likewise.
	(RELAX_MICROMIPS_CLEAR_TOOFAR16): Likewise.
	(RELAX_MICROMIPS_TOOFAR32): Likewise.
	(RELAX_MICROMIPS_MARK_TOOFAR32): Likewise.
	(RELAX_MICROMIPS_CLEAR_TOOFAR32): Likewise.
	(INSERT_OPERAND, EXTRACT_OPERAND): Handle microMIPS ASE.
	(mips_macro_warning): Add delay_slot_16bit_p, delay_slot_32bit_p,
	fsize and insns.
	(mips_mark_labels): New function.
	(mips16_small, mips16_ext): Remove variables, replacing with...
	(forced_insn_size): ... this.
	(append_insn, mips16_ip): Update accordingly.
	(micromips_insn_length): New function.
	(insn_length): Return the length of microMIPS instructions.
	(mips_record_mips16_mode): Rename to...
	(mips_record_compressed_mode): ... this.  Handle microMIPS ASE.
	(install_insn): Handle microMIPS ASE.
	(reglist_lookup): New function.
	(is_size_valid, is_delay_slot_valid): Likewise.
	(md_begin): Handle microMIPS ASE.
	(md_assemble): Likewise.  Update for append_insn interface change.
	(micromips_reloc_p): New function.
	(got16_reloc_p): Handle microMIPS ASE.
	(hi16_reloc_p): Likewise.
	(lo16_reloc_p): Likewise.
	(jmp_reloc_p): New function.
	(jalr_reloc_p): Likewise.
	(matching_lo_reloc): Handle microMIPS ASE.
	(insn_uses_reg, reg_needs_delay): Likewise.
	(mips_move_labels): Likewise.
	(mips16_mark_labels): Rename to...
	(mips_compressed_mark_labels): ... this.  Handle microMIPS ASE.
	(gpr_mod_mask): New function.
	(gpr_read_mask, gpr_write_mask): Handle microMIPS ASE.
	(fpr_read_mask, fpr_write_mask): Likewise.
	(insns_between, nops_for_vr4130, nops_for_insn): Likewise.
	(fix_loongson2f_nop, fix_loongson2f_jump): Likewise.
	(MICROMIPS_LABEL_CHAR): New macro.
	(micromips_target_label, micromips_target_name): New variables.
	(micromips_label_name, micromips_label_expr): New functions.
	(micromips_label_inc, micromips_add_label): Likewise.
	(mips_label_is_local): Likewise.
	(micromips_map_reloc): Likewise.
	(can_swap_branch_p): Handle microMIPS ASE.
	(append_insn): Add expansionp argument.  Handle microMIPS ASE.
	(start_noreorder, end_noreorder): Handle microMIPS ASE.
	(macro_start, macro_warning, macro_end): Likewise.
	(brk_fmt, cop12_fmt, jalr_fmt, lui_fmt): New variables.
	(mem12_fmt, mfhl_fmt, shft_fmt, trap_fmt): Likewise.
	(BRK_FMT, COP12_FMT, JALR_FMT, LUI_FMT): New macros.
	(MEM12_FMT, MFHL_FMT, SHFT_FMT, TRAP_FMT): Likewise.
	(macro_build): Handle microMIPS ASE.  Update for append_insn
	interface change.
	(mips16_macro_build): Update for append_insn interface change.
	(macro_build_jalr): Handle microMIPS ASE.
	(macro_build_lui): Likewise.  Simplify.
	(load_register): Handle microMIPS ASE.
	(load_address): Likewise.
	(move_register): Likewise.
	(macro_build_branch_likely): New function.
	(macro_build_branch_ccl): Likewise.
	(macro_build_branch_rs): Likewise.
	(macro_build_branch_rsrt): Likewise.
	(macro): Handle microMIPS ASE.
	(validate_micromips_insn): New function.
	(expr_const_in_range): Likewise.
	(mips_ip): Handle microMIPS ASE.
	(options): Add OPTION_MICROMIPS and OPTION_NO_MICROMIPS.
	(md_longopts): Add mmicromips and mno-micromips.
	(md_parse_option): Handle OPTION_MICROMIPS and
	OPTION_NO_MICROMIPS.
	(mips_after_parse_args): Handle microMIPS ASE.
	(md_pcrel_from): Handle microMIPS relocations.
	(mips_force_relocation): Likewise.
	(md_apply_fix): Likewise.
	(mips_align): Handle microMIPS ASE.
	(s_mipsset): Likewise.
	(s_cpload, s_cpsetup, s_cpreturn): Use relocation wrappers.
	(s_dtprel_internal): Likewise.
	(s_gpword, s_gpdword): Likewise.
	(s_insn): Handle microMIPS ASE.
	(s_mips_stab): Likewise.
	(relaxed_micromips_32bit_branch_length): New function.
	(relaxed_micromips_16bit_branch_length): New function.
	(md_estimate_size_before_relax): Handle microMIPS ASE.
	(mips_fix_adjustable): Likewise.
	(tc_gen_reloc): Handle microMIPS relocations.
	(mips_relax_frag): Handle microMIPS ASE.
	(md_convert_frag): Likewise.
	(mips_frob_file_after_relocs): Likewise.
	(mips_elf_final_processing): Likewise.
	(mips_nop_opcode): Likewise.
	(mips_handle_align): Likewise.
	(md_show_usage): Handle microMIPS options.
	* symbols.c (TC_LABEL_IS_LOCAL): New macro.
	(S_IS_LOCAL): Add a TC_LABEL_IS_LOCAL check.

	* doc/as.texinfo (Target MIPS options): Add -mmicromips and
	-mno-micromips.
	(-mmicromips, -mno-micromips): New options.
	* doc/c-mips.texi (-mmicromips, -mno-micromips): New options.
	(MIPS ISA): Document .set micromips and .set nomicromips.
	(MIPS insn): Update for microMIPS support.

gas/testsuite/
2011-02-25  Maciej W. Rozycki  <macro@codesourcery.com>
            Chao-ying Fu  <fu@mips.com>
	    Richard Sandiford  <rdsandiford@googlemail.com>

	* gas/mips/micromips.d: New test.
	* gas/mips/micromips-branch-delay.d: Likewise.
	* gas/mips/micromips-branch-relax.d: Likewise.
	* gas/mips/micromips-branch-relax-pic.d: Likewise.
	* gas/mips/micromips-size-1.d: Likewise.
	* gas/mips/micromips-trap.d: Likewise.
	* gas/mips/micromips.l: New stderr output.
	* gas/mips/micromips-branch-delay.l: Likewise.
	* gas/mips/micromips-branch-relax.l: Likewise.
	* gas/mips/micromips-branch-relax-pic.l: Likewise.
	* gas/mips/micromips-size-0.l: New list test.
	* gas/mips/micromips-size-1.l: New stderr output.
	* gas/mips/micromips.s: New test source.
	* gas/mips/micromips-branch-delay.s: Likewise.
	* gas/mips/micromips-branch-relax.s: Likewise.
	* gas/mips/micromips-size-0.s: Likewise.
	* gas/mips/micromips-size-1.s: Likewise.
	* gas/mips/mips.exp: Run the new tests.

	* gas/mips/dli.s: Use .p2align.
	* gas/mips/elf_ase_micromips.d: New test.
	* gas/mips/elf_ase_micromips-2.d: Likewise.
	* gas/mips/micromips@abs.d: Likewise.
	* gas/mips/micromips@add.d: Likewise.
	* gas/mips/micromips@alnv_ps-swap.d: Likewise.
	* gas/mips/micromips@and.d: Likewise.
	* gas/mips/micromips@beq.d: Likewise.
	* gas/mips/micromips@bge.d: Likewise.
	* gas/mips/micromips@bgeu.d: Likewise.
	* gas/mips/micromips@blt.d: Likewise.
	* gas/mips/micromips@bltu.d: Likewise.
	* gas/mips/micromips@branch-likely.d: Likewise.
	* gas/mips/micromips@branch-misc-1.d: Likewise.
	* gas/mips/micromips@branch-misc-2-64.d: Likewise.
	* gas/mips/micromips@branch-misc-2.d: Likewise.
	* gas/mips/micromips@branch-misc-2pic-64.d: Likewise.
	* gas/mips/micromips@branch-misc-2pic.d: Likewise.
	* gas/mips/micromips@branch-misc-4-64.d: Likewise.
	* gas/mips/micromips@branch-misc-4.d: Likewise.
	* gas/mips/micromips@branch-self.d: Likewise.
	* gas/mips/micromips@cache.d: Likewise.
	* gas/mips/micromips@daddi.d: Likewise.
	* gas/mips/micromips@dli.d: Likewise.
	* gas/mips/micromips@elf-jal.d: Likewise.
	* gas/mips/micromips@elf-rel2.d: Likewise.
	* gas/mips/micromips@elfel-rel2.d: Likewise.
	* gas/mips/micromips@elf-rel4.d: Likewise.
	* gas/mips/micromips@jal-svr4pic.d: Likewise.
	* gas/mips/micromips@jal-svr4pic-noreorder.d: Likewise.
	* gas/mips/micromips@lb-svr4pic-ilocks.d: Likewise.
	* gas/mips/micromips@li.d: Likewise.
	* gas/mips/micromips@loc-swap-dis.d: Likewise.
	* gas/mips/micromips@loc-swap.d: Likewise.
	* gas/mips/micromips@mips1-fp.d: Likewise.
	* gas/mips/micromips@mips32-cp2.d: Likewise.
	* gas/mips/micromips@mips32-imm.d: Likewise.
	* gas/mips/micromips@mips32-sf32.d: Likewise.
	* gas/mips/micromips@mips32.d: Likewise.
	* gas/mips/micromips@mips32r2-cp2.d: Likewise.
	* gas/mips/micromips@mips32r2-fp32.d: Likewise.
	* gas/mips/micromips@mips32r2-sync.d: Likewise.
	* gas/mips/micromips@mips32r2.d: Likewise.
	* gas/mips/micromips@mips4-branch-likely.d: Likewise.
	* gas/mips/micromips@mips4-fp.d: Likewise.
	* gas/mips/micromips@mips4.d: Likewise.
	* gas/mips/micromips@mips5.d: Likewise.
	* gas/mips/micromips@mips64-cp2.d: Likewise.
	* gas/mips/micromips@mips64.d: Likewise.
	* gas/mips/micromips@mips64r2.d: Likewise.
	* gas/mips/micromips@pref.d: Likewise.
	* gas/mips/micromips@relax-at.d: Likewise.
	* gas/mips/micromips@relax.d: Likewise.
	* gas/mips/micromips@rol-hw.d: Likewise.
	* gas/mips/micromips@uld2-eb.d: Likewise.
	* gas/mips/micromips@uld2-el.d: Likewise.
	* gas/mips/micromips@ulh2-eb.d: Likewise.
	* gas/mips/micromips@ulh2-el.d: Likewise.
	* gas/mips/micromips@ulw2-eb-ilocks.d: Likewise.
	* gas/mips/micromips@ulw2-el-ilocks.d: Likewise.
	* gas/mips/cache.d: Likewise.
	* gas/mips/daddi.d: Likewise.
	* gas/mips/mips32-imm.d: Likewise.
	* gas/mips/pref.d: Likewise.
	* gas/mips/elf-rel27.d: Handle microMIPS ASE.
	* gas/mips/l_d.d: Likewise.
	* gas/mips/l_d-n32.d: Likewise.
	* gas/mips/l_d-n64.d: Likewise.
	* gas/mips/ld.d: Likewise.
	* gas/mips/ld-n32.d: Likewise.
	* gas/mips/ld-n64.d: Likewise.
	* gas/mips/s_d.d: Likewise.
	* gas/mips/s_d-n32.d: Likewise.
	* gas/mips/s_d-n64.d: Likewise.
	* gas/mips/sd.d: Likewise.
	* gas/mips/sd-n32.d: Likewise.
	* gas/mips/sd-n64.d: Likewise.
	* gas/mips/mips32.d: Update immediates.
	* gas/mips/micromips@mips32-cp2.s: New test source.
	* gas/mips/micromips@mips32-imm.s: Likewise.
	* gas/mips/micromips@mips32r2-cp2.s: Likewise.
	* gas/mips/micromips@mips64-cp2.s: Likewise.
	* gas/mips/cache.s: Likewise.
	* gas/mips/daddi.s: Likewise.
	* gas/mips/mips32-imm.s: Likewise.
	* gas/mips/elf-rel4.s: Handle microMIPS ASE.
	* gas/mips/lb-pic.s: Likewise.
	* gas/mips/ld.s: Likewise.
	* gas/mips/mips32.s: Likewise.
	* gas/mips/mips.exp: Add the micromips arch.  Exclude mips16e
	from micromips.  Run mips32-imm.

	* gas/mips/jal-mask-11.d: New test.
	* gas/mips/jal-mask-12.d: Likewise.
	* gas/mips/micromips@jal-mask-11.d: Likewise.
	* gas/mips/jal-mask-1.s: Source for the new tests.
	* gas/mips/jal-mask-21.d: New test.
	* gas/mips/jal-mask-22.d: Likewise.
	* gas/mips/micromips@jal-mask-12.d: Likewise.
	* gas/mips/jal-mask-2.s: Source for the new tests.
	* gas/mips/mips.exp: Run the new tests.

	* gas/mips/mips16-e.d: Add --special-syms to `objdump'.
	* gas/mips/tmips16-e.d: Likewise.
	* gas/mips/mipsel16-e.d: Likewise.
	* gas/mips/tmipsel16-e.d: Likewise.

	* gas/mips/and.s: Adjust padding.
	* gas/mips/beq.s: Likewise.
	* gas/mips/bge.s: Likewise.
	* gas/mips/bgeu.s: Likewise.
	* gas/mips/blt.s: Likewise.
	* gas/mips/bltu.s: Likewise.
	* gas/mips/branch-misc-2.s: Likewise.
	* gas/mips/jal.s: Likewise.
	* gas/mips/li.s: Likewise.
	* gas/mips/mips4.s: Likewise.
	* gas/mips/mips4-fp.s: Likewise.
	* gas/mips/relax.s: Likewise.
	* gas/mips/and.d: Update accordingly.
	* gas/mips/elf-jal.d: Likewise.
	* gas/mips/jal.d: Likewise.
	* gas/mips/li.d: Likewise.
	* gas/mips/relax-at.d: Likewise.
	* gas/mips/relax.d: Likewise.

include/elf/
2011-02-25  Chao-ying Fu  <fu@mips.com>
            Maciej W. Rozycki  <macro@codesourcery.com>

	* mips.h (R_MICROMIPS_min): New relocations.
	(R_MICROMIPS_26_S1): Likewise.
	(R_MICROMIPS_HI16, R_MICROMIPS_LO16): Likewise.
	(R_MICROMIPS_GPREL16, R_MICROMIPS_LITERAL): Likewise.
	(R_MICROMIPS_GOT16, R_MICROMIPS_PC7_S1): Likewise.
	(R_MICROMIPS_PC10_S1, R_MICROMIPS_PC16_S1): Likewise.
	(R_MICROMIPS_CALL16, R_MICROMIPS_GOT_DISP): Likewise.
	(R_MICROMIPS_GOT_PAGE, R_MICROMIPS_GOT_OFST): Likewise.
	(R_MICROMIPS_GOT_HI16, R_MICROMIPS_GOT_LO16): Likewise.
	(R_MICROMIPS_SUB, R_MICROMIPS_HIGHER): Likewise.
	(R_MICROMIPS_HIGHEST, R_MICROMIPS_CALL_HI16): Likewise.
	(R_MICROMIPS_CALL_LO16, R_MICROMIPS_SCN_DISP): Likewise.
	(R_MICROMIPS_JALR, R_MICROMIPS_HI0_LO16): Likewise.
	(R_MICROMIPS_TLS_GD, R_MICROMIPS_TLS_LDM): Likewise.
	(R_MICROMIPS_TLS_DTPREL_HI, R_MICROMIPS_TLS_DTPREL_LO): Likewise.
	(R_MICROMIPS_TLS_GOTTPREL): Likewise.
	(R_MICROMIPS_TLS_TPREL_HI16): Likewise.
	(R_MICROMIPS_TLS_TPREL_LO16): Likewise.
	(R_MICROMIPS_GPREL7_S2, R_MICROMIPS_PC23_S2): Likewise.
	(R_MICROMIPS_max): Likewise.
	(EF_MIPS_ARCH_ASE_MICROMIPS): New macro.
	(STO_MIPS_ISA, STO_MIPS_FLAGS): Likewise.
	(ELF_ST_IS_MIPS_PLT, ELF_ST_SET_MIPS_PLT): Likewise.
	(STO_MICROMIPS): Likewise.
	(ELF_ST_IS_MICROMIPS, ELF_ST_SET_MICROMIPS): Likewise.
	(ELF_ST_IS_COMPRESSED): Likewise.
	(STO_MIPS_PLT, STO_MIPS_PIC): Rework.
	(ELF_ST_IS_MIPS_PIC, ELF_ST_SET_MIPS_PIC): Likewise.
	(STO_MIPS16, ELF_ST_IS_MIPS16, ELF_ST_SET_MIPS16): Likewise.

include/opcode/
2011-02-25  Chao-ying Fu  <fu@mips.com>
            Maciej W. Rozycki  <macro@codesourcery.com>

	* mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
	(OP_MASK_STYPE, OP_SH_STYPE): Likewise.
	(OP_MASK_CODE10, OP_SH_CODE10): Likewise.
	(OP_MASK_TRAP, OP_SH_TRAP): Likewise.
	(OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
	(OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
	(OP_MASK_RS3, OP_SH_RS3): Likewise.
	(OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
	(OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
	(OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
	(OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
	(OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
	(OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
	(OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
	(OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
	(OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
	(OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
	(OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
	(OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
	(OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
	(OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
	(INSN_WRITE_GPR_S): New macro.
	(INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
	(INSN2_READ_FPR_D): Likewise.
	(INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
	(INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
	(INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
	(INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
	(INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
	(INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
	(INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
	(INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
	(CPU_MICROMIPS): New macro.
	(M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
	(M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
	(M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
	(M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
	(M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
	(M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
	(M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
	(M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
	(M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
	(M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
	(M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
	(M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
	(M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
	(MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
	(MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
	(MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
	(MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
	(MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
	(MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
	(MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
	(MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
	(MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
	(MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
	(MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
	(MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
	(MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
	(MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
	(MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
	(MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
	(MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
	(MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
	(MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
	(MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
	(MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
	(MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
	(MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
	(MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
	(MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
	(MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
	(MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
	(MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
	(MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
	(MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
	(MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
	(MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
	(MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
	(MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
	(MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
	(MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
	(MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
	(MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
	(MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
	(MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
	(MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
	(MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
	(MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
	(MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
	(MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
	(MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
	(MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
	(MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
	(MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
	(MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
	(MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
	(MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
	(MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
	(MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
	(MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
	(MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
	(MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
	(MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
	(MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
	(MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
	(MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
	(MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
	(MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
	(MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
	(MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
	(MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
	(MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
	(MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
	(MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
	(MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
	(MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
	(MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
	(MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
	(MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
	(MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
	(MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
	(MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
	(MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
	(MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
	(MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
	(MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
	(MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
	(MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
	(MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
	(MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
	(MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
	(MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
	(MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
	(MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
	(MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
	(MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
	(MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
	(micromips_opcodes): New declaration.
	(bfd_micromips_num_opcodes): Likewise.

ld/testsuite/
2011-02-25  Catherine Moore  <clm@codesourcery.com>
            Chao-ying Fu  <fu@mips.com>
            Maciej W. Rozycki  <macro@codesourcery.com>

	* lib/ld-lib.exp (run_dump_test): Support distinct assembler
	flags for the same source named multiple times.
	* ld-mips-elf/jalx-1.s: New test source.
	* ld-mips-elf/jalx-1.d: New test output.
	* ld-mips-elf/jalx-1.ld: New test linker script.
	* ld-mips-elf/jalx-2-main.s: New test source.
	* ld-mips-elf/jalx-2-ex.s: Likewise.
	* ld-mips-elf/jalx-2-printf.s: Likewise.
	* ld-mips-elf/jalx-2.dd: New test output.
	* ld-mips-elf/jalx-2.ld: New test linker script.
	* ld-mips-elf/mips16-and-micromips.d: New test.
	* ld-mips-elf/mips-elf.exp: Run the new tests

opcodes/
2011-02-25  Chao-ying Fu  <fu@mips.com>
            Maciej W. Rozycki  <macro@codesourcery.com>

	* micromips-opc.c: New file.
	* mips-dis.c (micromips_to_32_reg_b_map): New array.
	(micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
	(micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
	(micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
	(micromips_to_32_reg_q_map): Likewise.
	(micromips_imm_b_map, micromips_imm_c_map): Likewise.
	(micromips_ase): New variable.
	(is_micromips): New function.
	(set_default_mips_dis_options): Handle microMIPS ASE.
	(print_insn_micromips): New function.
	(is_compressed_mode_p): Likewise.
	(_print_insn_mips): Handle microMIPS instructions.
	* Makefile.am (CFILES): Add micromips-opc.c.
	* configure.in (bfd_mips_arch): Add micromips-opc.lo.
	* Makefile.in: Regenerate.
	* configure: Regenerate.

	* mips-dis.c (micromips_to_32_reg_h_map): New variable.
	(micromips_to_32_reg_i_map): Likewise.
	(micromips_to_32_reg_m_map): Likewise.
	(micromips_to_32_reg_n_map): New macro.
This commit is contained in:
Richard Sandiford
2011-07-24 14:20:15 +00:00
parent a40bc9dd42
commit df58fc944d
180 changed files with 41118 additions and 3805 deletions
Download Patch File Download Diff File Expand all files Collapse all files

847
opcodes/mips-dis.c
View File

@@ -57,6 +57,91 @@ static const unsigned int mips16_to_32_reg_map[] =
16, 17, 2, 3, 4, 5, 6, 7
};
/* The microMIPS registers with type b. */
#define micromips_to_32_reg_b_map mips16_to_32_reg_map
/* The microMIPS registers with type c. */
#define micromips_to_32_reg_c_map mips16_to_32_reg_map
/* The microMIPS registers with type d. */
#define micromips_to_32_reg_d_map mips16_to_32_reg_map
/* The microMIPS registers with type e. */
#define micromips_to_32_reg_e_map mips16_to_32_reg_map
/* The microMIPS registers with type f. */
#define micromips_to_32_reg_f_map mips16_to_32_reg_map
/* The microMIPS registers with type g. */
#define micromips_to_32_reg_g_map mips16_to_32_reg_map
/* The microMIPS registers with type h. */
static const unsigned int micromips_to_32_reg_h_map[] =
{
5, 5, 6, 4, 4, 4, 4, 4
};
/* The microMIPS registers with type i. */
static const unsigned int micromips_to_32_reg_i_map[] =
{
6, 7, 7, 21, 22, 5, 6, 7
};
/* The microMIPS registers with type j: 32 registers. */
/* The microMIPS registers with type l. */
#define micromips_to_32_reg_l_map mips16_to_32_reg_map
/* The microMIPS registers with type m. */
static const unsigned int micromips_to_32_reg_m_map[] =
{
0, 17, 2, 3, 16, 18, 19, 20
};
/* The microMIPS registers with type n. */
#define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
/* The microMIPS registers with type p: 32 registers. */
/* The microMIPS registers with type q. */
static const unsigned int micromips_to_32_reg_q_map[] =
{
0, 17, 2, 3, 4, 5, 6, 7
};
/* reg type s is $29. */
/* reg type t is the same as the last register. */
/* reg type y is $31. */
/* reg type z is $0. */
/* micromips imm B type. */
static const int micromips_imm_b_map[8] =
{
1, 4, 8, 12, 16, 20, 24, -1
};
/* micromips imm C type. */
static const int micromips_imm_c_map[16] =
{
128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
};
/* micromips imm D type: (-512..511)<<1. */
/* micromips imm E type: (-64..63)<<1. */
/* micromips imm F type: (0..63). */
/* micromips imm G type: (-1..14). */
/* micromips imm H type: (0..15)<<1. */
/* micromips imm I type: (-1..126). */
/* micromips imm J type: (0..15)<<2. */
/* micromips imm L type: (0..15). */
/* micromips imm M type: (1..8). */
/* micromips imm W type: (0..63)<<2. */
/* micromips imm X type: (-8..7). */
/* micromips imm Y type: (-258..-3, 2..257)<<2. */
#define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]]
@@ -537,6 +622,7 @@ const struct mips_arch_choice mips_arch_choices[] =
values. */
static int mips_processor;
static int mips_isa;
static int micromips_ase;
static const char * const *mips_gpr_names;
static const char * const *mips_fpr_names;
static const char * const *mips_cp0_names;
@@ -619,15 +705,28 @@ is_newabi (Elf_Internal_Ehdr *header)
return 0;
}
/* Check if the object has microMIPS ASE code. */
static int
is_micromips (Elf_Internal_Ehdr *header)
{
if ((header->e_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0)
return 1;
return 0;
}
static void
set_default_mips_dis_options (struct disassemble_info *info)
{
const struct mips_arch_choice *chosen_arch;
/* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
and numeric FPR, CP0 register, and HWR names. */
/* Defaults: mipsIII/r3000 (?!), no microMIPS ASE (any compressed code
is MIPS16 ASE) (o)32-style ("oldabi") GPR names, and numeric FPR,
CP0 register, and HWR names. */
mips_isa = ISA_MIPS3;
mips_processor = CPU_R3000;
mips_processor = CPU_R3000;
micromips_ase = 0;
mips_gpr_names = mips_gpr_names_oldabi;
mips_fpr_names = mips_fpr_names_numeric;
mips_cp0_names = mips_cp0_names_numeric;
@@ -636,14 +735,17 @@ set_default_mips_dis_options (struct disassemble_info *info)
mips_hwr_names = mips_hwr_names_numeric;
no_aliases = 0;
/* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
/* Update settings according to the ELF file header flags. */
if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
{
Elf_Internal_Ehdr *header;
header = elf_elfheader (info->section->owner);
/* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
if (is_newabi (header))
mips_gpr_names = mips_gpr_names_newabi;
/* If a microMIPS binary, then don't use MIPS16 bindings. */
micromips_ase = is_micromips (header);
}
/* Set ISA, architecture, and cp0 register names as best we can. */
@@ -2141,6 +2243,723 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
return length;
}
/* Disassemble microMIPS instructions. */
static int
print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info)
{
const fprintf_ftype iprintf = info->fprintf_func;
const struct mips_opcode *op, *opend;
unsigned int lsb, msbd, msb;
void *is = info->stream;
unsigned int regno;
bfd_byte buffer[2];
int lastregno = 0;
int higher;
int length;
int status;
int delta;
int immed;
int insn;
lsb = 0;
info->bytes_per_chunk = 2;
info->display_endian = info->endian;
info->insn_info_valid = 1;
info->branch_delay_insns = 0;
info->data_size = 0;
info->insn_type = dis_nonbranch;
info->target = 0;
info->target2 = 0;
status = (*info->read_memory_func) (memaddr, buffer, 2, info);
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
length = 2;
if (info->endian == BFD_ENDIAN_BIG)
insn = bfd_getb16 (buffer);
else
insn = bfd_getl16 (buffer);
if ((insn & 0xfc00) == 0x7c00)
{
/* This is a 48-bit microMIPS instruction. */
higher = insn;
status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info);
if (status != 0)
{
iprintf (is, "micromips 0x%x", higher);
(*info->memory_error_func) (status, memaddr + 2, info);
return -1;
}
if (info->endian == BFD_ENDIAN_BIG)
insn = bfd_getb16 (buffer);
else
insn = bfd_getl16 (buffer);
higher = (higher << 16) | insn;
status = (*info->read_memory_func) (memaddr + 4, buffer, 2, info);
if (status != 0)
{
iprintf (is, "micromips 0x%x", higher);
(*info->memory_error_func) (status, memaddr + 4, info);
return -1;
}
if (info->endian == BFD_ENDIAN_BIG)
insn = bfd_getb16 (buffer);
else
insn = bfd_getl16 (buffer);
iprintf (is, "0x%x%04x (48-bit insn)", higher, insn);
info->insn_type = dis_noninsn;
return 6;
}
else if ((insn & 0x1c00) == 0x0000 || (insn & 0x1000) == 0x1000)
{
/* This is a 32-bit microMIPS instruction. */
higher = insn;
status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info);
if (status != 0)
{
iprintf (is, "micromips 0x%x", higher);
(*info->memory_error_func) (status, memaddr + 2, info);
return -1;
}
if (info->endian == BFD_ENDIAN_BIG)
insn = bfd_getb16 (buffer);
else
insn = bfd_getl16 (buffer);
insn = insn | (higher << 16);
length += 2;
}
/* FIXME: Should probably use a hash table on the major opcode here. */
#define GET_OP(insn, field) \
(((insn) >> MICROMIPSOP_SH_##field) & MICROMIPSOP_MASK_##field)
opend = micromips_opcodes + bfd_micromips_num_opcodes;
for (op = micromips_opcodes; op < opend; op++)
{
if (op->pinfo != INSN_MACRO
&& !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
&& (insn & op->mask) == op->match
&& ((length == 2 && (op->mask & 0xffff0000) == 0)
|| (length == 4 && (op->mask & 0xffff0000) != 0)))
{
const char *s;
iprintf (is, "%s", op->name);
if (op->args[0] != '\0')
iprintf (is, "\t");
for (s = op->args; *s != '\0'; s++)
{
switch (*s)
{
case ',':
case '(':
case ')':
iprintf (is, "%c", *s);
break;
case '.':
delta = GET_OP (insn, OFFSET10);
if (delta & 0x200)
delta |= ~0x3ff;
iprintf (is, "%d", delta);
break;
case '1':
iprintf (is, "0x%lx", GET_OP (insn, STYPE));
break;
case '<':
iprintf (is, "0x%lx", GET_OP (insn, SHAMT));
break;
case '|':
iprintf (is, "0x%lx", GET_OP (insn, TRAP));
break;
case '~':
delta = GET_OP (insn, OFFSET12);
if (delta & 0x800)
delta |= ~0x7ff;
iprintf (is, "%d", delta);
break;
case 'a':
if (strcmp (op->name, "jalx") == 0)
info->target = (((memaddr + 4) & ~(bfd_vma) 0x0fffffff)
| (GET_OP (insn, TARGET) << 2));
else
info->target = (((memaddr + 4) & ~(bfd_vma) 0x07ffffff)
| ((GET_OP (insn, TARGET)) << 1));
/* For gdb disassembler, force odd address on jalx. */
if (info->flavour == bfd_target_unknown_flavour
&& strcmp (op->name, "jalx") == 0)
info->target |= 1;
(*info->print_address_func) (info->target, info);
break;
case 'b':
case 'r':
case 's':
case 'v':
iprintf (is, "%s", mips_gpr_names[GET_OP (insn, RS)]);
break;
case 'c':
iprintf (is, "0x%lx", GET_OP (insn, CODE));
break;
case 'd':
iprintf (is, "%s", mips_gpr_names[GET_OP (insn, RD)]);
break;
case 'h':
iprintf (is, "0x%lx", GET_OP (insn, PREFX));
break;
case 'i':
case 'u':
iprintf (is, "0x%lx", GET_OP (insn, IMMEDIATE));
break;
case 'j': /* Same as i, but sign-extended. */
case 'o':
delta = (GET_OP (insn, DELTA) ^ 0x8000) - 0x8000;
iprintf (is, "%d", delta);
break;
case 'k':
iprintf (is, "0x%x", GET_OP (insn, CACHE));
break;
case 'n':
{
int s_reg_encode;
immed = GET_OP (insn, RT);
s_reg_encode = immed & 0xf;
if (s_reg_encode != 0)
{
if (s_reg_encode == 1)
iprintf (is, "%s", mips_gpr_names[16]);
else if (s_reg_encode < 9)
iprintf (is, "%s-%s",
mips_gpr_names[16],
mips_gpr_names[15 + s_reg_encode]);
else if (s_reg_encode == 9)
iprintf (is, "%s-%s,%s",
mips_gpr_names[16],
mips_gpr_names[23],
mips_gpr_names[30]);
else
iprintf (is, "UNKNOWN");
}
if (immed & 0x10) /* For ra. */
{
if (s_reg_encode == 0)
iprintf (is, "%s", mips_gpr_names[31]);
else
iprintf (is, ",%s", mips_gpr_names[31]);
}
break;
}
case 'p':
/* Sign-extend the displacement. */
delta = (GET_OP (insn, DELTA) ^ 0x8000) - 0x8000;
info->target = (delta << 1) + memaddr + length;
(*info->print_address_func) (info->target, info);
break;
case 'q':
iprintf (is, "0x%lx", GET_OP (insn, CODE2));
break;
case 't':
case 'w':
iprintf (is, "%s", mips_gpr_names[GET_OP (insn, RT)]);
break;
case 'y':
iprintf (is, "%s", mips_gpr_names[GET_OP (insn, RS3)]);
break;
case 'z':
iprintf (is, "%s", mips_gpr_names[0]);
break;
case 'B':
iprintf (is, "0x%lx", GET_OP (insn, CODE10));
break;
case 'C':
iprintf (is, "0x%lx", GET_OP (insn, COPZ));
break;
case 'D':
iprintf (is, "%s", mips_fpr_names[GET_OP (insn, FD)]);
break;
case 'E':
/* Coprocessor register for lwcN instructions, et al.
Note that there is no load/store cp0 instructions, and
that FPU (cp1) instructions disassemble this field using
'T' format. Therefore, until we gain understanding of
cp2 register names, we can simply print the register
numbers. */
iprintf (is, "$%ld", GET_OP (insn, RT));
break;
case 'G':
/* Coprocessor register for mtcN instructions, et al. Note
that FPU (cp1) instructions disassemble this field using
'S' format. Therefore, we only need to worry about cp0,
cp2, and cp3.
The microMIPS encoding does not have a coprocessor
identifier field as such, so we must work out the
coprocessor number by looking at the opcode. */
switch (insn
& ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT)
| (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)))
{
case 0x000000fc: /* mfc0 */
case 0x000002fc: /* mtc0 */
case 0x580000fc: /* dmfc0 */
case 0x580002fc: /* dmtc0 */
iprintf (is, "%s", mips_cp0_names[GET_OP (insn, RS)]);
break;
default:
iprintf (is, "$%ld", GET_OP (insn, RS));
break;
}
break;
case 'H':
iprintf (is, "%ld", GET_OP (insn, SEL));
break;
case 'K':
iprintf (is, "%s", mips_hwr_names[GET_OP (insn, RS)]);
break;
case 'M':
iprintf (is, "$fcc%ld", GET_OP (insn, CCC));
break;
case 'N':
iprintf (is,
(op->pinfo & (FP_D | FP_S)) != 0
? "$fcc%ld" : "$cc%ld",
GET_OP (insn, BCC));
break;
case 'R':
iprintf (is, "%s", mips_fpr_names[GET_OP (insn, FR)]);
break;
case 'S':
case 'V':
iprintf (is, "%s", mips_fpr_names[GET_OP (insn, FS)]);
break;
case 'T':
iprintf (is, "%s", mips_fpr_names[GET_OP (insn, FT)]);
break;
case '+':
/* Extension character; switch for second char. */
s++;
switch (*s)
{
case 'A':
lsb = GET_OP (insn, EXTLSB);
iprintf (is, "0x%x", lsb);
break;
case 'B':
msb = GET_OP (insn, INSMSB);
iprintf (is, "0x%x", msb - lsb + 1);
break;
case 'C':
case 'H':
msbd = GET_OP (insn, EXTMSBD);
iprintf (is, "0x%x", msbd + 1);
break;
case 'D':
{
const struct mips_cp0sel_name *n;
unsigned int cp0reg, sel;
cp0reg = GET_OP (insn, RS);
sel = GET_OP (insn, SEL);
/* CP0 register including 'sel' code for mtcN
(et al.), to be printed textually if known.
If not known, print both CP0 register name and
sel numerically since CP0 register with sel 0 may
have a name unrelated to register being printed. */
n = lookup_mips_cp0sel_name (mips_cp0sel_names,
mips_cp0sel_names_len,
cp0reg, sel);
if (n != NULL)
iprintf (is, "%s", n->name);
else
iprintf (is, "$%d,%d", cp0reg, sel);
break;
}
case 'E':
lsb = GET_OP (insn, EXTLSB) + 32;
iprintf (is, "0x%x", lsb);
break;
case 'F':
msb = GET_OP (insn, INSMSB) + 32;
iprintf (is, "0x%x", msb - lsb + 1);
break;
case 'G':
msbd = GET_OP (insn, EXTMSBD) + 32;
iprintf (is, "0x%x", msbd + 1);
break;
default:
/* xgettext:c-format */
iprintf (is,
_("# internal disassembler error, "
"unrecognized modifier (+%c)"),
*s);
abort ();
}
break;
case 'm':
/* Extension character; switch for second char. */
s++;
switch (*s)
{
case 'a': /* global pointer. */
iprintf (is, "%s", mips_gpr_names[28]);
break;
case 'b':
regno = micromips_to_32_reg_b_map[GET_OP (insn, MB)];
iprintf (is, "%s", mips_gpr_names[regno]);
break;
case 'c':
regno = micromips_to_32_reg_c_map[GET_OP (insn, MC)];
iprintf (is, "%s", mips_gpr_names[regno]);
break;
case 'd':
regno = micromips_to_32_reg_d_map[GET_OP (insn, MD)];
iprintf (is, "%s", mips_gpr_names[regno]);
break;
case 'e':
regno = micromips_to_32_reg_e_map[GET_OP (insn, ME)];
iprintf (is, "%s", mips_gpr_names[regno]);
break;
case 'f':
/* Save lastregno for "mt" to print out later. */
lastregno = micromips_to_32_reg_f_map[GET_OP (insn, MF)];
iprintf (is, "%s", mips_gpr_names[lastregno]);
break;
case 'g':
regno = micromips_to_32_reg_g_map[GET_OP (insn, MG)];
iprintf (is, "%s", mips_gpr_names[regno]);
break;
case 'h':
regno = micromips_to_32_reg_h_map[GET_OP (insn, MH)];
iprintf (is, "%s", mips_gpr_names[regno]);
break;
case 'i':
regno = micromips_to_32_reg_i_map[GET_OP (insn, MI)];
iprintf (is, "%s", mips_gpr_names[regno]);
break;
case 'j':
iprintf (is, "%s", mips_gpr_names[GET_OP (insn, MJ)]);
break;
case 'l':
regno = micromips_to_32_reg_l_map[GET_OP (insn, ML)];
iprintf (is, "%s", mips_gpr_names[regno]);
break;
case 'm':
regno = micromips_to_32_reg_m_map[GET_OP (insn, MM)];
iprintf (is, "%s", mips_gpr_names[regno]);
break;
case 'n':
regno = micromips_to_32_reg_n_map[GET_OP (insn, MN)];
iprintf (is, "%s", mips_gpr_names[regno]);
break;
case 'p':
/* Save lastregno for "mt" to print out later. */
lastregno = GET_OP (insn, MP);
iprintf (is, "%s", mips_gpr_names[lastregno]);
break;
case 'q':
regno = micromips_to_32_reg_q_map[GET_OP (insn, MQ)];
iprintf (is, "%s", mips_gpr_names[regno]);
break;
case 'r': /* program counter. */
iprintf (is, "$pc");
break;
case 's': /* stack pointer. */
lastregno = 29;
iprintf (is, "%s", mips_gpr_names[29]);
break;
case 't':
iprintf (is, "%s", mips_gpr_names[lastregno]);
break;
case 'z': /* $0. */
iprintf (is, "%s", mips_gpr_names[0]);
break;
case 'A':
/* Sign-extend the immediate. */
immed = ((GET_OP (insn, IMMA) ^ 0x40) - 0x40) << 2;
iprintf (is, "%d", immed);
break;
case 'B':
immed = micromips_imm_b_map[GET_OP (insn, IMMB)];
iprintf (is, "%d", immed);
break;
case 'C':
immed = micromips_imm_c_map[GET_OP (insn, IMMC)];
iprintf (is, "0x%lx", immed);
break;
case 'D':
/* Sign-extend the displacement. */
delta = (GET_OP (insn, IMMD) ^ 0x200) - 0x200;
info->target = (delta << 1) + memaddr + length;
(*info->print_address_func) (info->target, info);
break;
case 'E':
/* Sign-extend the displacement. */
delta = (GET_OP (insn, IMME) ^ 0x40) - 0x40;
info->target = (delta << 1) + memaddr + length;
(*info->print_address_func) (info->target, info);
break;
case 'F':
immed = GET_OP (insn, IMMF);
iprintf (is, "0x%x", immed);
break;
case 'G':
immed = (insn >> MICROMIPSOP_SH_IMMG) + 1;
immed = (immed & MICROMIPSOP_MASK_IMMG) - 1;
iprintf (is, "%d", immed);
break;
case 'H':
immed = GET_OP (insn, IMMH) << 1;
iprintf (is, "%d", immed);
break;
case 'I':
immed = (insn >> MICROMIPSOP_SH_IMMI) + 1;
immed = (immed & MICROMIPSOP_MASK_IMMI) - 1;
iprintf (is, "%d", immed);
break;
case 'J':
immed = GET_OP (insn, IMMJ) << 2;
iprintf (is, "%d", immed);
break;
case 'L':
immed = GET_OP (insn, IMML);
iprintf (is, "%d", immed);
break;
case 'M':
immed = (insn >> MICROMIPSOP_SH_IMMM) - 1;
immed = (immed & MICROMIPSOP_MASK_IMMM) + 1;
iprintf (is, "%d", immed);
break;
case 'N':
immed = GET_OP (insn, IMMN);
if (immed == 0)
iprintf (is, "%s,%s",
mips_gpr_names[16],
mips_gpr_names[31]);
else
iprintf (is, "%s-%s,%s",
mips_gpr_names[16],
mips_gpr_names[16 + immed],
mips_gpr_names[31]);
break;
case 'O':
immed = GET_OP (insn, IMMO);
iprintf (is, "0x%x", immed);
break;
case 'P':
immed = GET_OP (insn, IMMP) << 2;
iprintf (is, "%d", immed);
break;
case 'Q':
/* Sign-extend the immediate. */
immed = (GET_OP (insn, IMMQ) ^ 0x400000) - 0x400000;
immed <<= 2;
iprintf (is, "%d", immed);
break;
case 'U':
immed = GET_OP (insn, IMMU) << 2;
iprintf (is, "%d", immed);
break;
case 'W':
immed = GET_OP (insn, IMMW) << 2;
iprintf (is, "%d", immed);
break;
case 'X':
/* Sign-extend the immediate. */
immed = (GET_OP (insn, IMMX) ^ 0x8) - 0x8;
iprintf (is, "%d", immed);
break;
case 'Y':
/* Sign-extend the immediate. */
immed = (GET_OP (insn, IMMY) ^ 0x100) - 0x100;
if (immed >= -2 && immed <= 1)
immed ^= 0x100;
immed = immed << 2;
iprintf (is, "%d", immed);
break;
default:
/* xgettext:c-format */
iprintf (is,
_("# internal disassembler error, "
"unrecognized modifier (m%c)"),
*s);
abort ();
}
break;
default:
/* xgettext:c-format */
iprintf (is,
_("# internal disassembler error, "
"unrecognized modifier (%c)"),
*s);
abort ();
}
}
/* Figure out instruction type and branch delay information. */
if ((op->pinfo
& (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY)) != 0)
info->branch_delay_insns = 1;
if (((op->pinfo & INSN_UNCOND_BRANCH_DELAY)
| (op->pinfo2 & INSN2_UNCOND_BRANCH)) != 0)
{
if ((op->pinfo & (INSN_WRITE_GPR_31 | INSN_WRITE_GPR_T)) != 0)
info->insn_type = dis_jsr;
else
info->insn_type = dis_branch;
}
else if (((op->pinfo & INSN_COND_BRANCH_DELAY)
| (op->pinfo2 & INSN2_COND_BRANCH)) != 0)
{
if ((op->pinfo & INSN_WRITE_GPR_31) != 0)
info->insn_type = dis_condjsr;
else
info->insn_type = dis_condbranch;
}
else if ((op->pinfo
& (INSN_STORE_MEMORY | INSN_LOAD_MEMORY_DELAY)) != 0)
info->insn_type = dis_dref;
return length;
}
}
#undef GET_OP
iprintf (is, "0x%x", insn);
info->insn_type = dis_noninsn;
return length;
}
/* Return 1 if a symbol associated with the location being disassembled
indicates a compressed (MIPS16 or microMIPS) mode. We iterate over
all the symbols at the address being considered assuming if at least
one of them indicates code compression, then such code has been
genuinely produced here (other symbols could have been derived from
function symbols defined elsewhere or could define data). Otherwise,
return 0. */
static bfd_boolean
is_compressed_mode_p (struct disassemble_info *info)
{
elf_symbol_type *symbol;
int pos;
int i;
for (i = 0; i < info->num_symbols; i++)
{
pos = info->symtab_pos + i;
if (bfd_asymbol_flavour (info->symtab[pos]) != bfd_target_elf_flavour)
continue;
symbol = (elf_symbol_type *) info->symtab[pos];
if ((!micromips_ase
&& ELF_ST_IS_MIPS16 (symbol->internal_elf_sym.st_other))
|| (micromips_ase
&& ELF_ST_IS_MICROMIPS (symbol->internal_elf_sym.st_other)))
return 1;
}
return 0;
}
/* In an environment where we do not know the symbol type of the
instruction we are forced to assume that the low order bit of the
instructions' address may mark it as a mips16 instruction. If we
@@ -2152,26 +2971,30 @@ _print_insn_mips (bfd_vma memaddr,
struct disassemble_info *info,
enum bfd_endian endianness)
{
int (*print_insn_compr) (bfd_vma, struct disassemble_info *);
bfd_byte buffer[INSNLEN];
int status;
set_default_mips_dis_options (info);
parse_mips_dis_options (info->disassembler_options);
if (info->mach == bfd_mach_mips16)
return print_insn_mips16 (memaddr, info);
if (info->mach == bfd_mach_mips_micromips)
return print_insn_micromips (memaddr, info);
print_insn_compr = !micromips_ase ? print_insn_mips16 : print_insn_micromips;
#if 1
/* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
/* FIXME: If odd address, this is CLEARLY a compressed instruction. */
/* Only a few tools will work this way. */
if (memaddr & 0x01)
return print_insn_mips16 (memaddr, info);
return print_insn_compr (memaddr, info);
#endif
#if SYMTAB_AVAILABLE
if (info->mach == bfd_mach_mips16
|| (info->symbols != NULL
&& bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
&& ELF_ST_IS_MIPS16 ((*(elf_symbol_type **) info->symbols)
->internal_elf_sym.st_other)))
return print_insn_mips16 (memaddr, info);
if (is_compressed_mode_p (info))
return print_insn_compr (memaddr, info);
#endif
status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);