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[ARC] Fix handling of ARCv2 H-register class.

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For ARCv2, h-regs are only valid unitl r31.

gas/
2017-11-21  Claudiu Zissulescu <claziss@synopsys.com>

        * testsuite/gas/arc/hregs-err.s: New test.

opcodes/
2017-11-21  Claudiu Zissulescu <claziss@synopsys.com>

        * arc-opc.c (insert_rhv2): Check h-regs range.
This commit is contained in:
claziss
2017-11-22 10:46:45 +01:00
parent 0ad71725d9
commit dc95848142
4 changed files with 21 additions and 0 deletions
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4
gas/ChangeLog
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@@ -1,3 +1,7 @@
2017-11-22 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/hregs-err.s: New test.
2017-11-21 H.J. Lu <hongjiu.lu@intel.com> 2017-11-21 H.J. Lu <hongjiu.lu@intel.com>
PR gas/22464 PR gas/22464

11
gas/testsuite/gas/arc/hregs-err.s Normal file
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@@ -0,0 +1,11 @@
; { dg-do assemble { target arc*-*-* } }
.cpu HS
.text
ld_s r0,[r32,28] ; { dg-error "Error: register must be R1 for instruction 'ld_s'" }
ld_s r0,[r28,28]
ld_s r1,[r32,28] ; { dg-error "Error: register must be GP for instruction 'ld_s'" }
ld_s r2,[r32,28] ; { dg-error "Error: register must be R1 for instruction 'ld_s'" }
ld_s r3,[pcl,0x10]
add_s r0,r0,r32 ; { dg-error "Error: inappropriate arguments for opcode 'add_s'" }
add_s r0,r0,r28
mov_s.ne r0,r32 ; { dg-error "Error: inappropriate arguments for opcode 'mov_s'" }

4
opcodes/ChangeLog
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@@ -1,3 +1,7 @@
2017-11-22 Claudiu Zissulescu <claziss@synopsys.com>
*arc-opc (insert_rhv2): Check h-regs range.
2017-11-21 Claudiu Zissulescu <claziss@synopsys.com> 2017-11-21 Claudiu Zissulescu <claziss@synopsys.com>
* arc-dis.c (print_insn_arc): Pretty print pc-relative offsets. * arc-dis.c (print_insn_arc): Pretty print pc-relative offsets.

2
opcodes/arc-opc.c
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@@ -171,6 +171,8 @@ insert_rhv2 (unsigned long long insn,
{ {
if (value == 0x1E) if (value == 0x1E)
*errmsg = _("register R30 is a limm indicator"); *errmsg = _("register R30 is a limm indicator");
else if (value < 0 || value > 31)
*errmsg = _("register out of range");
return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03); return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03);
} }