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* Updates to tx3904 peripheral simulations for ECC.
Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com> * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE register upon non-zero interrupt event level, clear upon zero event value. * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal by passing zero event value. (*_io_{read,write}_buffer): Endianness fixes. * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes. (deliver_*_tick): Reduce sim event interval to 75% of count interval. * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based serial I/O and timer module at base address 0xFFFF0000.
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@@ -363,6 +363,8 @@ static const OPTION mips_options[] =
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/* start-sanitize-tx3904 */
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#define BOARD_JMR3904 "jmr3904"
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"|" BOARD_JMR3904
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#define BOARD_JMR3904_PAL "jmr3904pal"
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"|" BOARD_JMR3904_PAL
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#define BOARD_JMR3904_DEBUG "jmr3904debug"
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"|" BOARD_JMR3904_DEBUG
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/* end-sanitize-tx3904 */
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@@ -481,6 +483,7 @@ sim_open (kind, cb, abfd, argv)
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#if (WITH_HW)
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if (board != NULL
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&& (strcmp(board, BOARD_JMR3904) == 0 ||
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strcmp(board, BOARD_JMR3904_PAL) == 0 ||
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strcmp(board, BOARD_JMR3904_DEBUG) == 0))
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{
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/* match VIRTUAL memory layout of JMR-TX3904 board */
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@@ -518,6 +521,19 @@ sim_open (kind, cb, abfd, argv)
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sim_hw_parse (sd, "/tx3904tmr@0xfffff100 > int tmr1 /tx3904irc");
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sim_hw_parse (sd, "/tx3904tmr@0xfffff200 > int tmr2 /tx3904irc");
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/* add PAL timer & I/O module */
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if(! strcmp(board, BOARD_JMR3904_PAL))
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{
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/* the device */
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sim_hw_parse (sd, "/pal@0xffff0000");
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sim_hw_parse (sd, "/pal@0xffff0000/reg 0xffff0000 64");
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/* wire up interrupt ports to irc */
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sim_hw_parse (sd, "/pal@0x31000000 > countdown tmr0 /tx3904irc");
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sim_hw_parse (sd, "/pal@0x31000000 > timer tmr1 /tx3904irc");
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sim_hw_parse (sd, "/pal@0x31000000 > int int0 /tx3904irc");
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}
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if(! strcmp(board, BOARD_JMR3904_DEBUG))
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{
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/* -- DEBUG: glue interrupt generators --- */
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