mirror of
https://github.com/bminor/binutils-gdb.git
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Revert "x86/APX: drop AMX-TRANSPOSE promoted insns"
This reverts commit bafcf0823c.
The patch (the removal) was done on the wrong assumption that
it was only the APX-promoted forms which would be dropped
because the APX spec was updated ahead of ISE and there was no
info that AMX-TRANSPOSE would be de-published at that time.
Given the current situation, since we will choose to disable
AMX-TRANSPOSE but not to remove the support in Binutils, we will
also not remove the APX support.
This commit is contained in:
Haochen Jiang
@@ -2303,7 +2303,8 @@ cpu_flags_match (const insn_template *t)
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|| any.bitfield.cpuavx512f || any.bitfield.cpuavx512bw
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|| any.bitfield.cpuavx512dq || any.bitfield.cpuamx_tile
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|| any.bitfield.cpucmpccxadd || any.bitfield.cpuuser_msr
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|| any.bitfield.cpumsr_imm || any.bitfield.cpuamx_movrs))
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|| any.bitfield.cpumsr_imm || any.bitfield.cpuamx_transpose
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|| any.bitfield.cpuamx_movrs))
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{
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/* These checks (verifying that APX_F() was properly used in the
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opcode table entry) make sure there's no need for an "else" to
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@@ -4207,7 +4208,8 @@ install_template (const insn_template *t)
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|| maybe_cpu (t, CpuAVX512F) || maybe_cpu (t, CpuAVX512DQ)
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|| maybe_cpu (t, CpuAVX512BW) || maybe_cpu (t, CpuBMI)
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|| maybe_cpu (t, CpuBMI2) || maybe_cpu (t, CpuUSER_MSR)
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|| maybe_cpu (t, CpuMSR_IMM) || maybe_cpu (t, CpuAMX_MOVRS))
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|| maybe_cpu (t, CpuMSR_IMM) || maybe_cpu (t, CpuAMX_TRANSPOSE)
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|| maybe_cpu (t, CpuAMX_MOVRS))
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&& maybe_cpu (t, CpuAPX_F))
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{
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if (need_evex_encoding (t))
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@@ -139,6 +139,14 @@ Disassembly of section \.text:
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[ ]*[a-f0-9]+:[ ]*62 52 87 00 f7 df[ ]+shrx[ ]+r11,r15,r31
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[ ]*[a-f0-9]+:[ ]*62 5a 87 00 f7 bc 87 23 01 00 00[ ]+shrx[ ]+r15,QWORD PTR \[r31\+rax\*4\+0x123\],r31
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[ ]*[a-f0-9]+:[ ]*62 da 7d 08 49 84 87 23 01 00 00[ ]+sttilecfg[ ]+\[r31\+rax\*4\+0x123\]
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[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz0 tmm6,\[r31\+rax\*8\+0x123\]
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[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rs tmm6,\[r31\+rax\*8\+0x123\]
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[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rst1 tmm6,\[r31\+rax\*8\+0x123\]
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[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz0t1 tmm6,\[r31\+rax\*8\+0x123\]
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[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz1 tmm6,\[r31\+rax\*8\+0x123\]
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[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rs tmm6,\[r31\+rax\*8\+0x123\]
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[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rst1 tmm6,\[r31\+rax\*8\+0x123\]
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[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz1t1 tmm6,\[r31\+rax\*8\+0x123\]
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[ ]*[a-f0-9]+:[ ]*62 da 7f 08 4b b4 87 23 01 00 00[ ]+tileloadd tmm6,\[r31\+rax\*4\+0x123\]
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[ ]*[a-f0-9]+:[ ]*62 b2 7b 08 4a b4 fd 00 00 00 10[ ]+tileloaddrs[ ]+tmm6,\[rbp\+r31\*8\+0x10000000\]
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[ ]*[a-f0-9]+:[ ]*62 fa 7f 08 4a 1c 20[ ]+tileloaddrs[ ]+tmm3,\[r16\+riz\*1\]
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@@ -278,6 +286,14 @@ Disassembly of section \.text:
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[ ]*[a-f0-9]+:[ ]*62 52 87 00 f7 df[ ]+shrx[ ]+r11,r15,r31
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[ ]*[a-f0-9]+:[ ]*62 5a 87 00 f7 bc 87 23 01 00 00[ ]+shrx[ ]+r15,QWORD PTR \[r31\+rax\*4\+0x123\],r31
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[ ]*[a-f0-9]+:[ ]*62 da 7d 08 49 84 87 23 01 00 00[ ]+sttilecfg[ ]+\[r31\+rax\*4\+0x123\]
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[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz0 tmm6,\[r31\+rax\*8\+0x123\]
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[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rs tmm6,\[r31\+rax\*8\+0x123\]
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[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rst1 tmm6,\[r31\+rax\*8\+0x123\]
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[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz0t1 tmm6,\[r31\+rax\*8\+0x123\]
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[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz1 tmm6,\[r31\+rax\*8\+0x123\]
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[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rs tmm6,\[r31\+rax\*8\+0x123\]
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[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rst1 tmm6,\[r31\+rax\*8\+0x123\]
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[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz1t1 tmm6,\[r31\+rax\*8\+0x123\]
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[ ]*[a-f0-9]+:[ ]*62 da 7f 08 4b b4 87 23 01 00 00[ ]+tileloadd tmm6,\[r31\+rax\*4\+0x123\]
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[ ]*[a-f0-9]+:[ ]*62 b2 7b 08 4a b4 fd 00 00 00 10[ ]+tileloaddrs[ ]+tmm6,\[rbp\+r31\*8\+0x10000000\]
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[ ]*[a-f0-9]+:[ ]*62 fa 7f 08 4a 1c 20[ ]+tileloaddrs[ ]+tmm3,\[r16\+riz\*1\]
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@@ -139,6 +139,14 @@ Disassembly of section \.text:
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[ ]*[a-f0-9]+:[ ]*62 52 87 00 f7 df[ ]+shrx[ ]+%r31,%r15,%r11
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[ ]*[a-f0-9]+:[ ]*62 5a 87 00 f7 bc 87 23 01 00 00[ ]+shrx[ ]+%r31,0x123\(%r31,%rax,4\),%r15
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[ ]*[a-f0-9]+:[ ]*62 da 7d 08 49 84 87 23 01 00 00[ ]+sttilecfg[ ]+0x123\(%r31,%rax,4\)
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[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz0[ ]+0x123\(%r31,%rax,8\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rs[ ]+0x123\(%r31,%rax,8\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rst1[ ]+0x123\(%r31,%rax,8\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz0t1[ ]+0x123\(%r31,%rax,8\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz1[ ]+0x123\(%r31,%rax,8\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rs[ ]+0x123\(%r31,%rax,8\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rst1[ ]+0x123\(%r31,%rax,8\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz1t1[ ]+0x123\(%r31,%rax,8\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 da 7f 08 4b b4 87 23 01 00 00[ ]+tileloadd[ ]+0x123\(%r31,%rax,4\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 b2 7b 08 4a b4 fd 00 00 00 10[ ]+tileloaddrs[ ]+0x10000000\(%rbp,%r31,8\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 fa 7f 08 4a 1c 20[ ]+tileloaddrs[ ]+\(%r16,%riz,1\),%tmm3
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@@ -278,6 +286,14 @@ Disassembly of section \.text:
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[ ]*[a-f0-9]+:[ ]*62 52 87 00 f7 df[ ]+shrx[ ]+%r31,%r15,%r11
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[ ]*[a-f0-9]+:[ ]*62 5a 87 00 f7 bc 87 23 01 00 00[ ]+shrx[ ]+%r31,0x123\(%r31,%rax,4\),%r15
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[ ]*[a-f0-9]+:[ ]*62 da 7d 08 49 84 87 23 01 00 00[ ]+sttilecfg[ ]+0x123\(%r31,%rax,4\)
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[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz0[ ]+0x123\(%r31,%rax,8\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rs[ ]+0x123\(%r31,%rax,8\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rst1[ ]+0x123\(%r31,%rax,8\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz0t1[ ]+0x123\(%r31,%rax,8\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz1[ ]+0x123\(%r31,%rax,8\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rs[ ]+0x123\(%r31,%rax,8\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rst1[ ]+0x123\(%r31,%rax,8\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz1t1[ ]+0x123\(%r31,%rax,8\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 da 7f 08 4b b4 87 23 01 00 00[ ]+tileloadd[ ]+0x123\(%r31,%rax,4\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 b2 7b 08 4a b4 fd 00 00 00 10[ ]+tileloaddrs[ ]+0x10000000\(%rbp,%r31,8\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 fa 7f 08 4a 1c 20[ ]+tileloaddrs[ ]+\(%r16,%riz,1\),%tmm3
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@@ -139,6 +139,14 @@ Disassembly of section \.text:
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[ ]*[a-f0-9]+:[ ]*62 52 87 00 f7 df[ ]+shrx[ ]+%r31,%r15,%r11
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[ ]*[a-f0-9]+:[ ]*62 5a 87 00 f7 bc 87 23 01 00 00[ ]+shrx[ ]+%r31,0x123\(%r31,%rax,4\),%r15
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[ ]*[a-f0-9]+:[ ]*62 da 7d 08 49 84 87 23 01 00 00[ ]+sttilecfg[ ]+0x123\(%r31,%rax,4\)
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[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz0[ ]+0x123\(%r31,%rax,8\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rs[ ]+0x123\(%r31,%rax,8\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rst1[ ]+0x123\(%r31,%rax,8\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz0t1[ ]+0x123\(%r31,%rax,8\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz1[ ]+0x123\(%r31,%rax,8\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rs[ ]+0x123\(%r31,%rax,8\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rst1[ ]+0x123\(%r31,%rax,8\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz1t1[ ]+0x123\(%r31,%rax,8\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 da 7f 08 4b b4 87 23 01 00 00[ ]+tileloadd[ ]+0x123\(%r31,%rax,4\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 b2 7b 08 4a b4 fd 00 00 00 10[ ]+tileloaddrs[ ]+0x10000000\(%rbp,%r31,8\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 fa 7f 08 4a 1c 20[ ]+tileloaddrs[ ]+\(%r16,%riz,1\),%tmm3
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@@ -278,6 +286,14 @@ Disassembly of section \.text:
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[ ]*[a-f0-9]+:[ ]*62 52 87 00 f7 df[ ]+shrx[ ]+%r31,%r15,%r11
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[ ]*[a-f0-9]+:[ ]*62 5a 87 00 f7 bc 87 23 01 00 00[ ]+shrx[ ]+%r31,0x123\(%r31,%rax,4\),%r15
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[ ]*[a-f0-9]+:[ ]*62 da 7d 08 49 84 87 23 01 00 00[ ]+sttilecfg[ ]+0x123\(%r31,%rax,4\)
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[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz0[ ]+0x123\(%r31,%rax,8\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rs[ ]+0x123\(%r31,%rax,8\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rst1[ ]+0x123\(%r31,%rax,8\),%tmm6
|
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[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz0t1[ ]+0x123\(%r31,%rax,8\),%tmm6
|
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[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz1[ ]+0x123\(%r31,%rax,8\),%tmm6
|
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[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rs[ ]+0x123\(%r31,%rax,8\),%tmm6
|
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[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rst1[ ]+0x123\(%r31,%rax,8\),%tmm6
|
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[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz1t1[ ]+0x123\(%r31,%rax,8\),%tmm6
|
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[ ]*[a-f0-9]+:[ ]*62 da 7f 08 4b b4 87 23 01 00 00[ ]+tileloadd[ ]+0x123\(%r31,%rax,4\),%tmm6
|
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[ ]*[a-f0-9]+:[ ]*62 b2 7b 08 4a b4 fd 00 00 00 10[ ]+tileloaddrs[ ]+0x10000000\(%rbp,%r31,8\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 fa 7f 08 4a 1c 20[ ]+tileloaddrs[ ]+\(%r16,%riz,1\),%tmm3
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@@ -133,6 +133,14 @@ _start:
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shrx %r31,%r15,%r11
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shrx %r31,0x123(%r31,%rax,4),%r15
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sttilecfg 0x123(%r31,%rax,4)
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t2rpntlvwz0 0x123(%r31,%rax,8),%tmm6
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t2rpntlvwz0rs 0x123(%r31,%rax,8),%tmm6
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t2rpntlvwz0rst1 0x123(%r31,%rax,8),%tmm6
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t2rpntlvwz0t1 0x123(%r31,%rax,8),%tmm6
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t2rpntlvwz1 0x123(%r31,%rax,8),%tmm6
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t2rpntlvwz1rs 0x123(%r31,%rax,8),%tmm6
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t2rpntlvwz1rst1 0x123(%r31,%rax,8),%tmm6
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t2rpntlvwz1t1 0x123(%r31,%rax,8),%tmm6
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tileloadd 0x123(%r31,%rax,4),%tmm6
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tileloaddrs 0x10000000(%rbp, %r31, 8), %tmm6
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tileloaddrs (%r16), %tmm3
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@@ -274,6 +282,14 @@ _start:
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shrx r11,r15,r31
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shrx r15,QWORD PTR [r31+rax*4+0x123],r31
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sttilecfg [r31+rax*4+0x123]
|
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t2rpntlvwz0 tmm6,[r31+rax*8+0x123]
|
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t2rpntlvwz0rs tmm6,[r31+rax*8+0x123]
|
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t2rpntlvwz0rst1 tmm6,[r31+rax*8+0x123]
|
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t2rpntlvwz0t1 tmm6,[r31+rax*8+0x123]
|
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t2rpntlvwz1 tmm6,[r31+rax*8+0x123]
|
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t2rpntlvwz1rs tmm6,[r31+rax*8+0x123]
|
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t2rpntlvwz1rst1 tmm6,[r31+rax*8+0x123]
|
||||
t2rpntlvwz1t1 tmm6,[r31+rax*8+0x123]
|
||||
tileloadd tmm6,[r31+rax*4+0x123]
|
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tileloaddrs tmm6, [rbp+r31*8+0x10000000]
|
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tileloaddrs tmm3, [r16]
|
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|
||||
@@ -416,8 +416,8 @@ static const struct dis386 evex_table[][256] = {
|
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{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ X86_64_TABLE (X86_64_EVEX_0F386D) },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
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{ X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F386E) },
|
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{ X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F386F) },
|
||||
/* 70 */
|
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{ VEX_W_TABLE (EVEX_W_0F3870) },
|
||||
{ "vpshldv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
|
||||
|
||||
@@ -1049,6 +1049,20 @@ process_i386_cpu_flag (FILE *table, char *flag,
|
||||
all[Cpu64].value = 1;
|
||||
|
||||
output_cpu_flags(table, all, ARRAY_SIZE (all), -1, comma, indent, lineno);
|
||||
|
||||
/* For APX_F extension of multiple cpuid enabled insns, we cannot use
|
||||
APX_F(cpuid_A&cpuid_B) in the opcode table, as the result would fail
|
||||
to be parsed. Furthermore, the result also wouldn't be quite valid.
|
||||
However, the assembler's cpu_flags_match() will simply propagate "any"
|
||||
to "all", zapping "any" afterwards altogether. IOW in this situation
|
||||
both masks have "&&" meaning. Set the missing flag here. */
|
||||
if (all[CpuAMX_TRANSPOSE].value && all[CpuAMX_MOVRS].value)
|
||||
{
|
||||
if (!any[CpuAPX_F].value || !any[CpuAMX_MOVRS].value)
|
||||
fail ("%s: %d: internal error: APX_F=%d AMX_MOVRS=%d\n",
|
||||
filename, lineno, any[CpuAPX_F].value, any[CpuAMX_MOVRS].value);
|
||||
any[CpuAMX_TRANSPOSE].value = 1;
|
||||
}
|
||||
}
|
||||
|
||||
output_cpu_flags (table, any, ARRAY_SIZE (any), name != NULL,
|
||||
|
||||
@@ -3247,8 +3247,8 @@ tilezero, 0xf249, AMX_TILE, Modrm|Vex128|Space0F38|VexW0|NoSuf, { RegTMM }
|
||||
|
||||
<loc:opc, $t:0x0, t1:0x1>
|
||||
|
||||
t2rpntlvw<z><loc>, 0x<z:pfx>6e | <loc:opc>, AMX_TRANSPOSE, Sibmem|Vex128|Space0F38|VexW0|NoSuf|ImplicitGroup, { Unspecified|BaseIndex, RegTMM }
|
||||
t2rpntlvw<z>rs<loc>, 0x<z:pfx>f8 | <loc:opc>, AMX_TRANSPOSE&AMX_MOVRS, Sibmem|Vex128|Map5|VexW0|NoSuf|ImplicitGroup, { Unspecified|BaseIndex, RegTMM }
|
||||
t2rpntlvw<z><loc>, 0x<z:pfx>6e | <loc:opc>, APX_F(AMX_TRANSPOSE), Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf|ImplicitGroup, { Unspecified|BaseIndex, RegTMM }
|
||||
t2rpntlvw<z>rs<loc>, 0x<z:pfx>f8 | <loc:opc>, AMX_TRANSPOSE&APX_F(AMX_MOVRS), Sibmem|Vex128|EVex128|Map5|VexW0|NoSuf|ImplicitGroup, { Unspecified|BaseIndex, RegTMM }
|
||||
|
||||
<z>
|
||||
<loc>
|
||||
|
||||
@@ -43226,80 +43226,80 @@ static const insn_template i386_optab[] =
|
||||
0, 0, 0, 1, 0, 0 } } } },
|
||||
{ MN_t2rpntlvwz0, 0x6e | 0x0, 2, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 5, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 0, 1, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
|
||||
0, 0, 0, 1, 0, 1, 0, 4, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0 } },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 1, 0 } },
|
||||
{ { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 0, 0 } } } },
|
||||
{ MN_t2rpntlvwz0t1, 0x6e | 0x1, 2, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 5, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 0, 1, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
|
||||
0, 0, 0, 1, 0, 1, 0, 4, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0 } },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 1, 0 } },
|
||||
{ { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 0, 0 } } } },
|
||||
{ MN_t2rpntlvwz1, 0x6e | 0x0, 2, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 5, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 0, 1, 1, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
|
||||
0, 0, 0, 1, 0, 1, 1, 4, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0 } },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 1, 0 } },
|
||||
{ { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 0, 0 } } } },
|
||||
{ MN_t2rpntlvwz1t1, 0x6e | 0x1, 2, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 5, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 0, 1, 1, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
|
||||
0, 0, 0, 1, 0, 1, 1, 4, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0 } },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 1, 0 } },
|
||||
{ { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 0, 0 } } } },
|
||||
{ MN_t2rpntlvwz0rs, 0xf8 | 0x0, 2, SPACE_MAP5, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 5, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 0, 1, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
|
||||
0, 0, 0, 1, 0, 1, 0, 4, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 },
|
||||
{ { 119, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 119, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0 } },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 1, 0 } },
|
||||
{ { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 0, 0 } } } },
|
||||
{ MN_t2rpntlvwz0rst1, 0xf8 | 0x1, 2, SPACE_MAP5, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 5, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 0, 1, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
|
||||
0, 0, 0, 1, 0, 1, 0, 4, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 },
|
||||
{ { 119, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 119, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0 } },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 1, 0 } },
|
||||
{ { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 0, 0 } } } },
|
||||
{ MN_t2rpntlvwz1rs, 0xf8 | 0x0, 2, SPACE_MAP5, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 5, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 0, 1, 1, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
|
||||
0, 0, 0, 1, 0, 1, 1, 4, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 },
|
||||
{ { 119, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 119, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0 } },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 1, 0 } },
|
||||
{ { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 0, 0 } } } },
|
||||
{ MN_t2rpntlvwz1rst1, 0xf8 | 0x1, 2, SPACE_MAP5, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 5, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 0, 1, 1, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
|
||||
0, 0, 0, 1, 0, 1, 1, 4, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 },
|
||||
{ { 119, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 119, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0 } },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 1, 0 } },
|
||||
{ { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
Reference in New Issue
Block a user