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Arc assembler: Convert nps400 from a machine type to an extension.

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gas	* config/tc-arc.c (check_cpu_feature, md_parse_option):
	Add nps400 option and feature. Add check for nps400
	feature. Refactor existing checks to check subclass before
	feature enablement.
	(md_show_usage): Document flags for NPS-400 and add some other
	undocumented flags.
	(cpu_type): Remove nps400 CPU type entry
	(check_zol): Remove bfd_mach_arc_nps400 case.
	(md_show_usage): Add help on -mcpu=nps400.
	(cpu_types): Add entry for nps400 as arc700 plus nps400 extension
	set.
	* doc/c-arc.texi: Document the -mnps400, -mspfp, -mdpfp, and
	-fpuda flags.  Document -mcpu=nps400.
	* testsuite/gas/arc/nps-400-0.d: Use -mcpu=arc700 -mnps400. Change
	expected flags to match ARC700 instead of NPS400.
	* testsuite/gas/arc/nps-400-1.d: Use -mcpu=arc700 -mnps400.
	* testsuite/gas/arc/nps-400-2.d: Likewise.
	* testsuite/gas/arc/nps-400-3.d: Likewise.
	* testsuite/gas/arc/nps-400-4.d: Likewise.
	* testsuite/gas/arc/nps-400-5.d: Likewise.
	* testsuite/gas/arc/nps-400-6.d: Likewise.
	* testsuite/gas/arc/nps-400-7.d: Likewise.
	* testsuite/gas/arc/textinsn2op01.s: Change opcode of myinsn to
	avoid clash with cbba instruction.
	* testsuite/gas/arc/textinsn2op01.d: Likewise.
	* testsuite/gas/arc/textinsn3op.d: Likewise.
	* testsuite/gas/arc/textinsn3op.s: Likewise.
	* testsuite/gas/arc/nps-400-0.d: Test using NPS-400 using
	-mcpu=nps400 as an alternative to -mcpu=arc700 -mnps400 flags.

binutils* readelf.c (decode_ARC_machine_flags): Remove E_ARC_MACH_NPS400
	case.

ld	* testsuite/ld-arc/nps-1a.d: Use -mcpu=arc700 -mnps400.
	* testsuite/ld-arc/nps-1b.d: Likewise.

include	* opcode/arc.h: Add nps400 extension and instruction
	subclass.
	Remove ARC_OPCODE_NPS400
	* elf/arc.h: Remove E_ARC_MACH_NPS400

opcodes	* arc-dis.c (arc_insn_length): Add comment on instruction length.
	Use same method for determining	instruction length on ARC700 and
	NPS-400.
	(arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
	* arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
	with the NPS400 subclass.
	* arc-opc.c: Likewise.

bfd	* archures.c: Remove bfd_mach_arc_nps400.
	* bfd-in2.h: Likewise.
	* cpu-arc.c (arch_info_struct): Likewise.
	* elf32-arc.c (arc_elf_object_p, arc_elf_final_write_processing):
	Likewise.
This commit is contained in:
Graham Markall
2016-06-21 14:03:08 +01:00
committed by Nick Clifton
parent 782c112285
commit bdd582dbf1
33 changed files with 432 additions and 315 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
opcodes/arc-dis.c
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@@ -557,7 +557,12 @@ arc_insn_length (bfd_byte msb, bfd_byte lsb, struct disassemble_info *info)
switch (info->mach)
{
case bfd_mach_arc_nps400:
case bfd_mach_arc_arc700:
/* The nps400 extension set requires this special casing of the
instruction length calculation. Right now this is not causing any
problems as none of the known extensions overlap in opcode space,
but, if they ever do then we might need to start carrying
information around in the elf about which extensions are in use. */
if (major_opcode == 0xb)
{
bfd_byte minor_opcode = lsb & 0x1f;
@@ -565,7 +570,6 @@ arc_insn_length (bfd_byte msb, bfd_byte lsb, struct disassemble_info *info)
if (minor_opcode < 4)
return 2;
}
case bfd_mach_arc_arc700:
case bfd_mach_arc_arc600:
return (major_opcode > 0xb) ? 2 : 4;
break;
@@ -719,10 +723,6 @@ print_insn_arc (bfd_vma memaddr,
switch (info->mach)
{
case bfd_mach_arc_nps400:
isa_mask = ARC_OPCODE_ARC700 | ARC_OPCODE_NPS400;
break;
case bfd_mach_arc_arc700:
isa_mask = ARC_OPCODE_ARC700;
break;