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* Makefile.in (devices.o): Add dependencies.

Browse Source 
* arch.h,cpu.c,cpu.h,cpuall.h: Regenerate.
	* sem-switch.c,sem.c: Regenerate.
	* mloop.in (execute): Update calls to TRACE_INSN_{INIT,FINI}.
	* cpux.c,cpux.h,modelx.c,semx.c: Regenerate.
	* m32rx.c (m32rx_model_mark_{busy,unbusy}_reg): New functions.
	* mloopx.in (execute): Update calls to TRACE_INSN_{INIT,FINI}.
This commit is contained in:
Doug Evans
1998-05-15 23:46:24 +00:00
parent bcb829fdbd
commit a8981d6751
5 changed files with 711 additions and 386 deletions
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314
sim/m32r/sem-switch.c
View File

@@ -27,118 +27,118 @@ with this program; if not, write to the Free Software Foundation, Inc.,
/* The labels have the case they have because the enum of insn types
is all uppercase and in the non-stdc case the insn symbol is built
into the enum name.
into the enum name. */
The order here must match the order in m32r_decode_vars in decode.c. */
static void *labels[] = {
&& case_sem_INSN_ILLEGAL,
&& case_sem_INSN_ADD,
&& case_sem_INSN_ADD3,
&& case_sem_INSN_AND,
&& case_sem_INSN_AND3,
&& case_sem_INSN_OR,
&& case_sem_INSN_OR3,
&& case_sem_INSN_XOR,
&& case_sem_INSN_XOR3,
&& case_sem_INSN_ADDI,
&& case_sem_INSN_ADDV,
&& case_sem_INSN_ADDV3,
&& case_sem_INSN_ADDX,
&& case_sem_INSN_BC8,
&& case_sem_INSN_BC24,
&& case_sem_INSN_BEQ,
&& case_sem_INSN_BEQZ,
&& case_sem_INSN_BGEZ,
&& case_sem_INSN_BGTZ,
&& case_sem_INSN_BLEZ,
&& case_sem_INSN_BLTZ,
&& case_sem_INSN_BNEZ,
&& case_sem_INSN_BL8,
&& case_sem_INSN_BL24,
&& case_sem_INSN_BNC8,
&& case_sem_INSN_BNC24,
&& case_sem_INSN_BNE,
&& case_sem_INSN_BRA8,
&& case_sem_INSN_BRA24,
&& case_sem_INSN_CMP,
&& case_sem_INSN_CMPI,
&& case_sem_INSN_CMPU,
&& case_sem_INSN_CMPUI,
&& case_sem_INSN_DIV,
&& case_sem_INSN_DIVU,
&& case_sem_INSN_REM,
&& case_sem_INSN_REMU,
&& case_sem_INSN_JL,
&& case_sem_INSN_JMP,
&& case_sem_INSN_LD,
&& case_sem_INSN_LD_D,
&& case_sem_INSN_LDB,
&& case_sem_INSN_LDB_D,
&& case_sem_INSN_LDH,
&& case_sem_INSN_LDH_D,
&& case_sem_INSN_LDUB,
&& case_sem_INSN_LDUB_D,
&& case_sem_INSN_LDUH,
&& case_sem_INSN_LDUH_D,
&& case_sem_INSN_LD_PLUS,
&& case_sem_INSN_LD24,
&& case_sem_INSN_LDI8,
&& case_sem_INSN_LDI16,
&& case_sem_INSN_LOCK,
&& case_sem_INSN_MACHI,
&& case_sem_INSN_MACLO,
&& case_sem_INSN_MACWHI,
&& case_sem_INSN_MACWLO,
&& case_sem_INSN_MUL,
&& case_sem_INSN_MULHI,
&& case_sem_INSN_MULLO,
&& case_sem_INSN_MULWHI,
&& case_sem_INSN_MULWLO,
&& case_sem_INSN_MV,
&& case_sem_INSN_MVFACHI,
&& case_sem_INSN_MVFACLO,
&& case_sem_INSN_MVFACMI,
&& case_sem_INSN_MVFC,
&& case_sem_INSN_MVTACHI,
&& case_sem_INSN_MVTACLO,
&& case_sem_INSN_MVTC,
&& case_sem_INSN_NEG,
&& case_sem_INSN_NOP,
&& case_sem_INSN_NOT,
&& case_sem_INSN_RAC,
&& case_sem_INSN_RACH,
&& case_sem_INSN_RTE,
&& case_sem_INSN_SETH,
&& case_sem_INSN_SLL,
&& case_sem_INSN_SLL3,
&& case_sem_INSN_SLLI,
&& case_sem_INSN_SRA,
&& case_sem_INSN_SRA3,
&& case_sem_INSN_SRAI,
&& case_sem_INSN_SRL,
&& case_sem_INSN_SRL3,
&& case_sem_INSN_SRLI,
&& case_sem_INSN_ST,
&& case_sem_INSN_ST_D,
&& case_sem_INSN_STB,
&& case_sem_INSN_STB_D,
&& case_sem_INSN_STH,
&& case_sem_INSN_STH_D,
&& case_sem_INSN_ST_PLUS,
&& case_sem_INSN_ST_MINUS,
&& case_sem_INSN_SUB,
&& case_sem_INSN_SUBV,
&& case_sem_INSN_SUBX,
&& case_sem_INSN_TRAP,
&& case_sem_INSN_UNLOCK,
0
static struct {
int index;
void *label;
} labels[] = {
{ M32R_XINSN_ILLEGAL, && case_sem_INSN_ILLEGAL },
{ M32R_XINSN_ADD, && case_sem_INSN_ADD },
{ M32R_XINSN_ADD3, && case_sem_INSN_ADD3 },
{ M32R_XINSN_AND, && case_sem_INSN_AND },
{ M32R_XINSN_AND3, && case_sem_INSN_AND3 },
{ M32R_XINSN_OR, && case_sem_INSN_OR },
{ M32R_XINSN_OR3, && case_sem_INSN_OR3 },
{ M32R_XINSN_XOR, && case_sem_INSN_XOR },
{ M32R_XINSN_XOR3, && case_sem_INSN_XOR3 },
{ M32R_XINSN_ADDI, && case_sem_INSN_ADDI },
{ M32R_XINSN_ADDV, && case_sem_INSN_ADDV },
{ M32R_XINSN_ADDV3, && case_sem_INSN_ADDV3 },
{ M32R_XINSN_ADDX, && case_sem_INSN_ADDX },
{ M32R_XINSN_BC8, && case_sem_INSN_BC8 },
{ M32R_XINSN_BC24, && case_sem_INSN_BC24 },
{ M32R_XINSN_BEQ, && case_sem_INSN_BEQ },
{ M32R_XINSN_BEQZ, && case_sem_INSN_BEQZ },
{ M32R_XINSN_BGEZ, && case_sem_INSN_BGEZ },
{ M32R_XINSN_BGTZ, && case_sem_INSN_BGTZ },
{ M32R_XINSN_BLEZ, && case_sem_INSN_BLEZ },
{ M32R_XINSN_BLTZ, && case_sem_INSN_BLTZ },
{ M32R_XINSN_BNEZ, && case_sem_INSN_BNEZ },
{ M32R_XINSN_BL8, && case_sem_INSN_BL8 },
{ M32R_XINSN_BL24, && case_sem_INSN_BL24 },
{ M32R_XINSN_BNC8, && case_sem_INSN_BNC8 },
{ M32R_XINSN_BNC24, && case_sem_INSN_BNC24 },
{ M32R_XINSN_BNE, && case_sem_INSN_BNE },
{ M32R_XINSN_BRA8, && case_sem_INSN_BRA8 },
{ M32R_XINSN_BRA24, && case_sem_INSN_BRA24 },
{ M32R_XINSN_CMP, && case_sem_INSN_CMP },
{ M32R_XINSN_CMPI, && case_sem_INSN_CMPI },
{ M32R_XINSN_CMPU, && case_sem_INSN_CMPU },
{ M32R_XINSN_CMPUI, && case_sem_INSN_CMPUI },
{ M32R_XINSN_DIV, && case_sem_INSN_DIV },
{ M32R_XINSN_DIVU, && case_sem_INSN_DIVU },
{ M32R_XINSN_REM, && case_sem_INSN_REM },
{ M32R_XINSN_REMU, && case_sem_INSN_REMU },
{ M32R_XINSN_JL, && case_sem_INSN_JL },
{ M32R_XINSN_JMP, && case_sem_INSN_JMP },
{ M32R_XINSN_LD, && case_sem_INSN_LD },
{ M32R_XINSN_LD_D, && case_sem_INSN_LD_D },
{ M32R_XINSN_LDB, && case_sem_INSN_LDB },
{ M32R_XINSN_LDB_D, && case_sem_INSN_LDB_D },
{ M32R_XINSN_LDH, && case_sem_INSN_LDH },
{ M32R_XINSN_LDH_D, && case_sem_INSN_LDH_D },
{ M32R_XINSN_LDUB, && case_sem_INSN_LDUB },
{ M32R_XINSN_LDUB_D, && case_sem_INSN_LDUB_D },
{ M32R_XINSN_LDUH, && case_sem_INSN_LDUH },
{ M32R_XINSN_LDUH_D, && case_sem_INSN_LDUH_D },
{ M32R_XINSN_LD_PLUS, && case_sem_INSN_LD_PLUS },
{ M32R_XINSN_LD24, && case_sem_INSN_LD24 },
{ M32R_XINSN_LDI8, && case_sem_INSN_LDI8 },
{ M32R_XINSN_LDI16, && case_sem_INSN_LDI16 },
{ M32R_XINSN_LOCK, && case_sem_INSN_LOCK },
{ M32R_XINSN_MACHI, && case_sem_INSN_MACHI },
{ M32R_XINSN_MACLO, && case_sem_INSN_MACLO },
{ M32R_XINSN_MACWHI, && case_sem_INSN_MACWHI },
{ M32R_XINSN_MACWLO, && case_sem_INSN_MACWLO },
{ M32R_XINSN_MUL, && case_sem_INSN_MUL },
{ M32R_XINSN_MULHI, && case_sem_INSN_MULHI },
{ M32R_XINSN_MULLO, && case_sem_INSN_MULLO },
{ M32R_XINSN_MULWHI, && case_sem_INSN_MULWHI },
{ M32R_XINSN_MULWLO, && case_sem_INSN_MULWLO },
{ M32R_XINSN_MV, && case_sem_INSN_MV },
{ M32R_XINSN_MVFACHI, && case_sem_INSN_MVFACHI },
{ M32R_XINSN_MVFACLO, && case_sem_INSN_MVFACLO },
{ M32R_XINSN_MVFACMI, && case_sem_INSN_MVFACMI },
{ M32R_XINSN_MVFC, && case_sem_INSN_MVFC },
{ M32R_XINSN_MVTACHI, && case_sem_INSN_MVTACHI },
{ M32R_XINSN_MVTACLO, && case_sem_INSN_MVTACLO },
{ M32R_XINSN_MVTC, && case_sem_INSN_MVTC },
{ M32R_XINSN_NEG, && case_sem_INSN_NEG },
{ M32R_XINSN_NOP, && case_sem_INSN_NOP },
{ M32R_XINSN_NOT, && case_sem_INSN_NOT },
{ M32R_XINSN_RAC, && case_sem_INSN_RAC },
{ M32R_XINSN_RACH, && case_sem_INSN_RACH },
{ M32R_XINSN_RTE, && case_sem_INSN_RTE },
{ M32R_XINSN_SETH, && case_sem_INSN_SETH },
{ M32R_XINSN_SLL, && case_sem_INSN_SLL },
{ M32R_XINSN_SLL3, && case_sem_INSN_SLL3 },
{ M32R_XINSN_SLLI, && case_sem_INSN_SLLI },
{ M32R_XINSN_SRA, && case_sem_INSN_SRA },
{ M32R_XINSN_SRA3, && case_sem_INSN_SRA3 },
{ M32R_XINSN_SRAI, && case_sem_INSN_SRAI },
{ M32R_XINSN_SRL, && case_sem_INSN_SRL },
{ M32R_XINSN_SRL3, && case_sem_INSN_SRL3 },
{ M32R_XINSN_SRLI, && case_sem_INSN_SRLI },
{ M32R_XINSN_ST, && case_sem_INSN_ST },
{ M32R_XINSN_ST_D, && case_sem_INSN_ST_D },
{ M32R_XINSN_STB, && case_sem_INSN_STB },
{ M32R_XINSN_STB_D, && case_sem_INSN_STB_D },
{ M32R_XINSN_STH, && case_sem_INSN_STH },
{ M32R_XINSN_STH_D, && case_sem_INSN_STH_D },
{ M32R_XINSN_ST_PLUS, && case_sem_INSN_ST_PLUS },
{ M32R_XINSN_ST_MINUS, && case_sem_INSN_ST_MINUS },
{ M32R_XINSN_SUB, && case_sem_INSN_SUB },
{ M32R_XINSN_SUBV, && case_sem_INSN_SUBV },
{ M32R_XINSN_SUBX, && case_sem_INSN_SUBX },
{ M32R_XINSN_TRAP, && case_sem_INSN_TRAP },
{ M32R_XINSN_UNLOCK, && case_sem_INSN_UNLOCK },
{ 0, 0 }
};
extern DECODE *m32r_decode_vars[];
int i;
for (i = 0; m32r_decode_vars[i] != 0; ++i)
m32r_decode_vars[i]->semantic_lab = labels[i];
for (i = 0; labels[i].label != 0; ++i)
CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
#endif /* DEFINE_LABELS */
@@ -156,7 +156,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#endif
#undef GET_ATTR
#define GET_ATTR(cpu, num, attr) CGEN_INSN_ATTR (abuf->opcode, CGEN_INSN_##attr)
#define GET_ATTR(cpu, num, attr) CGEN_INSN_ATTR (abuf->idesc->opcode, CGEN_INSN_##attr)
{
SEM_ARG sem_arg = sc;
@@ -338,28 +338,28 @@ do {
}
BREAK (sem);
CASE (sem, INSN_BC8) : /* bc $disp8 */
CASE (sem, INSN_BC8) : /* bc.s $disp8 */
{
#define FLD(f) abuf->fields.fmt_bc8.f
new_pc = SEM_NEXT_PC (sem_arg, 2);
if (CPU (h_cond)) {
BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8)));
TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
TRACE_RESULT (current_cpu, "pc", 'x', new_pc);
}
#undef FLD
}
BREAK (sem);
CASE (sem, INSN_BC24) : /* bc $disp24 */
CASE (sem, INSN_BC24) : /* bc.l $disp24 */
{
#define FLD(f) abuf->fields.fmt_bc24.f
new_pc = SEM_NEXT_PC (sem_arg, 4);
if (CPU (h_cond)) {
BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24)));
TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
TRACE_RESULT (current_cpu, "pc", 'x', new_pc);
}
#undef FLD
@@ -373,7 +373,7 @@ if (CPU (h_cond)) {
if (EQSI (* FLD (f_r1), * FLD (f_r2))) {
BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
TRACE_RESULT (current_cpu, "pc", 'x', new_pc);
}
#undef FLD
@@ -387,7 +387,7 @@ if (EQSI (* FLD (f_r1), * FLD (f_r2))) {
if (EQSI (* FLD (f_r2), 0)) {
BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
TRACE_RESULT (current_cpu, "pc", 'x', new_pc);
}
#undef FLD
@@ -401,7 +401,7 @@ if (EQSI (* FLD (f_r2), 0)) {
if (GESI (* FLD (f_r2), 0)) {
BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
TRACE_RESULT (current_cpu, "pc", 'x', new_pc);
}
#undef FLD
@@ -415,7 +415,7 @@ if (GESI (* FLD (f_r2), 0)) {
if (GTSI (* FLD (f_r2), 0)) {
BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
TRACE_RESULT (current_cpu, "pc", 'x', new_pc);
}
#undef FLD
@@ -429,7 +429,7 @@ if (GTSI (* FLD (f_r2), 0)) {
if (LESI (* FLD (f_r2), 0)) {
BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
TRACE_RESULT (current_cpu, "pc", 'x', new_pc);
}
#undef FLD
@@ -443,7 +443,7 @@ if (LESI (* FLD (f_r2), 0)) {
if (LTSI (* FLD (f_r2), 0)) {
BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
TRACE_RESULT (current_cpu, "pc", 'x', new_pc);
}
#undef FLD
@@ -457,67 +457,67 @@ if (LTSI (* FLD (f_r2), 0)) {
if (NESI (* FLD (f_r2), 0)) {
BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
TRACE_RESULT (current_cpu, "pc", 'x', new_pc);
}
#undef FLD
}
BREAK (sem);
CASE (sem, INSN_BL8) : /* bl $disp8 */
CASE (sem, INSN_BL8) : /* bl.s $disp8 */
{
#define FLD(f) abuf->fields.fmt_bl8.f
new_pc = SEM_NEXT_PC (sem_arg, 2);
do {
CPU (h_gr[14]) = ADDSI (ANDSI (CPU (h_pc), -4), 4);
TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14]));
TRACE_RESULT (current_cpu, "gr-14", 'x', CPU (h_gr[14]));
BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8)));
TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
TRACE_RESULT (current_cpu, "pc", 'x', new_pc);
} while (0);
#undef FLD
}
BREAK (sem);
CASE (sem, INSN_BL24) : /* bl $disp24 */
CASE (sem, INSN_BL24) : /* bl.l $disp24 */
{
#define FLD(f) abuf->fields.fmt_bl24.f
new_pc = SEM_NEXT_PC (sem_arg, 4);
do {
CPU (h_gr[14]) = ADDSI (CPU (h_pc), 4);
TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14]));
TRACE_RESULT (current_cpu, "gr-14", 'x', CPU (h_gr[14]));
BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24)));
TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
TRACE_RESULT (current_cpu, "pc", 'x', new_pc);
} while (0);
#undef FLD
}
BREAK (sem);
CASE (sem, INSN_BNC8) : /* bnc $disp8 */
CASE (sem, INSN_BNC8) : /* bnc.s $disp8 */
{
#define FLD(f) abuf->fields.fmt_bc8.f
new_pc = SEM_NEXT_PC (sem_arg, 2);
if (NOTBI (CPU (h_cond))) {
BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8)));
TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
TRACE_RESULT (current_cpu, "pc", 'x', new_pc);
}
#undef FLD
}
BREAK (sem);
CASE (sem, INSN_BNC24) : /* bnc $disp24 */
CASE (sem, INSN_BNC24) : /* bnc.l $disp24 */
{
#define FLD(f) abuf->fields.fmt_bc24.f
new_pc = SEM_NEXT_PC (sem_arg, 4);
if (NOTBI (CPU (h_cond))) {
BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24)));
TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
TRACE_RESULT (current_cpu, "pc", 'x', new_pc);
}
#undef FLD
@@ -531,32 +531,32 @@ if (NOTBI (CPU (h_cond))) {
if (NESI (* FLD (f_r1), * FLD (f_r2))) {
BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
TRACE_RESULT (current_cpu, "pc", 'x', new_pc);
}
#undef FLD
}
BREAK (sem);
CASE (sem, INSN_BRA8) : /* bra $disp8 */
CASE (sem, INSN_BRA8) : /* bra.s $disp8 */
{
#define FLD(f) abuf->fields.fmt_bra8.f
new_pc = SEM_NEXT_PC (sem_arg, 2);
BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8)));
TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
TRACE_RESULT (current_cpu, "pc", 'x', new_pc);
#undef FLD
}
BREAK (sem);
CASE (sem, INSN_BRA24) : /* bra $disp24 */
CASE (sem, INSN_BRA24) : /* bra.l $disp24 */
{
#define FLD(f) abuf->fields.fmt_bra24.f
new_pc = SEM_NEXT_PC (sem_arg, 4);
BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24)));
TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
TRACE_RESULT (current_cpu, "pc", 'x', new_pc);
#undef FLD
}
@@ -676,9 +676,9 @@ do {
temp0 = ADDSI (ANDSI (CPU (h_pc), -4), 4);
temp1 = * FLD (f_r2);
CPU (h_gr[14]) = temp0;
TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14]));
TRACE_RESULT (current_cpu, "gr-14", 'x', CPU (h_gr[14]));
BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, temp1));
TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
TRACE_RESULT (current_cpu, "pc", 'x', new_pc);
} while (0);
#undef FLD
@@ -691,7 +691,7 @@ do {
new_pc = SEM_NEXT_PC (sem_arg, 2);
BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, * FLD (f_r2)));
TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
TRACE_RESULT (current_cpu, "pc", 'x', new_pc);
#undef FLD
}
@@ -848,7 +848,7 @@ do {
}
BREAK (sem);
CASE (sem, INSN_LDI8) : /* ldi $dr,$simm8 */
CASE (sem, INSN_LDI8) : /* ldi8 $dr,$simm8 */
{
#define FLD(f) abuf->fields.fmt_ldi8.f
new_pc = SEM_NEXT_PC (sem_arg, 2);
@@ -860,7 +860,7 @@ do {
}
BREAK (sem);
CASE (sem, INSN_LDI16) : /* ldi $dr,$hash$slo16 */
CASE (sem, INSN_LDI16) : /* ldi16 $dr,$hash$slo16 */
{
#define FLD(f) abuf->fields.fmt_ldi16.f
new_pc = SEM_NEXT_PC (sem_arg, 4);
@@ -879,7 +879,7 @@ do {
do {
CPU (h_lock) = 1;
TRACE_RESULT (current_cpu, "h-lock-0", 'x', CPU (h_lock));
TRACE_RESULT (current_cpu, "lock-0", 'x', CPU (h_lock));
* FLD (f_r1) = GETMEMSI (current_cpu, * FLD (f_r2));
TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
} while (0);
@@ -1177,13 +1177,13 @@ m32r_h_accum_set (current_cpu, SRADI (SLLDI (tmp_tmp1, 7), 7));
do {
CPU (h_sm) = CPU (h_bsm);
TRACE_RESULT (current_cpu, "h-sm-0", 'x', CPU (h_sm));
TRACE_RESULT (current_cpu, "sm-0", 'x', CPU (h_sm));
CPU (h_ie) = CPU (h_bie);
TRACE_RESULT (current_cpu, "h-ie-0", 'x', CPU (h_ie));
TRACE_RESULT (current_cpu, "ie-0", 'x', CPU (h_ie));
CPU (h_cond) = CPU (h_bcond);
TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, ANDSI (CPU (h_bpc), -4)));
TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
TRACE_RESULT (current_cpu, "pc", 'x', new_pc);
} while (0);
#undef FLD
@@ -1316,7 +1316,7 @@ do {
new_pc = SEM_NEXT_PC (sem_arg, 2);
SETMEMSI (current_cpu, * FLD (f_r2), * FLD (f_r1));
TRACE_RESULT (current_cpu, "h-memory-src2", 'x', GETMEMSI (current_cpu, * FLD (f_r2)));
TRACE_RESULT (current_cpu, "memory", 'x', GETMEMSI (current_cpu, * FLD (f_r2)));
#undef FLD
}
@@ -1328,7 +1328,7 @@ SETMEMSI (current_cpu, * FLD (f_r2), * FLD (f_r1));
new_pc = SEM_NEXT_PC (sem_arg, 4);
SETMEMSI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), * FLD (f_r1));
TRACE_RESULT (current_cpu, "h-memory-add-WI-src2-slo16", 'x', GETMEMSI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
TRACE_RESULT (current_cpu, "memory", 'x', GETMEMSI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
#undef FLD
}
@@ -1340,7 +1340,7 @@ SETMEMSI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), * FLD (f_r1));
new_pc = SEM_NEXT_PC (sem_arg, 2);
SETMEMQI (current_cpu, * FLD (f_r2), * FLD (f_r1));
TRACE_RESULT (current_cpu, "h-memory-src2", 'x', GETMEMQI (current_cpu, * FLD (f_r2)));
TRACE_RESULT (current_cpu, "memory", 'x', GETMEMQI (current_cpu, * FLD (f_r2)));
#undef FLD
}
@@ -1352,7 +1352,7 @@ SETMEMQI (current_cpu, * FLD (f_r2), * FLD (f_r1));
new_pc = SEM_NEXT_PC (sem_arg, 4);
SETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), * FLD (f_r1));
TRACE_RESULT (current_cpu, "h-memory-add-WI-src2-slo16", 'x', GETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
TRACE_RESULT (current_cpu, "memory", 'x', GETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
#undef FLD
}
@@ -1364,7 +1364,7 @@ SETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), * FLD (f_r1));
new_pc = SEM_NEXT_PC (sem_arg, 2);
SETMEMHI (current_cpu, * FLD (f_r2), * FLD (f_r1));
TRACE_RESULT (current_cpu, "h-memory-src2", 'x', GETMEMHI (current_cpu, * FLD (f_r2)));
TRACE_RESULT (current_cpu, "memory", 'x', GETMEMHI (current_cpu, * FLD (f_r2)));
#undef FLD
}
@@ -1376,7 +1376,7 @@ SETMEMHI (current_cpu, * FLD (f_r2), * FLD (f_r1));
new_pc = SEM_NEXT_PC (sem_arg, 4);
SETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), * FLD (f_r1));
TRACE_RESULT (current_cpu, "h-memory-add-WI-src2-slo16", 'x', GETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
TRACE_RESULT (current_cpu, "memory", 'x', GETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
#undef FLD
}
@@ -1391,7 +1391,7 @@ do {
SI tmp_new_src2;
tmp_new_src2 = ADDSI (* FLD (f_r2), 4);
SETMEMSI (current_cpu, tmp_new_src2, * FLD (f_r1));
TRACE_RESULT (current_cpu, "h-memory-new-src2", 'x', GETMEMSI (current_cpu, tmp_new_src2));
TRACE_RESULT (current_cpu, "memory", 'x', GETMEMSI (current_cpu, tmp_new_src2));
* FLD (f_r2) = tmp_new_src2;
TRACE_RESULT (current_cpu, "src2", 'x', * FLD (f_r2));
} while (0);
@@ -1409,7 +1409,7 @@ do {
SI tmp_new_src2;
tmp_new_src2 = SUBSI (* FLD (f_r2), 4);
SETMEMSI (current_cpu, tmp_new_src2, * FLD (f_r1));
TRACE_RESULT (current_cpu, "h-memory-new-src2", 'x', GETMEMSI (current_cpu, tmp_new_src2));
TRACE_RESULT (current_cpu, "memory", 'x', GETMEMSI (current_cpu, tmp_new_src2));
* FLD (f_r2) = tmp_new_src2;
TRACE_RESULT (current_cpu, "src2", 'x', * FLD (f_r2));
} while (0);
@@ -1475,11 +1475,11 @@ do {
do {
m32r_h_cr_set (current_cpu, 6, ADDSI (CPU (h_pc), 4));
TRACE_RESULT (current_cpu, "h-cr-6", 'x', m32r_h_cr_get (current_cpu, 6));
TRACE_RESULT (current_cpu, "cr-6", 'x', m32r_h_cr_get (current_cpu, 6));
m32r_h_cr_set (current_cpu, 0, ANDSI (SLLSI (m32r_h_cr_get (current_cpu, 0), 8), 65408));
TRACE_RESULT (current_cpu, "h-cr-0", 'x', m32r_h_cr_get (current_cpu, 0));
TRACE_RESULT (current_cpu, "cr-0", 'x', m32r_h_cr_get (current_cpu, 0));
BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, do_trap (current_cpu, FLD (f_uimm4))));
TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
TRACE_RESULT (current_cpu, "pc", 'x', new_pc);
} while (0);
#undef FLD
@@ -1494,10 +1494,10 @@ m32r_h_cr_set (current_cpu, 0, ANDSI (SLLSI (m32r_h_cr_get (current_cpu, 0), 8),
do {
if (CPU (h_lock)) {
SETMEMSI (current_cpu, * FLD (f_r2), * FLD (f_r1));
TRACE_RESULT (current_cpu, "h-memory-src2", 'x', GETMEMSI (current_cpu, * FLD (f_r2)));
TRACE_RESULT (current_cpu, "memory", 'x', GETMEMSI (current_cpu, * FLD (f_r2)));
}
CPU (h_lock) = 0;
TRACE_RESULT (current_cpu, "h-lock-0", 'x', CPU (h_lock));
TRACE_RESULT (current_cpu, "lock-0", 'x', CPU (h_lock));
} while (0);
#undef FLD