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MIPS16/opcodes: Make the handling of BREAK and SDBBP consistent

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Disassemble the MIPS16 BREAK and SDBBP instruction's immediate operand
in the hexadecimal rather than decimal numeral system and add respective
operandless variants with an implicit 0 operand, making our handling of
these instructions consistent with how we have processed their regular
MIPS and microMIPS counterparts since forever.

	opcodes/
	* mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
	type to hexadecimal.
	(mips16_opcodes): Add operandless "break" and "sdbbp" entries.

	binutils/
	* testsuite/binutils-all/mips/mips16-extend-insn.d: Adjust BREAK
	and SDBBP disassembly.

	gas/
	* testsuite/gas/mips/mips16.d: Adjust BREAK disassembly.
	* testsuite/gas/mips/mips16-64@mips16.d: Likewise.
	* testsuite/gas/mips/mips16-64.d: Likewise.
	* testsuite/gas/mips/mips16-64@mips16-64.d: Likewise.
	* testsuite/gas/mips/mips16-macro.d: Likewise.
	* testsuite/gas/mips/mips16-64@mips16-macro.d: Likewise.
	* testsuite/gas/mips/mips16-sub.d: Likewise.
	* testsuite/gas/mips/mips16-32@mips16-sub.d: Likewise.
This commit is contained in:
Maciej W. Rozycki
2017-05-12 01:09:36 +01:00
parent de428bc533
commit a4f8991513
13 changed files with 85 additions and 61 deletions
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4
binutils/testsuite/binutils-all/mips/mips16-extend-insn.d
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@@ -215,7 +215,7 @@ Disassembly of section \.text:
[0-9a-f]+ <[^>]*> f123 extend 0x123
[0-9a-f]+ <[^>]*> e8c0 jalrc s0
[0-9a-f]+ <[^>]*> f123 extend 0x123
[0-9a-f]+ <[^>]*> e801 sdbbp 0
[0-9a-f]+ <[^>]*> e801 sdbbp
[0-9a-f]+ <[^>]*> f123 extend 0x123
[0-9a-f]+ <[^>]*> e802 slt s0,s0
[0-9a-f]+ <[^>]*> f123 extend 0x123
@@ -223,7 +223,7 @@ Disassembly of section \.text:
[0-9a-f]+ <[^>]*> f123 extend 0x123
[0-9a-f]+ <[^>]*> e804 sllv s0,s0
[0-9a-f]+ <[^>]*> f123 extend 0x123
[0-9a-f]+ <[^>]*> e805 break 0
[0-9a-f]+ <[^>]*> e805 break
[0-9a-f]+ <[^>]*> f123 extend 0x123
[0-9a-f]+ <[^>]*> e806 srlv s0,s0
[0-9a-f]+ <[^>]*> f123 extend 0x123