RISC-V: Support for unlabeled landing pad PLT generation

This patch adds support for generating unlabeled landing pad PLT entries
for the RISC-V architecture. Unlabeled landing pad will place a LPAD
instruction at the PLT entry and PLT header, also PLT header will have
few changes due to the offset is different from the original one.

Ref: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/417

include/opcode/riscv.h

@@ -421,6 +421,7 @@ static inline unsigned int riscv_insn_length (insn_t insn)
 
 /* ABI names for selected x-registers.  */
 
+#define X_ZERO 0
 #define X_RA 1
 #define X_SP 2
 #define X_GP 3