Use bool in include

* bfdlink.h: Replace bfd_boolean with bool throughout.
	* coff/ecoff.h: Likewise.
	* coff/xcoff.h: Likewise.
	* dis-asm.h: Likewise.
	* elf/mmix.h: Likewise.
	* elf/xtensa.h: Likewise.
	* opcode/aarch64.h: Likewise, and FALSE with false, TRUE with true.
	* opcode/arc.h: Likewise.
	* opcode/mips.h: Likewise.
	* opcode/tic6x-opcode-table.h: Likewise.
	* opcode/tic6x.h: Likewise.

include/opcode/aarch64.h

@@ -753,14 +753,14 @@ typedef aarch64_opnd_qualifier_t	\
 	  aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
 
 /* FIXME: improve the efficiency.  */
-static inline bfd_boolean
+static inline bool
 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
 {
   int i;
   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
     if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
-      return FALSE;
-  return TRUE;
+      return false;
+  return true;
 }
 
 /*  Forward declare error reporting type.  */
@@ -819,7 +819,7 @@ struct aarch64_opcode
 
   /* If non-NULL, a function to verify that a given instruction is valid.  */
   enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn,
-			      bfd_vma, bfd_boolean, aarch64_operand_error *,
+			      bfd_vma, bool, aarch64_operand_error *,
 			      struct aarch64_instr_sequence *);
 };
 
@@ -897,13 +897,13 @@ extern aarch64_opcode aarch64_opcode_table[];
 #define C_MAX_ELEM (1U << 1)
 /* Next bit is 2.  */
 
-static inline bfd_boolean
+static inline bool
 alias_opcode_p (const aarch64_opcode *opcode)
 {
   return (opcode->flags & F_ALIAS) != 0;
 }
 
-static inline bfd_boolean
+static inline bool
 opcode_has_alias (const aarch64_opcode *opcode)
 {
   return (opcode->flags & F_HAS_ALIAS) != 0;
@@ -916,13 +916,13 @@ opcode_priority (const aarch64_opcode *opcode)
   return (opcode->flags >> 2) & 0x3;
 }
 
-static inline bfd_boolean
+static inline bool
 pseudo_opcode_p (const aarch64_opcode *opcode)
 {
   return (opcode->flags & F_PSEUDO) != 0lu;
 }
 
-static inline bfd_boolean
+static inline bool
 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
 {
   return ((opcode->flags >> 12) & 0x7) == idx + 1;
@@ -940,7 +940,7 @@ get_opcode_dependent_value (const aarch64_opcode *opcode)
   return (opcode->flags >> 24) & 0x7;
 }
 
-static inline bfd_boolean
+static inline bool
 opcode_has_special_coder (const aarch64_opcode *opcode)
 {
   return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
@@ -974,9 +974,9 @@ typedef struct
 
 extern const aarch64_sys_reg aarch64_sys_regs [];
 extern const aarch64_sys_reg aarch64_pstatefields [];
-extern bfd_boolean aarch64_sys_reg_deprecated_p (const uint32_t);
-extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
-						    const aarch64_sys_reg *);
+extern bool aarch64_sys_reg_deprecated_p (const uint32_t);
+extern bool aarch64_pstatefield_supported_p (const aarch64_feature_set,
+					     const aarch64_sys_reg *);
 
 typedef struct
 {
@@ -985,8 +985,8 @@ typedef struct
   uint32_t flags ;
 } aarch64_sys_ins_reg;
 
-extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
-extern bfd_boolean
+extern bool aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
+extern bool
 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
 				 const char *reg_name, aarch64_insn,
                                  uint32_t, aarch64_feature_set);
@@ -1019,7 +1019,7 @@ enum aarch64_modifier_kind
   AARCH64_MOD_MUL_VL,
 };
 
-bfd_boolean
+bool
 aarch64_extend_operator_p (enum aarch64_modifier_kind);
 
 enum aarch64_modifier_kind
@@ -1242,7 +1242,7 @@ struct aarch64_operand_error
   int index;
   const char *error;
   int data[3];	/* Some data for extra information.  */
-  bfd_boolean non_fatal;
+  bool non_fatal;
 };
 
 /* AArch64 sequence structure used to track instructions with F_SCAN
@@ -1262,7 +1262,7 @@ struct aarch64_instr_sequence
 
 /* Encoding entrypoint.  */
 
-extern bfd_boolean
+extern bool
 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
 		       aarch64_insn *, aarch64_opnd_qualifier_t *,
 		       aarch64_operand_error *, aarch64_instr_sequence *);
@@ -1293,7 +1293,7 @@ extern aarch64_opnd_qualifier_t
 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
 				const aarch64_opnd_qualifier_t, int);
 
-extern bfd_boolean
+extern bool
 aarch64_is_destructive_by_operands (const aarch64_opcode *);
 
 extern int
@@ -1306,7 +1306,7 @@ extern int
 aarch64_zero_register_p (const aarch64_opnd_info *);
 
 extern enum err_type
-aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean,
+aarch64_decode_insn (aarch64_insn, aarch64_inst *, bool,
 		     aarch64_operand_error *);
 
 extern void
@@ -1326,7 +1326,7 @@ aarch64_get_operand_name (enum aarch64_opnd);
 extern const char *
 aarch64_get_operand_desc (enum aarch64_opnd);
 
-extern bfd_boolean
+extern bool
 aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
 
 #ifdef DEBUG_AARCH64

include/opcode/arc.h

@@ -260,8 +260,7 @@ struct arc_operand
      TRUE if this operand type can not actually be extracted from
      this operand (i.e., the instruction does not match).  If the
      operand is valid, *INVALID will not be changed.  */
-  long long int (*extract) (unsigned long long instruction,
-                            bfd_boolean *invalid);
+  long long int (*extract) (unsigned long long instruction, bool *invalid);
 };
 
 /* Elements in the table are retrieved by indexing with values from

include/opcode/mips.h

@@ -519,7 +519,7 @@ struct mips_int_operand
   unsigned int shift;
 
   /* True if the operand should be printed as hex rather than decimal.  */
-  bfd_boolean print_hex;
+  bool print_hex;
 };
 
 /* Uses a lookup table to describe a small integer operand.  */
@@ -531,7 +531,7 @@ struct mips_mapped_int_operand
   const int *int_map;
 
   /* True if the operand should be printed as hex rather than decimal.  */
-  bfd_boolean print_hex;
+  bool print_hex;
 };
 
 /* An operand that encodes the most significant bit position of a bitfield.
@@ -551,7 +551,7 @@ struct mips_msb_operand
 
   /* True if the operand encodes MSB directly, false if it encodes
      MSB - LSB.  */
-  bfd_boolean add_lsb;
+  bool add_lsb;
 
   /* The maximum value of MSB + 1.  */
   unsigned int opsize;
@@ -576,10 +576,10 @@ struct mips_check_prev_operand
 {
   struct mips_operand root;
 
-  bfd_boolean greater_than_ok;
-  bfd_boolean less_than_ok;
-  bfd_boolean equal_ok;
-  bfd_boolean zero_ok;
+  bool greater_than_ok;
+  bool less_than_ok;
+  bool equal_ok;
+  bool zero_ok;
 };
 
 /* Describes an operand that encodes a pair of registers.  */
@@ -619,7 +619,7 @@ struct mips_pcrel_operand
 
 /* Return true if the assembly syntax allows OPERAND to be omitted.  */
 
-static inline bfd_boolean
+static inline bool
 mips_optional_operand_p (const struct mips_operand *operand)
 {
   return (operand->type == OP_OPTIONAL_REG
@@ -758,7 +758,7 @@ struct mips_opcode
 
 /* Return true if MO is an instruction that requires 32-bit encoding.  */
 
-static inline bfd_boolean
+static inline bool
 mips_opcode_32bit_p (const struct mips_opcode *mo)
 {
   return mo->mask >> 16 != 0;
@@ -1387,7 +1387,7 @@ static const unsigned int mips_isa_table[] = {
 
 /* Return true if the given CPU is included in INSN_* mask MASK.  */
 
-static inline bfd_boolean
+static inline bool
 cpu_is_member (int cpu, unsigned int mask)
 {
   switch (cpu)
@@ -1462,7 +1462,7 @@ cpu_is_member (int cpu, unsigned int mask)
 	     || ((mask & INSN_ISA_MASK) == INSN_ISA64R6);
 
     default:
-      return FALSE;
+      return false;
     }
 }
 
@@ -1472,7 +1472,7 @@ cpu_is_member (int cpu, unsigned int mask)
    test, or zero if no CPU specific ISA test is desired.  Return true
    if instruction INSN is available to the given ISA and CPU. */
 
-static inline bfd_boolean
+static inline bool
 opcode_is_member (const struct mips_opcode *insn, int isa, int ase, int cpu)
 {
   if (!cpu_is_member (cpu, insn->exclusions))
@@ -1482,17 +1482,17 @@ opcode_is_member (const struct mips_opcode *insn, int isa, int ase, int cpu)
 	  && (insn->membership & INSN_ISA_MASK) != 0
 	  && ((mips_isa_table[(isa & INSN_ISA_MASK) - 1]
 	       >> ((insn->membership & INSN_ISA_MASK) - 1)) & 1) != 0)
-	return TRUE;
+	return true;
 
       /* Test for ASE compatibility.  */
       if ((ase & insn->ase) != 0)
-	return TRUE;
+	return true;
 
       /* Test for processor-specific extensions.  */
       if (cpu_is_member (cpu, insn->membership))
-	return TRUE;
+	return true;
     }
-  return FALSE;
+  return false;
 }
 
 /* This is a list of macro expanded instructions.
@@ -1941,7 +1941,7 @@ extern int bfd_mips_num_opcodes;
    FP_D (never used)
    */
 
-extern const struct mips_operand *decode_mips16_operand (char, bfd_boolean);
+extern const struct mips_operand *decode_mips16_operand (char, bool);
 extern const struct mips_opcode mips16_opcodes[];
 extern const int bfd_mips16_num_opcodes;
 

include/opcode/tic6x-opcode-table.h

@@ -38,7 +38,7 @@
 #define FIX2(a, b) 2, { a, b }
 #define FIX3(a, b, c) 3, { a, b, c }
 #define FIX4(a, b, c, d) 4, { a, b, c, d }
-#define OP0() 0, { { 0, 0, FALSE, 0, 0, 0, 0 } }
+#define OP0() 0, { { 0, 0, false, 0, 0, 0, 0 } }
 #define OP1(a) 1, { a }
 #define OP2(a, b) 2, { a, b }
 #define OP3(a, b, c) 3, { a, b, c }

include/opcode/tic6x.h

@@ -697,26 +697,26 @@ typedef struct
   unsigned int header;
 
   /* Whether each word uses compact instructions.  */
-  bfd_boolean word_compact[7];
+  bool word_compact[7];
 
   /* Whether loads are protected.  */
-  bfd_boolean prot;
+  bool prot;
 
   /* Whether instructions use the high register set.  */
-  bfd_boolean rs;
+  bool rs;
 
   /* Data size.  */
   unsigned int dsz;
 
   /* Whether compact instructions in the S unit are decoded as
      branches.  */
-  bfd_boolean br;
+  bool br;
 
   /* Whether compact instructions saturate.  */
-  bfd_boolean sat;
+  bool sat;
 
   /* P-bits.  */
-  bfd_boolean p_bits[14];
+  bool p_bits[14];
 } tic6x_fetch_packet_header;
 
 #ifdef __cplusplus