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[OPCODE][ARM]Correct disassembler for cdp/cdp2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2

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opcodes/

2016-02-24  Renlin Li  <renlin.li@arm.com>

	* arm-dis.c (print_insn_coprocessor): Check co-processor number for
	cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.

gas/

2016-02-24  Renlin Li  <renlin.li@arm.com>

	* testsuite/gas/arm/copro.s: Use coprocessor other than 10, 11.
	* testsuite/gas/arm/copro.d: Update.
This commit is contained in:
Renlin Li
2016-02-24 13:48:59 +00:00
parent 30bdf5c82e
commit 8afc7bea40
5 changed files with 36 additions and 2 deletions
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23
opcodes/arm-dis.c
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@@ -3198,6 +3198,7 @@ print_insn_coprocessor (bfd_vma pc,
unsigned long mask;
unsigned long value = 0;
int cond;
int cp_num;
struct arm_private_data *private_data = info->private_data;
arm_feature_set allowed_arches = ARM_ARCH_NONE;
@@ -3236,6 +3237,8 @@ print_insn_coprocessor (bfd_vma pc,
mask = insn->mask;
value = insn->value;
cp_num = (given >> 8) & 0xf;
if (thumb)
{
/* The high 4 bits are 0xe for Arm conditional instructions, and
@@ -3271,6 +3274,26 @@ print_insn_coprocessor (bfd_vma pc,
if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
continue;
if (insn->value == 0xfe000010 /* mcr2 */
|| insn->value == 0xfe100010 /* mrc2 */
|| insn->value == 0xfc100000 /* ldc2 */
|| insn->value == 0xfc000000) /* stc2 */
{
if (cp_num == 10 || cp_num == 11)
is_unpredictable = TRUE;
}
else if (insn->value == 0x0e000000 /* cdp */
|| insn->value == 0xfe000000 /* cdp2 */
|| insn->value == 0x0e000010 /* mcr */
|| insn->value == 0x0e100010 /* mrc */
|| insn->value == 0x0c100000 /* ldc */
|| insn->value == 0x0c000000) /* stc */
{
/* Floating-point instructions. */
if (cp_num == 10 || cp_num == 11)
continue;
}
for (c = insn->assembler; *c; c++)
{
if (*c == '%')