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RISC-V: Add missing disassembler option max

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The flag already exists but it's not been exposed to user.

Signed-off-by: Marek Pikuła <m.pikula@partner.samsung.com>
This commit is contained in:
Marek Pikuła
2025-04-01 17:43:16 +02:00
committed by Nelson Chu
parent e7092c0390
commit 88891208c3
2 changed files with 13 additions and 1 deletions
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8
binutils/doc/binutils.texi
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@@ -2701,6 +2701,14 @@ but the result again may not be as you expect.
For RISC-V, the following options are supported:
@table @code
@item max
Disassemble without checking architecture string. This is a best effort mode, so
for overlapping ISA extensions the first match (possibly incorrect in a given
context) will be used to decode the instruction. It's useful, if the ELF file
doesn't expose ISA string, preventing automatic ISA subset deduction, and the
default fallback ISA string (@code{rv64gc}) doesn't cover all instructions in
the binary.
@item numeric
Print numeric register names, rather than ABI names (e.g., print @code{x2}
instead of @code{sp}).