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Define CPU_INDEX. Initialize.

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For mips_options, iterate over MAX_NR_PROCESSORS when setting options.
This commit is contained in:
Andrew Cagney
1998-03-27 04:25:45 +00:00
parent 227b6b55fa
commit 82ea14fd9d
5 changed files with 62 additions and 25 deletions
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54
sim/mips/interp.c
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@@ -148,6 +148,12 @@ static void ColdReset PARAMS((SIM_DESC sd));
#define MONITOR_BASE (0xBFC00000)
#define MONITOR_SIZE (1 << 11)
#define MEM_SIZE (2 << 20)
/* start-sanitize-sky */
#ifdef TARGET_SKY
#undef MEM_SIZE
#define MEM_SIZE (16 << 20) /* 16 MB */
#endif
/* end-sanitize-sky */
#if defined(TRACE)
static char *tracefile = "trace.din"; /* default filename for trace log */
@@ -177,7 +183,7 @@ mips_option_handler (sd, cpu, opt, arg, is_command)
allow external control of the program points being traced
(i.e. only from main onwards, excluding the run-time setup,
etc.). */
for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
for (cpu_nr = 0; cpu_nr < MAX_NR_PROCESSORS; cpu_nr++)
{
sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
if (arg == NULL)
@@ -571,7 +577,7 @@ sim_write (sd,addr,buffer,size)
int cca;
if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW))
break;
if (sim_core_write_buffer (SD, CPU, sim_core_read_map, buffer + index, paddr, 1) != 1)
if (sim_core_write_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
break;
}
@@ -600,7 +606,7 @@ sim_read (sd,addr,buffer,size)
int cca;
if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW))
break;
if (sim_core_read_buffer (SD, CPU, sim_core_read_map, buffer + index, paddr, 1) != 1)
if (sim_core_read_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
break;
}
@@ -1539,43 +1545,42 @@ load_memory (SIM_DESC sd,
{
case AccessLength_QUADWORD :
{
unsigned_16 val = sim_core_read_aligned_16 (cpu, NULL_CIA,
sim_core_read_map, pAddr);
unsigned_16 val = sim_core_read_aligned_16 (cpu, NULL_CIA, read_map, pAddr);
value1 = VH8_16 (val);
value = VL8_16 (val);
break;
}
case AccessLength_DOUBLEWORD :
value = sim_core_read_aligned_8 (cpu, NULL_CIA,
sim_core_read_map, pAddr);
read_map, pAddr);
break;
case AccessLength_SEPTIBYTE :
value = sim_core_read_misaligned_7 (cpu, NULL_CIA,
sim_core_read_map, pAddr);
read_map, pAddr);
break;
case AccessLength_SEXTIBYTE :
value = sim_core_read_misaligned_6 (cpu, NULL_CIA,
sim_core_read_map, pAddr);
read_map, pAddr);
break;
case AccessLength_QUINTIBYTE :
value = sim_core_read_misaligned_5 (cpu, NULL_CIA,
sim_core_read_map, pAddr);
read_map, pAddr);
break;
case AccessLength_WORD :
value = sim_core_read_aligned_4 (cpu, NULL_CIA,
sim_core_read_map, pAddr);
read_map, pAddr);
break;
case AccessLength_TRIPLEBYTE :
value = sim_core_read_misaligned_3 (cpu, NULL_CIA,
sim_core_read_map, pAddr);
read_map, pAddr);
break;
case AccessLength_HALFWORD :
value = sim_core_read_aligned_2 (cpu, NULL_CIA,
sim_core_read_map, pAddr);
read_map, pAddr);
break;
case AccessLength_BYTE :
value = sim_core_read_aligned_1 (cpu, NULL_CIA,
sim_core_read_map, pAddr);
read_map, pAddr);
break;
default:
abort ();
@@ -1675,41 +1680,40 @@ store_memory (SIM_DESC sd,
case AccessLength_QUADWORD :
{
unsigned_16 val = U16_8 (MemElem1, MemElem);
sim_core_write_aligned_16 (cpu, NULL_CIA,
sim_core_write_map, pAddr, val);
sim_core_write_aligned_16 (cpu, NULL_CIA, write_map, pAddr, val);
break;
}
case AccessLength_DOUBLEWORD :
sim_core_write_aligned_8 (cpu, NULL_CIA,
sim_core_write_map, pAddr, MemElem);
write_map, pAddr, MemElem);
break;
case AccessLength_SEPTIBYTE :
sim_core_write_misaligned_7 (cpu, NULL_CIA,
sim_core_write_map, pAddr, MemElem);
write_map, pAddr, MemElem);
break;
case AccessLength_SEXTIBYTE :
sim_core_write_misaligned_6 (cpu, NULL_CIA,
sim_core_write_map, pAddr, MemElem);
write_map, pAddr, MemElem);
break;
case AccessLength_QUINTIBYTE :
sim_core_write_misaligned_5 (cpu, NULL_CIA,
sim_core_write_map, pAddr, MemElem);
write_map, pAddr, MemElem);
break;
case AccessLength_WORD :
sim_core_write_aligned_4 (cpu, NULL_CIA,
sim_core_write_map, pAddr, MemElem);
write_map, pAddr, MemElem);
break;
case AccessLength_TRIPLEBYTE :
sim_core_write_misaligned_3 (cpu, NULL_CIA,
sim_core_write_map, pAddr, MemElem);
write_map, pAddr, MemElem);
break;
case AccessLength_HALFWORD :
sim_core_write_aligned_2 (cpu, NULL_CIA,
sim_core_write_map, pAddr, MemElem);
write_map, pAddr, MemElem);
break;
case AccessLength_BYTE :
sim_core_write_aligned_1 (cpu, NULL_CIA,
sim_core_write_map, pAddr, MemElem);
write_map, pAddr, MemElem);
break;
default:
abort ();
@@ -2928,6 +2932,7 @@ SquareRoot(op,fmt)
return(result);
}
#if 0
uword64
Max (uword64 op1,
uword64 op2,
@@ -2995,7 +3000,9 @@ Max (uword64 op1,
return(result);
}
#endif
#if 0
uword64
Min (uword64 op1,
uword64 op2,
@@ -3063,6 +3070,7 @@ Min (uword64 op1,
return(result);
}
#endif
uword64
convert (SIM_DESC sd,