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aarch64: Add support for FEAT_MTETC

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This patch adds two new DC operations:

   *gbva
   *zgbva
This commit is contained in:
Richard Ball
2026-01-16 22:16:40 +00:00
parent fcdde313c9
commit 7ae2329129
8 changed files with 32 additions and 0 deletions
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1
gas/config/tc-aarch64.c
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@@ -11011,6 +11011,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"f16mm", AARCH64_FEATURE (F16MM), AARCH64_FEATURES (2, SIMD, F16)}, {"f16mm", AARCH64_FEATURE (F16MM), AARCH64_FEATURES (2, SIMD, F16)},
{"sve-b16mm", AARCH64_FEATURE (SVE_B16MM), AARCH64_FEATURE (SVE)}, {"sve-b16mm", AARCH64_FEATURE (SVE_B16MM), AARCH64_FEATURE (SVE)},
{"mpamv2", AARCH64_FEATURE (MPAMv2), AARCH64_NO_FEATURES}, {"mpamv2", AARCH64_FEATURE (MPAMv2), AARCH64_NO_FEATURES},
{"mtetc", AARCH64_FEATURE (MTETC), AARCH64_FEATURE (MEMTAG)},
{NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES}, {NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
}; };

2
gas/doc/c-aarch64.texi
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@@ -259,6 +259,8 @@ automatically cause those extensions to be disabled.
@tab Enable the Lookup Table (LUT) extension. @tab Enable the Lookup Table (LUT) extension.
@item @code{memtag} @tab @item @code{memtag} @tab
@tab Enable Armv8.5-A Memory Tagging Extensions. @tab Enable Armv8.5-A Memory Tagging Extensions.
@item @code{mtetc} @tab @code{memtag}
@tab Enable Data cache tag block operations.
@item @code{mops} @tab @item @code{mops} @tab
@tab Enable Armv8.8-A memcpy and memset acceleration instructions @tab Enable Armv8.8-A memcpy and memset acceleration instructions
@item @code{mpamv2} @tab @item @code{mpamv2} @tab

4
gas/testsuite/gas/aarch64/mtetc-invalid.d Normal file
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@@ -0,0 +1,4 @@
#name: FEAT_MTETC dc instructions without +mtetc.
#as: -march=armv8-a
#source: mtetc.s
#error_output: mtetc-invalid.l

5
gas/testsuite/gas/aarch64/mtetc-invalid.l Normal file
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@@ -0,0 +1,5 @@
.*: Assembler messages:
.*: Error: selected processor does not support system register name 'gbva'
.*: Error: selected processor does not support system register name 'gbva'
.*: Error: selected processor does not support system register name 'zgbva'
.*: Error: selected processor does not support system register name 'zgbva'

12
gas/testsuite/gas/aarch64/mtetc.d Normal file
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@@ -0,0 +1,12 @@
#as: -march=armv8-a+mtetc
#objdump: -dr
[^:]+: file format .*
Disassembly of section \.text:
[^:]+:
.*: d50b74e0 dc gbva, x0
.*: d50b74ff dc gbva, xzr
.*: d50b74a0 dc zgbva, x0
.*: d50b74bf dc zgbva, xzr

4
gas/testsuite/gas/aarch64/mtetc.s Normal file
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@@ -0,0 +1,4 @@
dc gbva, x0
dc gbva, xzr
dc zgbva, x0
dc zgbva, xzr

2
include/opcode/aarch64.h
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@@ -285,6 +285,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_TEV, AARCH64_FEATURE_TEV,
/* MPAMv2. */ /* MPAMv2. */
AARCH64_FEATURE_MPAMv2, AARCH64_FEATURE_MPAMv2,
/* MTETC. */
AARCH64_FEATURE_MTETC,
/* Virtual features. These are used to gate instructions that are enabled /* Virtual features. These are used to gate instructions that are enabled
by either of two (or more) sets of command line flags. */ by either of two (or more) sets of command line flags. */

2
opcodes/aarch64-opc.c
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@@ -5312,6 +5312,8 @@ const aarch64_sys_ins_reg aarch64_sys_regs_dc[] =
{ "zva", CPENS (3, C7, C4, 1), F_HASXT, AARCH64_NO_FEATURES }, { "zva", CPENS (3, C7, C4, 1), F_HASXT, AARCH64_NO_FEATURES },
{ "gva", CPENS (3, C7, C4, 3), F_HASXT, AARCH64_FEATURE (MEMTAG) }, { "gva", CPENS (3, C7, C4, 3), F_HASXT, AARCH64_FEATURE (MEMTAG) },
{ "gzva", CPENS (3, C7, C4, 4), F_HASXT, AARCH64_FEATURE (MEMTAG) }, { "gzva", CPENS (3, C7, C4, 4), F_HASXT, AARCH64_FEATURE (MEMTAG) },
{ "zgbva", CPENS (3, C7, C4, 5), F_HASXT, AARCH64_FEATURE (MTETC) },
{ "gbva", CPENS (3, C7, C4, 7), F_HASXT, AARCH64_FEATURE (MTETC) },
{ "ivac", CPENS (0, C7, C6, 1), F_HASXT, AARCH64_NO_FEATURES }, { "ivac", CPENS (0, C7, C6, 1), F_HASXT, AARCH64_NO_FEATURES },
{ "igvac", CPENS (0, C7, C6, 3), F_HASXT, AARCH64_FEATURE (MEMTAG) }, { "igvac", CPENS (0, C7, C6, 3), F_HASXT, AARCH64_FEATURE (MEMTAG) },
{ "igsw", CPENS (0, C7, C6, 4), F_HASXT, AARCH64_FEATURE (MEMTAG) }, { "igsw", CPENS (0, C7, C6, 4), F_HASXT, AARCH64_FEATURE (MEMTAG) },