aarch64: Add support for FEAT_MTETC

This patch adds two new DC operations:

   *gbva
   *zgbva
This commit is contained in:
Richard Ball
2026-01-16 22:16:40 +00:00
parent fcdde313c9
commit 7ae2329129
8 changed files with 32 additions and 0 deletions

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@@ -11011,6 +11011,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"f16mm", AARCH64_FEATURE (F16MM), AARCH64_FEATURES (2, SIMD, F16)},
{"sve-b16mm", AARCH64_FEATURE (SVE_B16MM), AARCH64_FEATURE (SVE)},
{"mpamv2", AARCH64_FEATURE (MPAMv2), AARCH64_NO_FEATURES},
{"mtetc", AARCH64_FEATURE (MTETC), AARCH64_FEATURE (MEMTAG)},
{NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
};

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@@ -259,6 +259,8 @@ automatically cause those extensions to be disabled.
@tab Enable the Lookup Table (LUT) extension.
@item @code{memtag} @tab
@tab Enable Armv8.5-A Memory Tagging Extensions.
@item @code{mtetc} @tab @code{memtag}
@tab Enable Data cache tag block operations.
@item @code{mops} @tab
@tab Enable Armv8.8-A memcpy and memset acceleration instructions
@item @code{mpamv2} @tab

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@@ -0,0 +1,4 @@
#name: FEAT_MTETC dc instructions without +mtetc.
#as: -march=armv8-a
#source: mtetc.s
#error_output: mtetc-invalid.l

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@@ -0,0 +1,5 @@
.*: Assembler messages:
.*: Error: selected processor does not support system register name 'gbva'
.*: Error: selected processor does not support system register name 'gbva'
.*: Error: selected processor does not support system register name 'zgbva'
.*: Error: selected processor does not support system register name 'zgbva'

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@@ -0,0 +1,12 @@
#as: -march=armv8-a+mtetc
#objdump: -dr
[^:]+: file format .*
Disassembly of section \.text:
[^:]+:
.*: d50b74e0 dc gbva, x0
.*: d50b74ff dc gbva, xzr
.*: d50b74a0 dc zgbva, x0
.*: d50b74bf dc zgbva, xzr

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@@ -0,0 +1,4 @@
dc gbva, x0
dc gbva, xzr
dc zgbva, x0
dc zgbva, xzr