x86: don't constrain %axl/%cxl

They can be used like their %al/%cl counterparts everywhere else;
there's no apparent reason why they shouldn't be usable as accumulator /
shift count respectively. Enforcing such a restriction only makes
writing heavily macro-ized code more cumbersome.

gas/config/tc-i386.c

@@ -7493,6 +7493,8 @@ i386_assemble (char *line)
   /* Update operand types and check extended states.  */
   for (j = 0; j < i.operands; j++)
     {
+      enum operand_class class = i.types[j].bitfield.class;
+
       i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
       switch (i.tm.operand_types[j].bitfield.class)
 	{
@@ -7517,6 +7519,9 @@ i386_assemble (char *line)
 	  else if (i.tm.operand_types[j].bitfield.xmmword)
 	    i.xstate |= xstate_xmm;
 	  break;
+	case ClassNone:
+	  i.types[j].bitfield.class = class;
+	  break;
 	}
     }
 

gas/testsuite/gas/i386/x86-64-reg-bad.l

@@ -1,21 +0,0 @@
-.*: Assembler messages:
-.*:6: Error: .* mismatch for `div'
-.*:7: Error: .* mismatch for `in'
-.*:8: Error: .* mismatch for `lods'
-.*:9: Error: .* mismatch for `movabs'
-.*:10: Error: .* mismatch for `shl'
-GAS LISTING .*
-
-
-[ 	]*[1-9][0-9]*[ 	]+\# Check %axl / %cxl aren't permitted as accumulator / shift count
-[ 	]*[1-9][0-9]*[ 	]+
-[ 	]*[1-9][0-9]*[ 	]+\.text
-[ 	]*[1-9][0-9]*[ 	]+reg:
-[ 	]*[1-9][0-9]*[ 	]+\?* 4080C001[ 	]+add	\$1, %axl
-[ 	]*[1-9][0-9]*[ 	]+div	%bl, %axl
-[ 	]*[1-9][0-9]*[ 	]+in	%dx, %axl
-[ 	]*[1-9][0-9]*[ 	]+lods	\(%rsi\), %axl
-[ 	]*[1-9][0-9]*[ 	]+movabs	-1, %axl
-[ 	]*[1-9][0-9]*[ 	]+shl	%cxl, %eax
-[ 	]*[1-9][0-9]*[ 	]+\?* 40F6C001[ 	]+test	\$1, %axl
-#pass

gas/testsuite/gas/i386/x86-64-reg-bad.s

@@ -1,11 +0,0 @@
-# Check %axl / %cxl aren't permitted as accumulator / shift count
-
-	.text
-reg:
-	add	$1, %axl
-	div	%bl, %axl
-	in	%dx, %axl
-	lods	(%rsi), %axl
-	movabs	-1, %axl
-	shl	%cxl, %eax
-	test	$1, %axl

gas/testsuite/gas/i386/x86-64-reg-intel.d

@@ -26,7 +26,7 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	0f 73 f6 02          	psllq  mm6,0x2
 [ 	]*[a-f0-9]+:	66 41 0f 73 f2 02    	psllq  xmm10,0x2
 [ 	]*[a-f0-9]+:	66 41 0f 73 fa 02    	pslldq xmm10,0x2
-[ 	]*[a-f0-9]+:	40 80 c0 01[ 	]+rex add al,0x1
+[ 	]*[a-f0-9]+:	40 04 01[ 	]+rex add al,0x1
 [ 	]*[a-f0-9]+:	40 80 c1 01[ 	]+rex add cl,0x1
 [ 	]*[a-f0-9]+:	40 80 c2 01[ 	]+rex add dl,0x1
 [ 	]*[a-f0-9]+:	40 80 c3 01[ 	]+rex add bl,0x1
@@ -34,6 +34,9 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	40 80 c5 01[ 	]+add    bpl,0x1
 [ 	]*[a-f0-9]+:	40 80 c6 01[ 	]+add    sil,0x1
 [ 	]*[a-f0-9]+:	40 80 c7 01[ 	]+add    dil,0x1
+[ 	]*[a-f0-9]+:	40 e4 00[ 	]+rex in al,0x0
+[ 	]*[a-f0-9]+:	40 e6 00[ 	]+rex out 0x0,al
+[ 	]*[a-f0-9]+:	40 d3 e0[ 	]+rex shl eax,cl
 [ 	]*[a-f0-9]+:	0f 71 d6 02          	psrlw  mm6,0x2
 [ 	]*[a-f0-9]+:	66 0f 71 d2 02       	psrlw  xmm2,0x2
 [ 	]*[a-f0-9]+:	0f 71 e6 02          	psraw  mm6,0x2

gas/testsuite/gas/i386/x86-64-reg.d

@@ -25,7 +25,7 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	0f 73 f6 02          	psllq  \$0x2,%mm6
 [ 	]*[a-f0-9]+:	66 41 0f 73 f2 02    	psllq  \$0x2,%xmm10
 [ 	]*[a-f0-9]+:	66 41 0f 73 fa 02    	pslldq \$0x2,%xmm10
-[ 	]*[a-f0-9]+:	40 80 c0 01[ 	]+rex add \$0x1,%al
+[ 	]*[a-f0-9]+:	40 04 01[ 	]+rex add \$0x1,%al
 [ 	]*[a-f0-9]+:	40 80 c1 01[ 	]+rex add \$0x1,%cl
 [ 	]*[a-f0-9]+:	40 80 c2 01[ 	]+rex add \$0x1,%dl
 [ 	]*[a-f0-9]+:	40 80 c3 01[ 	]+rex add \$0x1,%bl
@@ -33,6 +33,9 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	40 80 c5 01[ 	]+add    \$0x1,%bpl
 [ 	]*[a-f0-9]+:	40 80 c6 01[ 	]+add    \$0x1,%sil
 [ 	]*[a-f0-9]+:	40 80 c7 01[ 	]+add    \$0x1,%dil
+[ 	]*[a-f0-9]+:	40 e4 00[ 	]+rex in \$0x0,%al
+[ 	]*[a-f0-9]+:	40 e6 00[ 	]+rex out %al,\$0x0
+[ 	]*[a-f0-9]+:	40 d3 e0[ 	]+rex shl %cl,%eax
 [ 	]*[a-f0-9]+:	0f 71 d6 02          	psrlw  \$0x2,%mm6
 [ 	]*[a-f0-9]+:	66 0f 71 d2 02       	psrlw  \$0x2,%xmm2
 [ 	]*[a-f0-9]+:	0f 71 e6 02          	psraw  \$0x2,%mm6

gas/testsuite/gas/i386/x86-64-reg.s

@@ -30,6 +30,10 @@ pslldq $2, %xmm10
 	add	$1, %sil
 	add	$1, %dil
 
+	in	$0, %axl
+	out	%axl, $0
+	shl	%cxl, %eax
+
 .intel_syntax noprefix
 psrlw mm6, 2
 psrlw xmm2, 2

gas/testsuite/gas/i386/x86-64.exp

@@ -156,7 +156,6 @@ run_dump_test "x86-64-simd-suffix"
 run_dump_test "x86-64-mem"
 run_dump_test "x86-64-mem-intel"
 run_dump_test "x86-64-reg"
-run_list_test "x86-64-reg-bad" "-al"
 run_dump_test "x86-64-reg-intel"
 run_dump_test "x86-64-sib"
 run_dump_test "x86-64-sib-intel"

opcodes/i386-reg.tbl

@@ -30,8 +30,8 @@ ah, Class=Reg|Byte, 0, 4, Dw2Inval, Dw2Inval
 ch, Class=Reg|Byte, 0, 5, Dw2Inval, Dw2Inval
 dh, Class=Reg|Byte, 0, 6, Dw2Inval, Dw2Inval
 bh, Class=Reg|Byte, 0, 7, Dw2Inval, Dw2Inval
-axl, Class=Reg|Byte, RegRex64, 0, Dw2Inval, Dw2Inval
+axl, Class=Reg|Instance=Accum|Byte, RegRex64, 0, Dw2Inval, Dw2Inval
-cxl, Class=Reg|Byte, RegRex64, 1, Dw2Inval, Dw2Inval
+cxl, Class=Reg|Instance=RegC|Byte, RegRex64, 1, Dw2Inval, Dw2Inval
 dxl, Class=Reg|Byte, RegRex64, 2, Dw2Inval, Dw2Inval
 bxl, Class=Reg|Byte, RegRex64, 3, Dw2Inval, Dw2Inval
 spl, Class=Reg|Byte, RegRex64, 4, Dw2Inval, Dw2Inval

opcodes/i386-tbl.h

@@ -50491,11 +50491,11 @@ static const reg_entry i386_regtab[] =
 	0, 0, 0, 0, 0, 0 } },
     0, 7, { Dw2Inval, Dw2Inval } },
   { "axl",
-    { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
+    { { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
 	0, 0, 0, 0, 0, 0 } },
     RegRex64, 0, { Dw2Inval, Dw2Inval } },
   { "cxl",
-    { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
+    { { 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
 	0, 0, 0, 0, 0, 0 } },
     RegRex64, 1, { Dw2Inval, Dw2Inval } },
   { "dxl",