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cpu/or1k: Add support for orfp64a32 spec

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This patch adds support for OpenRISC 64-bit FPU operations on 32-bit cores by
using register pairs.  The functionality has been added to OpenRISC architecture
specification version 1.3 as per architecture proposal 14[0].

For supporting assembly of both 64-bit and 32-bit precision instructions we have
defined CGEN_VALIDATE_INSN_SUPPORTED.  This allows cgen to use 64-bit bit
architecture assembly parsing on 64-bit toolchains and 32-bit architecture
assembly parsing on 32-bit toolchains.  Without this the assembler has issues
parsing register pairs.

This patch also contains a few fixes to the symantics for existing OpenRISC
single and double precision FPU operations.

[0] https://openrisc.io/proposals/orfpx64a32

cpu/ChangeLog:

yyyy-mm-dd  Andrey Bacherov  <avbacherov@opencores.org>
	    Stafford Horne  <shorne@gmail.com>

	* or1k.cpu (ORFPX64A32-MACHS): New pmacro.
	(ORFPX-MACHS): Removed pmacro.
	* or1k.opc (or1k_cgen_insn_supported): New function.
	(CGEN_VALIDATE_INSN_SUPPORTED): Define macro.
	(parse_regpair, print_regpair): New functions.
	* or1kcommon.cpu (h-spr, spr-shift, spr-address, h-gpr): Reorder
	and add comments.
	(h-fdr): Update comment to indicate or64.
	(reg-pair-reg-lo, reg-pair-reg-hi): New pmacros for register pairs.
	(h-fd32r): New hardware for 64-bit fpu registers.
	(h-i64r): New hardware for 64-bit int registers.
	* or1korbis.cpu (f-resv-8-1): New field.
	* or1korfpx.cpu (rDSF, rASF, rBSF): Update attribute to ORFPX32-MACHS.
	(rDDF, rADF, rBDF): Update operand comment to indicate or64.
	(f-rdoff-10-1, f-raoff-9-1, f-rboff-8-1): New fields.
	(h-roff1): New hardware.
	(double-field-and-ops mnemonic): New pmacro to generate operations
	rDD32F, rAD32F, rBD32F, rDDI and rADI.
	(float-regreg-insn): Update single precision generator to MACH
	ORFPX32-MACHS.  Add generator for or32 64-bit instructions.
	(float-setflag-insn): Update single precision generator to MACH
	ORFPX32-MACHS.  Fix double instructions from single to double
	precision.  Add generator for or32 64-bit instructions.
	(float-cust-insn cust-num): Update single precision generator to MACH
	ORFPX32-MACHS.  Add generator for or32 64-bit instructions.
	(lf-rem-s, lf-itof-s, lf-ftoi-s, lf-madd-s): Update MACH to
	ORFPX32-MACHS.
	(lf-rem-d): Fix operation from mod to rem.
	(lf-rem-d32, lf-itof-d32, lf-ftoi-d32, lf-madd-d32): New instruction.
	(lf-itof-d): Fix operands from single to double.
	(lf-ftoi-d): Update operand mode from DI to WI.
This commit is contained in:
Stafford Horne
2019-06-13 06:16:18 +09:00
parent a0e44ef56c
commit 6ce26ac7c3
6 changed files with 376 additions and 47 deletions
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115
cpu/or1kcommon.cpu
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@@ -1,7 +1,8 @@
; OpenRISC 1000 32-bit CPU hardware description. -*- Scheme -*-
; Copyright 2000-2014 Free Software Foundation, Inc.
; Copyright 2000-2019 Free Software Foundation, Inc.
; Contributed for OR32 by Johan Rydberg, jrydberg@opencores.org
; Modified by Julius Baxter, juliusbaxter@gmail.com
; Modified by Andrey Bacherov, avbacherov@opencores.org
;
; This program is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
@@ -71,25 +72,9 @@
(fp 2))
)
(define-hardware
(name h-fsr)
(comment "floating point registers (single, virtual)")
(attrs VIRTUAL (MACH ORFPX32-MACHS))
(type register SF (32))
(indices keyword "" REG-INDICES)
(get (index) (subword SF (trunc SI (reg h-gpr index)) 0))
(set (index newval) (set UWI (reg h-gpr index) (zext UWI (subword SI newval 0))))
)
(define-hardware
(name h-fdr) (comment "floating point registers (double, virtual)")
(attrs VIRTUAL (MACH ORFPX64-MACHS))
(type register DF (32))
(indices keyword "" REG-INDICES)
(get (index) (subword DF (trunc DI (reg h-gpr index)) 0))
(set (index newval) (set UDI (reg h-gpr index) (zext UDI (subword DI newval 0))))
)
;
; Hardware: [S]pecial [P]urpose [R]egisters
;
(define-hardware
(name h-spr) (comment "special purpose registers")
(attrs VIRTUAL (MACH ORBIS-MACHS))
@@ -103,6 +88,9 @@
(or (sll UWI (enum UWI (.sym "SPR-GROUP-" spr-group)) spr-shift)
(enum UWI (.sym "SPR-INDEX-" spr-group "-" spr-index))))
;
; Hardware: [G]enepral [P]urpose [R]egisters
;
(define-hardware
(name h-gpr) (comment "general registers")
(attrs (MACH ORBIS-MACHS))
@@ -112,6 +100,93 @@
(set (index newval) (set UWI (reg UWI h-spr (add index (spr-address SYS GPR0))) newval))
)
;
; Hardware: virtual registerts for FPU (single precision)
; mapped to GPRs
;
(define-hardware
(name h-fsr)
(comment "floating point registers (single, virtual)")
(attrs VIRTUAL (MACH ORFPX32-MACHS))
(type register SF (32))
(indices keyword "" REG-INDICES)
(get (index) (subword SF (trunc SI (reg h-gpr index)) 0))
(set (index newval) (set UWI (reg h-gpr index) (zext UWI (subword SI newval 0))))
)
;
; Hardware: virtual registerts for FPU (double precision)
; mapped to GPRs
;
(define-hardware
(name h-fdr)
(comment "or64 floating point registers (double, virtual)")
(attrs VIRTUAL (MACH ORFPX64-MACHS))
(type register DF (32))
(indices keyword "" REG-INDICES)
(get (index) (subword DF (trunc DI (reg h-gpr index)) 0))
(set (index newval) (set UDI (reg h-gpr index) (zext UDI (subword DI newval 0))))
)
;
; Register pairs are offset by 2 for registers r16 and above. This is to
; be able to allow registers to be call saved in GCC across function calls.
;
(define-pmacro (reg-pair-reg-lo index)
(and index (const #x1f))
)
(define-pmacro (reg-pair-reg-hi index)
(add (and index (const #x1f))
(if (eq (sra index (const 5))
(const 1))
(const 2)
(const 1)
)
)
)
;
; Hardware: vrtual registers for double precision floating point
; operands on 32-bit machines
; mapped to GPRs
;
(define-hardware
(name h-fd32r)
(comment "or32 floating point registers (double, virtual)")
(attrs VIRTUAL (MACH ORFPX64A32-MACHS))
(type register DF (32))
(get (index) (join DF SI
(reg h-gpr (reg-pair-reg-lo index))
(reg h-gpr (reg-pair-reg-hi index))))
(set (index newval)
(sequence ()
(set (reg h-gpr (reg-pair-reg-lo index)) (subword SI newval 0))
(set (reg h-gpr (reg-pair-reg-hi index))
(subword SI newval 1))))
)
;
; Hardware: vrtual 64-bit integer registers for conversions
; float64 <-> int64 on 32-bit machines
; mapped to GPRs
;
(define-hardware
(name h-i64r)
(comment "or32 double word registers (int64, virtual)")
(attrs VIRTUAL (MACH ORFPX64A32-MACHS))
(type register DI (32))
(get (index) (join DI SI
(reg h-gpr (reg-pair-reg-lo index))
(reg h-gpr (reg-pair-reg-hi index))))
(set (index newval)
(sequence ()
(set (reg h-gpr (reg-pair-reg-lo index)) (subword SI newval 0))
(set (reg h-gpr (reg-pair-reg-hi index))
(subword SI newval 1))))
)
(define-normal-enum
except-number
"Exception numbers"