Imagelibrary/binutils-gdb
1
0
Fork 1
mirror of https://github.com/bminor/binutils-gdb.git synced 2025-12-05 15:15:42 +00:00
Code Issues Packages Projects Releases Wiki Activity

RISC-V: Added vendor extensions, xmipscbop, xmipscmov, xmipsexectl and xmipslsp

Browse Source 
Spec:
https://mips.com/wp-content/uploads/2025/03/P8700-F_Programmers_Reference_Manual_Rev1.82_3-19-2025.pdf

Added MIPS vendor extensions, xmipscbop, xmipscmov, xmipsexectl and xmipslsp
with verison 1.0.

Passed binutils testsuites of targets elf32/elf64/linux32/linux64.

Signed-off-by: Jovan Dmitrović <jovan.dmitrovic@htecgroup.com>
Signed-off-by: Chao-ying Fu <cfu@wavecomp.com>
This commit is contained in:
Chao-ying Fu
2025-05-09 09:52:17 +08:00
committed by Nelson Chu
parent 4480aaee57
commit 617ead3c20
11 changed files with 329 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

29
include/opcode/riscv-opc.h
View File

@@ -3804,6 +3804,25 @@
#define MASK_SFVFNRCLIPXUFQF 0xfe00707f
#define MATCH_SFVFNRCLIPXFQF 0x8e00505b
#define MASK_SFVFNRCLIPXFQF 0xfe00707f
/* MIPS custom instruction. */
#define MATCH_MIPS_CCMOV 0x600300b
#define MASK_MIPS_CCMOV 0x600707f
#define MATCH_MIPS_LWP 0x0010400b
#define MASK_MIPS_LWP 0x0030707f
#define MATCH_MIPS_LDP 0x0000400b
#define MASK_MIPS_LDP 0x0070707f
#define MATCH_MIPS_SWP 0x0000508b
#define MASK_MIPS_SWP 0x000071ff
#define MATCH_MIPS_SDP 0x0000500b
#define MASK_MIPS_SDP 0x000073ff
#define MATCH_MIPS_EHB 0x00301013
#define MASK_MIPS_EHB 0xffffffff
#define MATCH_MIPS_IHB 0x00101013
#define MASK_MIPS_IHB 0xffffffff
#define MATCH_MIPS_PAUSE 0x00501013
#define MASK_MIPS_PAUSE 0xffffffff
#define MATCH_MIPS_PREF 0x0000000b
#define MASK_MIPS_PREF 0xe000707f
/* Unprivileged Counter/Timers CSR addresses. */
#define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01
@@ -4945,6 +4964,16 @@ DECLARE_INSN(ssamoswap_w, MATCH_SSAMOSWAP_W, MASK_SSAMOSWAP_W)
DECLARE_INSN(ssamoswap_d, MATCH_SSAMOSWAP_D, MASK_SSAMOSWAP_D)
/* Zicfilp instructions. */
DECLARE_INSN(lpad, MATCH_LPAD, MASK_LPAD)
/* MIPS custom instructions. */
DECLARE_INSN(mips_ccmov, MATCH_MIPS_CCMOV, MASK_MIPS_CCMOV)
DECLARE_INSN(mips_lwp, MATCH_MIPS_LWP, MASK_MIPS_LWP)
DECLARE_INSN(mips_ldp, MATCH_MIPS_LDP, MASK_MIPS_LDP)
DECLARE_INSN(mips_swp, MATCH_MIPS_SWP, MASK_MIPS_SWP)
DECLARE_INSN(mips_sdp, MATCH_MIPS_SDP, MASK_MIPS_SDP)
DECLARE_INSN(mips_ehb, MATCH_MIPS_EHB, MASK_MIPS_EHB)
DECLARE_INSN(mips_ihb, MATCH_MIPS_IHB, MASK_MIPS_IHB)
DECLARE_INSN(mips_pause, MATCH_MIPS_PAUSE, MASK_MIPS_PAUSE)
DECLARE_INSN(mips_pref, MATCH_MIPS_PREF, MASK_MIPS_PREF)
#endif /* DECLARE_INSN */
#ifdef DECLARE_CSR
/* Unprivileged Counter/Timers CSRs. */

40
include/opcode/riscv.h
View File

@@ -132,6 +132,15 @@ static inline unsigned int riscv_insn_length (insn_t insn)
((RV_X(x, 25, 1)) | (RV_X(x, 20, 5) << 1) | (RV_IMM_SIGN_N(x, 20, 5) << 5))
#define EXTRACT_CV_SIMD_UIMM6(x) \
((RV_X(x, 25, 1)) | (RV_X(x, 20, 5) << 1))
/* Vendor-specific (MIPS) extract macros. */
#define EXTRACT_MIPS_LWP_IMM(x) \
(RV_X(x, 22, 5) << 2)
#define EXTRACT_MIPS_LDP_IMM(x) \
(RV_X(x, 23, 4) << 3)
#define EXTRACT_MIPS_SWP_IMM(x) \
((RV_X(x, 25, 2) << 5) | (RV_X(x, 9, 3) << 2))
#define EXTRACT_MIPS_SDP_IMM(x) \
((RV_X(x, 25, 2) << 5) | (RV_X(x, 10, 2) << 3))
#define ENCODE_ITYPE_IMM(x) \
(RV_X(x, 0, 12) << 20)
@@ -200,6 +209,15 @@ static inline unsigned int riscv_insn_length (insn_t insn)
((RV_X(x, 0, 1) << 25) | (RV_X(x, 1, 5) << 20))
#define ENCODE_CV_SIMD_UIMM6(x) \
((RV_X(x, 0, 1) << 25) | (RV_X(x, 1, 5) << 20))
/* Vendor-specific (MIPS) encode macros. */
#define ENCODE_MIPS_LWP_IMM(x) \
(RV_X(x, 2, 5) << 22)
#define ENCODE_MIPS_LDP_IMM(x) \
(RV_X(x, 3, 4) << 23)
#define ENCODE_MIPS_SWP_IMM(x) \
((RV_X(x, 5, 2) << 25) | (RV_X(x, 2, 3) << 9))
#define ENCODE_MIPS_SDP_IMM(x) \
((RV_X(x, 5, 2) << 25) | (RV_X(x, 3, 2) << 10))
#define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
#define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
@@ -383,6 +401,24 @@ static inline unsigned int riscv_insn_length (insn_t insn)
#define OP_MASK_XSO1 0x1
#define OP_SH_XSO1 26
/* MIPS fields. */
#define OP_MASK_MIPS_IMM9 0x1ff
#define OP_SH_MIPS_IMM9 20
#define OP_MASK_MIPS_HINT 0x1f
#define OP_SH_MIPS_HINT 7
#define OP_MASK_MIPS_LWP_OFFSET 0x1f
#define OP_SH_MIPS_LWP_OFFSET 22
#define OP_MASK_MIPS_LDP_OFFSET 0xf
#define OP_SH_MIPS_LDP_OFFSET 23
#define OP_MASK_MIPS_SWP_OFFSET9 0x7
#define OP_SH_MIPS_SWP_OFFSET9 9
#define OP_MASK_MIPS_SWP_OFFSET25 0x3
#define OP_SH_MIPS_SWP_OFFSET25 25
#define OP_MASK_MIPS_SDP_OFFSET10 0x3
#define OP_SH_MIPS_SDP_OFFSET10 10
#define OP_MASK_MIPS_SDP_OFFSET25 0x3
#define OP_SH_MIPS_SDP_OFFSET25 25
/* ABI names for selected x-registers. */
#define X_RA 1
@@ -563,6 +599,10 @@ enum riscv_insn_class
INSN_CLASS_XSFVQMACCQOQ,
INSN_CLASS_XSFVQMACCDOD,
INSN_CLASS_XSFVFNRCLIPXFQF,
INSN_CLASS_XMIPSCBOP,
INSN_CLASS_XMIPSCMOV,
INSN_CLASS_XMIPSEXECTL,
INSN_CLASS_XMIPSLSP,
};
/* This structure holds information for a particular instruction. */