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Add support for 48 and 64 bit ARC instructions.
gas * config/tc-arc.c (parse_opcode_flags): New function. (find_opcode_match): Move flag parsing code out to new function. Ignore operands marked IGNORE. (build_fake_opcode_hash_entry): New function. (find_special_case_long_opcode): New function. (find_special_case): Lookup long opcodes. * testsuite/gas/arc/nps400-7.d: New file. * testsuite/gas/arc/nps400-7.s: New file. include * opcode/arc.h (MAX_INSN_ARGS): Increase to 16. (struct arc_long_opcode): New structure. (arc_long_opcodes): Declare. (arc_num_long_opcodes): Declare. opcodes * arc-dis.c (struct arc_operand_iterator): New structure. (find_format_from_table): All the old content from find_format, with some minor adjustments, and parameter renaming. (find_format_long_instructions): New function. (find_format): Rewritten. (arc_insn_length): Add LSB parameter. (extract_operand_value): New function. (operand_iterator_next): New function. (print_insn_arc): Use new functions to find opcode, and iterator over operands. * arc-opc.c (insert_nps_3bit_dst_short): New function. (extract_nps_3bit_dst_short): New function. (insert_nps_3bit_src2_short): New function. (extract_nps_3bit_src2_short): New function. (insert_nps_bitop1_size): New function. (extract_nps_bitop1_size): New function. (insert_nps_bitop2_size): New function. (extract_nps_bitop2_size): New function. (insert_nps_bitop_mod4_msb): New function. (extract_nps_bitop_mod4_msb): New function. (insert_nps_bitop_mod4_lsb): New function. (extract_nps_bitop_mod4_lsb): New function. (insert_nps_bitop_dst_pos3_pos4): New function. (extract_nps_bitop_dst_pos3_pos4): New function. (insert_nps_bitop_ins_ext): New function. (extract_nps_bitop_ins_ext): New function. (arc_operands): Add new operands. (arc_long_opcodes): New global array. (arc_num_long_opcodes): New global. * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
This commit is contained in:
Andrew Burgess
committed by
Nick Clifton
Nick Clifton
parent
5b6312fd20
commit
4eb6f89250
@@ -28,6 +28,43 @@
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#include "arc-dis.h"
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#include "arc-ext.h"
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/* Structure used to iterate over, and extract the values for, operands of
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an opcode. */
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struct arc_operand_iterator
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{
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enum
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{
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OPERAND_ITERATOR_STANDARD,
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OPERAND_ITERATOR_LONG
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} mode;
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/* The array of 32-bit values that make up this instruction. All
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required values have been pre-loaded into this array during the
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find_format call. */
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unsigned *insn;
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union
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{
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struct
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{
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/* The opcode this iterator is operating on. */
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const struct arc_opcode *opcode;
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/* The index into the opcodes operand index list. */
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const unsigned char *opidx;
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} standard;
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struct
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{
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/* The long instruction opcode this iterator is operating on. */
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const struct arc_long_opcode *long_opcode;
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/* Two indexes into the opcodes operand index lists. */
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const unsigned char *opidx_base, *opidx_limm;
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} long_insn;
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} state;
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};
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/* Globals variables. */
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@@ -102,11 +139,13 @@ special_flag_p (const char *opname,
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return 0;
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}
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/* Find proper format for the given opcode. */
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/* Find opcode from ARC_TABLE given the instruction described by INSN and
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INSNLEN. The ISA_MASK restricts the possible matches in ARC_TABLE. */
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static const struct arc_opcode *
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find_format (const struct arc_opcode *arc_table,
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unsigned *insn, unsigned int insnLen,
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unsigned isa_mask)
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find_format_from_table (const struct arc_opcode *arc_table,
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unsigned *insn, unsigned int insn_len,
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unsigned isa_mask, bfd_boolean *has_limm)
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{
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unsigned int i = 0;
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const struct arc_opcode *opcode = NULL;
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@@ -118,12 +157,12 @@ find_format (const struct arc_opcode *arc_table,
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opcode = &arc_table[i++];
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if (ARC_SHORT (opcode->mask) && (insnLen == 2))
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if (ARC_SHORT (opcode->mask) && (insn_len == 2))
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{
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if (OPCODE_AC (opcode->opcode) != OPCODE_AC (insn[0]))
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continue;
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}
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else if (!ARC_SHORT (opcode->mask) && (insnLen == 4))
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else if (!ARC_SHORT (opcode->mask) && (insn_len == 4))
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{
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if (OPCODE (opcode->opcode) != OPCODE (insn[0]))
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continue;
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@@ -137,6 +176,8 @@ find_format (const struct arc_opcode *arc_table,
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if (!(opcode->cpu & isa_mask))
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continue;
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*has_limm = FALSE;
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/* Possible candidate, check the operands. */
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for (opidx = opcode->operands; *opidx; opidx++)
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{
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@@ -156,13 +197,17 @@ find_format (const struct arc_opcode *arc_table,
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if (operand->flags & ARC_OPERAND_IR
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&& !(operand->flags & ARC_OPERAND_LIMM))
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{
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if ((value == 0x3E && insnLen == 4)
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|| (value == 0x1E && insnLen == 2))
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if ((value == 0x3E && insn_len == 4)
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|| (value == 0x1E && insn_len == 2))
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{
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invalid = TRUE;
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break;
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}
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}
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if (operand->flags & ARC_OPERAND_LIMM
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&& !(operand->flags & ARC_OPERAND_DUPLICATE))
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*has_limm = TRUE;
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}
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/* Check the flags. */
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@@ -210,6 +255,184 @@ find_format (const struct arc_opcode *arc_table,
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return NULL;
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}
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/* Find long instructions matching values in INSN array. */
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static const struct arc_long_opcode *
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find_format_long_instructions (unsigned *insn,
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unsigned int *insn_len,
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unsigned isa_mask,
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bfd_vma memaddr,
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struct disassemble_info *info)
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{
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unsigned int i;
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unsigned limm = 0;
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bfd_boolean limm_loaded = FALSE;
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for (i = 0; i < arc_num_long_opcodes; ++i)
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{
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bfd_byte buffer[4];
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int status;
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const struct arc_opcode *opcode;
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opcode = &arc_long_opcodes[i].base_opcode;
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if (ARC_SHORT (opcode->mask) && (*insn_len == 2))
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{
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if (OPCODE_AC (opcode->opcode) != OPCODE_AC (insn[0]))
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continue;
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}
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else if (!ARC_SHORT (opcode->mask) && (*insn_len == 4))
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{
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if (OPCODE (opcode->opcode) != OPCODE (insn[0]))
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continue;
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}
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else
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continue;
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if ((insn[0] ^ opcode->opcode) & opcode->mask)
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continue;
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if (!(opcode->cpu & isa_mask))
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continue;
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if (!limm_loaded)
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{
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status = (*info->read_memory_func) (memaddr + *insn_len, buffer,
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4, info);
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if (status != 0)
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return NULL;
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limm = ARRANGE_ENDIAN (info, buffer);
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limm_loaded = TRUE;
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}
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/* Check the second word using the mask and template. */
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if ((limm & arc_long_opcodes[i].limm_mask)
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!= arc_long_opcodes[i].limm_template)
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continue;
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(*insn_len) += 4;
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insn[1] = limm;
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return &arc_long_opcodes[i];
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}
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return NULL;
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}
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/* Find opcode for INSN, trying various different sources. The instruction
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length in INSN_LEN will be updated if the instruction requires a LIMM
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extension, and the additional values loaded into the INSN array (which
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must be big enough).
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A pointer to the opcode is placed into OPCODE_RESULT, and ITER is
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initialised, ready to iterate over the operands of the found opcode.
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This function returns TRUE in almost all cases, FALSE is reserved to
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indicate an error (failing to find an opcode is not an error) a
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returned result of FALSE would indicate that the disassembler can't
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continue.
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If no matching opcode is found then the returned result will be TRUE,
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the value placed into OPCODE_RESULT will be NULL, ITER will be
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undefined, and INSN_LEN will be unchanged.
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If a matching opcode is found, then the returned result will be TRUE,
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the opcode pointer is placed into OPCODE_RESULT, INSN_LEN will be
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increased by 4 if the instruction requires a LIMM, and the LIMM value
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will have been loaded into the INSN[1]. Finally, ITER will have been
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initialised so that calls to OPERAND_ITERATOR_NEXT will iterate over
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the opcode's operands. */
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static bfd_boolean
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find_format (bfd_vma memaddr, unsigned *insn, unsigned int *insn_len,
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unsigned isa_mask, struct disassemble_info *info,
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const struct arc_opcode **opcode_result,
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struct arc_operand_iterator *iter)
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{
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const struct arc_opcode *opcode;
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bfd_boolean needs_limm;
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/* Find the first match in the opcode table. */
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opcode = find_format_from_table (arc_opcodes, insn, *insn_len,
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isa_mask, &needs_limm);
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if (opcode == NULL)
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{
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const extInstruction_t *einsn;
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/* No instruction found. Try the extensions. */
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einsn = arcExtMap_insn (OPCODE (insn[0]), insn[0]);
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if (einsn != NULL)
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{
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const char *errmsg = NULL;
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opcode = arcExtMap_genOpcode (einsn, isa_mask, &errmsg);
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if (opcode == NULL)
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{
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(*info->fprintf_func) (info->stream,
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"An error occured while "
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"generating the extension instruction "
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"operations");
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*opcode_result = NULL;
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return FALSE;
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}
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opcode = find_format_from_table (opcode, insn, *insn_len,
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isa_mask, &needs_limm);
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assert (opcode != NULL);
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}
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}
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if (needs_limm && opcode != NULL)
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{
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bfd_byte buffer[4];
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int status;
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status = (*info->read_memory_func) (memaddr + *insn_len, buffer,
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4, info);
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if (status != 0)
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{
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opcode = NULL;
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}
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else
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{
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insn[1] = ARRANGE_ENDIAN (info, buffer);
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*insn_len += 4;
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}
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}
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if (opcode == NULL)
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{
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const struct arc_long_opcode *long_opcode;
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/* No instruction found yet, try the long instructions. */
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long_opcode =
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find_format_long_instructions (insn, insn_len, isa_mask,
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memaddr, info);
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if (long_opcode != NULL)
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{
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iter->mode = OPERAND_ITERATOR_LONG;
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iter->insn = insn;
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iter->state.long_insn.long_opcode = long_opcode;
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iter->state.long_insn.opidx_base =
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long_opcode->base_opcode.operands;
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iter->state.long_insn.opidx_limm =
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long_opcode->operands;
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opcode = &long_opcode->base_opcode;
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}
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}
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else
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{
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iter->mode = OPERAND_ITERATOR_STANDARD;
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iter->insn = insn;
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iter->state.standard.opcode = opcode;
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iter->state.standard.opidx = opcode->operands;
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}
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*opcode_result = opcode;
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return TRUE;
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}
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static void
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print_flags (const struct arc_opcode *opcode,
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unsigned *insn,
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@@ -328,13 +551,20 @@ get_auxreg (const struct arc_opcode *opcode,
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cached for later use. */
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static unsigned int
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arc_insn_length (bfd_byte msb, struct disassemble_info *info)
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arc_insn_length (bfd_byte msb, bfd_byte lsb, struct disassemble_info *info)
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{
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bfd_byte major_opcode = msb >> 3;
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switch (info->mach)
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{
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case bfd_mach_arc_nps400:
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if (major_opcode == 0xb)
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{
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bfd_byte minor_opcode = lsb & 0x1f;
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if (minor_opcode < 4)
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return 2;
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}
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case bfd_mach_arc_arc700:
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case bfd_mach_arc_arc600:
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return (major_opcode > 0xb) ? 2 : 4;
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@@ -349,6 +579,120 @@ arc_insn_length (bfd_byte msb, struct disassemble_info *info)
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}
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}
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/* Extract and return the value of OPERAND from the instruction whose value
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is held in the array INSN. */
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static int
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extract_operand_value (const struct arc_operand *operand, unsigned *insn)
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{
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int value;
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/* Read the limm operand, if required. */
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if (operand->flags & ARC_OPERAND_LIMM)
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/* The second part of the instruction value will have been loaded as
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part of the find_format call made earlier. */
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value = insn[1];
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else
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{
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if (operand->extract)
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value = (*operand->extract) (insn[0], (int *) NULL);
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else
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{
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if (operand->flags & ARC_OPERAND_ALIGNED32)
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{
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value = (insn[0] >> operand->shift)
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& ((1 << (operand->bits - 2)) - 1);
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value = value << 2;
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}
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else
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{
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value = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
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}
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if (operand->flags & ARC_OPERAND_SIGNED)
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{
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int signbit = 1 << (operand->bits - 1);
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value = (value ^ signbit) - signbit;
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}
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}
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}
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return value;
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}
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/* Find the next operand, and the operands value from ITER. Return TRUE if
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there is another operand, otherwise return FALSE. If there is an
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operand returned then the operand is placed into OPERAND, and the value
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into VALUE. If there is no operand returned then OPERAND and VALUE are
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unchanged. */
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static bfd_boolean
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operand_iterator_next (struct arc_operand_iterator *iter,
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const struct arc_operand **operand,
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int *value)
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{
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if (iter->mode == OPERAND_ITERATOR_STANDARD)
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{
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if (*iter->state.standard.opidx == 0)
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{
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*operand = NULL;
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return FALSE;
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}
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*operand = &arc_operands[*iter->state.standard.opidx];
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*value = extract_operand_value (*operand, iter->insn);
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iter->state.standard.opidx++;
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}
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else
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{
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const struct arc_operand *operand_base, *operand_limm;
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int value_base, value_limm;
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if (*iter->state.long_insn.opidx_limm == 0)
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{
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*operand = NULL;
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return FALSE;
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}
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operand_base = &arc_operands[*iter->state.long_insn.opidx_base];
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operand_limm = &arc_operands[*iter->state.long_insn.opidx_limm];
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if (operand_base->flags & ARC_OPERAND_LIMM)
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{
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/* We've reached the end of the operand list. */
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*operand = NULL;
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return FALSE;
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}
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value_base = value_limm = 0;
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if (!(operand_limm->flags & ARC_OPERAND_IGNORE))
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{
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/* This should never happen. If it does then the use of
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extract_operand_value below will access memory beyond
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the insn array. */
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assert ((operand_limm->flags & ARC_OPERAND_LIMM) == 0);
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*operand = operand_limm;
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value_limm = extract_operand_value (*operand, &iter->insn[1]);
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}
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if (!(operand_base->flags & ARC_OPERAND_IGNORE))
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{
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*operand = operand_base;
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value_base = extract_operand_value (*operand, iter->insn);
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}
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/* This is a bit of a fudge. There's no reason why simply ORing
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together the two values is the right thing to do, however, for all
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the cases we currently have, it is the right thing, so, for now,
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I've put off solving the more complex problem. */
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*value = value_base | value_limm;
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iter->state.long_insn.opidx_base++;
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iter->state.long_insn.opidx_limm++;
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}
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return TRUE;
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}
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/* Disassemble ARC instructions. */
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static int
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@@ -358,16 +702,18 @@ print_insn_arc (bfd_vma memaddr,
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bfd_byte buffer[4];
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unsigned int lowbyte, highbyte;
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int status;
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unsigned int insnLen;
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unsigned int insn_len;
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unsigned insn[2] = { 0, 0 };
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unsigned isa_mask;
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const unsigned char *opidx;
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const struct arc_opcode *opcode;
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const extInstruction_t *einsn;
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bfd_boolean need_comma;
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bfd_boolean open_braket;
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int size;
|
||||
const struct arc_operand *operand;
|
||||
int value;
|
||||
struct arc_operand_iterator iter;
|
||||
|
||||
memset (&iter, 0, sizeof (iter));
|
||||
lowbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 1 : 0);
|
||||
highbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 0 : 1);
|
||||
|
||||
@@ -462,8 +808,9 @@ print_insn_arc (bfd_vma memaddr,
|
||||
return size;
|
||||
}
|
||||
|
||||
insnLen = arc_insn_length (buffer[lowbyte], info);
|
||||
switch (insnLen)
|
||||
insn_len = arc_insn_length (buffer[lowbyte], buffer[highbyte], info);
|
||||
pr_debug ("instruction length = %d bytes\n", insn_len);
|
||||
switch (insn_len)
|
||||
{
|
||||
case 2:
|
||||
insn[0] = (buffer[lowbyte] << 8) | buffer[highbyte];
|
||||
@@ -498,38 +845,18 @@ print_insn_arc (bfd_vma memaddr,
|
||||
info->disassembler_needs_relocs = TRUE;
|
||||
|
||||
/* Find the first match in the opcode table. */
|
||||
opcode = find_format (arc_opcodes, insn, insnLen, isa_mask);
|
||||
if (!find_format (memaddr, insn, &insn_len, isa_mask, info, &opcode, &iter))
|
||||
return -1;
|
||||
|
||||
if (!opcode)
|
||||
{
|
||||
/* No instruction found. Try the extensions. */
|
||||
einsn = arcExtMap_insn (OPCODE (insn[0]), insn[0]);
|
||||
if (einsn)
|
||||
{
|
||||
const char *errmsg = NULL;
|
||||
opcode = arcExtMap_genOpcode (einsn, isa_mask, &errmsg);
|
||||
if (opcode == NULL)
|
||||
{
|
||||
(*info->fprintf_func) (info->stream,
|
||||
"An error occured while "
|
||||
"generating the extension instruction "
|
||||
"operations");
|
||||
return -1;
|
||||
}
|
||||
|
||||
opcode = find_format (opcode, insn, insnLen, isa_mask);
|
||||
assert (opcode != NULL);
|
||||
}
|
||||
if (insn_len == 2)
|
||||
(*info->fprintf_func) (info->stream, ".long %#04x", insn[0]);
|
||||
else
|
||||
{
|
||||
if (insnLen == 2)
|
||||
(*info->fprintf_func) (info->stream, ".long %#04x", insn[0]);
|
||||
else
|
||||
(*info->fprintf_func) (info->stream, ".long %#08x", insn[0]);
|
||||
(*info->fprintf_func) (info->stream, ".long %#08x", insn[0]);
|
||||
|
||||
info->insn_type = dis_noninsn;
|
||||
return insnLen;
|
||||
}
|
||||
info->insn_type = dis_noninsn;
|
||||
return insn_len;
|
||||
}
|
||||
|
||||
/* Print the mnemonic. */
|
||||
@@ -575,11 +902,9 @@ print_insn_arc (bfd_vma memaddr,
|
||||
open_braket = FALSE;
|
||||
|
||||
/* Now extract and print the operands. */
|
||||
for (opidx = opcode->operands; *opidx; opidx++)
|
||||
operand = NULL;
|
||||
while (operand_iterator_next (&iter, &operand, &value))
|
||||
{
|
||||
const struct arc_operand *operand = &arc_operands[*opidx];
|
||||
int value;
|
||||
|
||||
if (open_braket && (operand->flags & ARC_OPERAND_BRAKET))
|
||||
{
|
||||
(*info->fprintf_func) (info->stream, "]");
|
||||
@@ -592,30 +917,9 @@ print_insn_arc (bfd_vma memaddr,
|
||||
&& !(operand->flags & ARC_OPERAND_BRAKET))
|
||||
continue;
|
||||
|
||||
if (operand->extract)
|
||||
value = (*operand->extract) (insn[0], (int *) NULL);
|
||||
else
|
||||
{
|
||||
if (operand->flags & ARC_OPERAND_ALIGNED32)
|
||||
{
|
||||
value = (insn[0] >> operand->shift)
|
||||
& ((1 << (operand->bits - 2)) - 1);
|
||||
value = value << 2;
|
||||
}
|
||||
else
|
||||
{
|
||||
value = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
|
||||
}
|
||||
if (operand->flags & ARC_OPERAND_SIGNED)
|
||||
{
|
||||
int signbit = 1 << (operand->bits - 1);
|
||||
value = (value ^ signbit) - signbit;
|
||||
}
|
||||
}
|
||||
|
||||
if (operand->flags & ARC_OPERAND_IGNORE
|
||||
&& (operand->flags & ARC_OPERAND_IR
|
||||
&& value == -1))
|
||||
if ((operand->flags & ARC_OPERAND_IGNORE)
|
||||
&& (operand->flags & ARC_OPERAND_IR)
|
||||
&& value == -1)
|
||||
continue;
|
||||
|
||||
if (need_comma)
|
||||
@@ -629,20 +933,6 @@ print_insn_arc (bfd_vma memaddr,
|
||||
continue;
|
||||
}
|
||||
|
||||
/* Read the limm operand, if required. */
|
||||
if (operand->flags & ARC_OPERAND_LIMM
|
||||
&& !(operand->flags & ARC_OPERAND_DUPLICATE))
|
||||
{
|
||||
status = (*info->read_memory_func) (memaddr + insnLen, buffer,
|
||||
4, info);
|
||||
if (status != 0)
|
||||
{
|
||||
(*info->memory_error_func) (status, memaddr + insnLen, info);
|
||||
return -1;
|
||||
}
|
||||
insn[1] = ARRANGE_ENDIAN (info, buffer);
|
||||
}
|
||||
|
||||
/* Print the operand as directed by the flags. */
|
||||
if (operand->flags & ARC_OPERAND_IR)
|
||||
{
|
||||
@@ -663,15 +953,15 @@ print_insn_arc (bfd_vma memaddr,
|
||||
}
|
||||
else if (operand->flags & ARC_OPERAND_LIMM)
|
||||
{
|
||||
const char *rname = get_auxreg (opcode, insn[1], isa_mask);
|
||||
const char *rname = get_auxreg (opcode, value, isa_mask);
|
||||
if (rname && open_braket)
|
||||
(*info->fprintf_func) (info->stream, "%s", rname);
|
||||
else
|
||||
{
|
||||
(*info->fprintf_func) (info->stream, "%#x", insn[1]);
|
||||
(*info->fprintf_func) (info->stream, "%#x", value);
|
||||
if (info->insn_type == dis_branch
|
||||
|| info->insn_type == dis_jsr)
|
||||
info->target = (bfd_vma) insn[1];
|
||||
info->target = (bfd_vma) value;
|
||||
}
|
||||
}
|
||||
else if (operand->flags & ARC_OPERAND_PCREL)
|
||||
@@ -710,14 +1000,9 @@ print_insn_arc (bfd_vma memaddr,
|
||||
}
|
||||
|
||||
need_comma = TRUE;
|
||||
|
||||
/* Adjust insn len. */
|
||||
if (operand->flags & ARC_OPERAND_LIMM
|
||||
&& !(operand->flags & ARC_OPERAND_DUPLICATE))
|
||||
insnLen += 4;
|
||||
}
|
||||
|
||||
return insnLen;
|
||||
return insn_len;
|
||||
}
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user