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sim: cgen: regenerate decode tables to avoid shadow warnings

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Use latest cgen to regenerate the decode tables which has some shadow
warning fixes with "val" variables.
This commit is contained in:
Mike Frysinger
2023-12-22 10:53:49 -05:00
parent 4a517293bb
commit 401b5b00ec
9 changed files with 548 additions and 548 deletions
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40
sim/m32r/decodex.c
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@@ -265,8 +265,8 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
CGEN_INSN_WORD insn = base_insn;
{
unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
switch (val)
unsigned int val0 = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
switch (val0)
{
case 0 : itype = M32RXF_INSN_SUBV; goto extract_sfmt_addv;
case 1 : itype = M32RXF_INSN_SUBX; goto extract_sfmt_addx;
@@ -277,8 +277,8 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
case 6 : itype = M32RXF_INSN_CMPEQ; goto extract_sfmt_cmp;
case 7 :
{
unsigned int val = (((insn >> 8) & (3 << 0)));
switch (val)
unsigned int val1 = (((insn >> 8) & (3 << 0)));
switch (val1)
{
case 0 :
if ((entire_insn & 0xfff0) == 0x70)
@@ -311,8 +311,8 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
case 26 : itype = M32RXF_INSN_MVTC; goto extract_sfmt_mvtc;
case 28 :
{
unsigned int val = (((insn >> 8) & (3 << 0)));
switch (val)
unsigned int val1 = (((insn >> 8) & (3 << 0)));
switch (val1)
{
case 0 :
if ((entire_insn & 0xfff0) == 0x1cc0)
@@ -396,8 +396,8 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
case 85 : itype = M32RXF_INSN_SLLI; goto extract_sfmt_slli;
case 87 :
{
unsigned int val = (((insn >> 0) & (1 << 0)));
switch (val)
unsigned int val1 = (((insn >> 0) & (1 << 0)));
switch (val1)
{
case 0 :
if ((entire_insn & 0xf0f3) == 0x5070)
@@ -428,8 +428,8 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
case 95 :
{
unsigned int val = (((insn >> 0) & (3 << 0)));
switch (val)
unsigned int val1 = (((insn >> 0) & (3 << 0)));
switch (val1)
{
case 0 : itype = M32RXF_INSN_MVFACHI_A; goto extract_sfmt_mvfachi_a;
case 1 : itype = M32RXF_INSN_MVFACLO_A; goto extract_sfmt_mvfachi_a;
@@ -455,8 +455,8 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
case 111 : itype = M32RXF_INSN_LDI8; goto extract_sfmt_ldi8;
case 112 :
{
unsigned int val = (((insn >> 7) & (15 << 1)) | ((insn >> 0) & (1 << 0)));
switch (val)
unsigned int val1 = (((insn >> 7) & (15 << 1)) | ((insn >> 0) & (1 << 0)));
switch (val1)
{
case 0 :
if ((entire_insn & 0xffff) == 0x7000)
@@ -505,8 +505,8 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
case 126 : /* fall through */
case 127 :
{
unsigned int val = (((insn >> 8) & (15 << 0)));
switch (val)
unsigned int val1 = (((insn >> 8) & (15 << 0)));
switch (val1)
{
case 1 : itype = M32RXF_INSN_SETPSW; goto extract_sfmt_setpsw;
case 2 : itype = M32RXF_INSN_CLRPSW; goto extract_sfmt_clrpsw;
@@ -529,8 +529,8 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
case 134 :
{
unsigned int val = (((entire_insn >> 8) & (3 << 0)));
switch (val)
unsigned int val1 = (((entire_insn >> 8) & (3 << 0)));
switch (val1)
{
case 0 :
if ((entire_insn & 0xf0f0ffff) == 0x80600000)
@@ -554,8 +554,8 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
case 142 : itype = M32RXF_INSN_OR3; goto extract_sfmt_or3;
case 144 :
{
unsigned int val = (((entire_insn >> 4) & (1 << 0)));
switch (val)
unsigned int val1 = (((entire_insn >> 4) & (1 << 0)));
switch (val1)
{
case 0 :
if ((entire_insn & 0xf0f0ffff) == 0x90000000)
@@ -666,8 +666,8 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
case 254 : /* fall through */
case 255 :
{
unsigned int val = (((insn >> 8) & (7 << 0)));
switch (val)
unsigned int val1 = (((insn >> 8) & (7 << 0)));
switch (val1)
{
case 0 :
if ((entire_insn & 0xff000000) == 0xf8000000)