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cpu/mem.opc whitespace tidy

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cpu/
	* mep.opc: Whitespace and formatting.
opcodes/
	* mep-asm.c: Regenerate.
	* mep-dis.c: Regenerate.
This commit is contained in:
Alan Modra
2023-03-16 11:52:09 +10:30
parent 0961e63157
commit 3e8b13bf77
3 changed files with 81 additions and 83 deletions
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43
cpu/mep.opc
View File

@@ -682,10 +682,10 @@ expand_macro (arg *args, int narg, const macro *mac)
/* printf("expanding macro %s with %d args\n", mac->name, narg + 1); */ /* printf("expanding macro %s with %d args\n", mac->name, narg + 1); */
while (*e) while (*e)
{ {
if (*e == '`' && if (*e == '`'
(*e+1) && && (*e+1)
((*(e + 1) - '1') <= MAXARGS) && && ((*(e + 1) - '1') <= MAXARGS)
((*(e + 1) - '1') <= narg)) && ((*(e + 1) - '1') <= narg))
{ {
result = str_append (result, mark, e - mark); result = str_append (result, mark, e - mark);
mac_arg = (*(e + 1) - '1'); mac_arg = (*(e + 1) - '1');
@@ -803,7 +803,6 @@ expand_string (const char *in, int first_only)
if (narg > -1) if (narg > -1)
args[narg].len++; args[narg].len++;
} }
} }
++in; ++in;
} }
@@ -958,8 +957,8 @@ mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info,
} }
status += my_status; status += my_status;
/* Print the + to indicate that the following copro insn is */ /* Print the + to indicate that the following copro insn is
/* part of a vliw group. */ part of a vliw group. */
if (copro1length > 0) if (copro1length > 0)
(*info->fprintf_func) (info->stream, " + "); (*info->fprintf_func) (info->stream, " + ");
} }
@@ -1140,16 +1139,16 @@ mep_examine_vliw32_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
{ {
if ((indicatorcop32[0] & 0xf0) == 0xf0 && (indicatorcop32[1] & 0x07) == 0x07) if ((indicatorcop32[0] & 0xf0) == 0xf0 && (indicatorcop32[1] & 0x07) == 0x07)
{ {
/* We have a 32 bit copro insn. */ /* We have a 32 bit copro insn. */
corebuflength = 0; corebuflength = 0;
/* All 4 4ytes are one copro insn. */ /* All 4 4ytes are one copro insn. */
cop1buflength = 4; cop1buflength = 4;
} }
else else
{ {
/* We have a 32 bit core. */ /* We have a 32 bit core. */
corebuflength = 4; corebuflength = 4;
cop1buflength = 0; cop1buflength = 0;
} }
} }
else else
@@ -1229,16 +1228,16 @@ mep_examine_vliw64_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
if ((indicator64[0] & 0xf0) == 0xf0 && (indicator64[1] & 0x07) == 0x07 if ((indicator64[0] & 0xf0) == 0xf0 && (indicator64[1] & 0x07) == 0x07
&& ((indicator64[2] & 0xfe) != 0xf0 || (indicator64[3] & 0xf4) != 0)) && ((indicator64[2] & 0xfe) != 0xf0 || (indicator64[3] & 0xf4) != 0))
{ {
/* We have a 64 bit copro insn. */ /* We have a 64 bit copro insn. */
corebuflength = 0; corebuflength = 0;
/* All 8 bytes are one copro insn. */ /* All 8 bytes are one copro insn. */
cop1buflength = 8; cop1buflength = 8;
} }
else else
{ {
/* We have a 32 bit core insn and a 32 bit copro insn. */ /* We have a 32 bit core insn and a 32 bit copro insn. */
corebuflength = 4; corebuflength = 4;
cop1buflength = 4; cop1buflength = 4;
} }
} }
else else
@@ -1290,10 +1289,10 @@ print_slot_insn (CGEN_CPU_DESC cd,
if ((CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG) if ((CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG)
&& CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG) != MEP_CONFIG) && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG) != MEP_CONFIG)
|| ! (CGEN_ATTR_CGEN_INSN_SLOTS_VALUE (CGEN_INSN_ATTRS (insn)) & (1 << slot))) || ! (CGEN_ATTR_CGEN_INSN_SLOTS_VALUE (CGEN_INSN_ATTRS (insn)) & (1 << slot)))
{ {
insn_list = CGEN_DIS_NEXT_INSN (insn_list); insn_list = CGEN_DIS_NEXT_INSN (insn_list);
continue; continue;
} }
if ((insn_value & CGEN_INSN_BASE_MASK (insn)) if ((insn_value & CGEN_INSN_BASE_MASK (insn))
== CGEN_INSN_BASE_VALUE (insn)) == CGEN_INSN_BASE_VALUE (insn))

9
opcodes/mep-asm.c
View File

@@ -638,10 +638,10 @@ expand_macro (arg *args, int narg, const macro *mac)
/* printf("expanding macro %s with %d args\n", mac->name, narg + 1); */ /* printf("expanding macro %s with %d args\n", mac->name, narg + 1); */
while (*e) while (*e)
{ {
if (*e == '`' && if (*e == '`'
(*e+1) && && (*e+1)
((*(e + 1) - '1') <= MAXARGS) && && ((*(e + 1) - '1') <= MAXARGS)
((*(e + 1) - '1') <= narg)) && ((*(e + 1) - '1') <= narg))
{ {
result = str_append (result, mark, e - mark); result = str_append (result, mark, e - mark);
mac_arg = (*(e + 1) - '1'); mac_arg = (*(e + 1) - '1');
@@ -759,7 +759,6 @@ expand_string (const char *in, int first_only)
if (narg > -1) if (narg > -1)
args[narg].len++; args[narg].len++;
} }
} }
++in; ++in;
} }

34
opcodes/mep-dis.c
View File

@@ -154,8 +154,8 @@ mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info,
} }
status += my_status; status += my_status;
/* Print the + to indicate that the following copro insn is */ /* Print the + to indicate that the following copro insn is
/* part of a vliw group. */ part of a vliw group. */
if (copro1length > 0) if (copro1length > 0)
(*info->fprintf_func) (info->stream, " + "); (*info->fprintf_func) (info->stream, " + ");
} }
@@ -336,16 +336,16 @@ mep_examine_vliw32_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
{ {
if ((indicatorcop32[0] & 0xf0) == 0xf0 && (indicatorcop32[1] & 0x07) == 0x07) if ((indicatorcop32[0] & 0xf0) == 0xf0 && (indicatorcop32[1] & 0x07) == 0x07)
{ {
/* We have a 32 bit copro insn. */ /* We have a 32 bit copro insn. */
corebuflength = 0; corebuflength = 0;
/* All 4 4ytes are one copro insn. */ /* All 4 4ytes are one copro insn. */
cop1buflength = 4; cop1buflength = 4;
} }
else else
{ {
/* We have a 32 bit core. */ /* We have a 32 bit core. */
corebuflength = 4; corebuflength = 4;
cop1buflength = 0; cop1buflength = 0;
} }
} }
else else
@@ -425,16 +425,16 @@ mep_examine_vliw64_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
if ((indicator64[0] & 0xf0) == 0xf0 && (indicator64[1] & 0x07) == 0x07 if ((indicator64[0] & 0xf0) == 0xf0 && (indicator64[1] & 0x07) == 0x07
&& ((indicator64[2] & 0xfe) != 0xf0 || (indicator64[3] & 0xf4) != 0)) && ((indicator64[2] & 0xfe) != 0xf0 || (indicator64[3] & 0xf4) != 0))
{ {
/* We have a 64 bit copro insn. */ /* We have a 64 bit copro insn. */
corebuflength = 0; corebuflength = 0;
/* All 8 bytes are one copro insn. */ /* All 8 bytes are one copro insn. */
cop1buflength = 8; cop1buflength = 8;
} }
else else
{ {
/* We have a 32 bit core insn and a 32 bit copro insn. */ /* We have a 32 bit core insn and a 32 bit copro insn. */
corebuflength = 4; corebuflength = 4;
cop1buflength = 4; cop1buflength = 4;
} }
} }
else else
@@ -486,10 +486,10 @@ print_slot_insn (CGEN_CPU_DESC cd,
if ((CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG) if ((CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG)
&& CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG) != MEP_CONFIG) && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG) != MEP_CONFIG)
|| ! (CGEN_ATTR_CGEN_INSN_SLOTS_VALUE (CGEN_INSN_ATTRS (insn)) & (1 << slot))) || ! (CGEN_ATTR_CGEN_INSN_SLOTS_VALUE (CGEN_INSN_ATTRS (insn)) & (1 << slot)))
{ {
insn_list = CGEN_DIS_NEXT_INSN (insn_list); insn_list = CGEN_DIS_NEXT_INSN (insn_list);
continue; continue;
} }
if ((insn_value & CGEN_INSN_BASE_MASK (insn)) if ((insn_value & CGEN_INSN_BASE_MASK (insn))
== CGEN_INSN_BASE_VALUE (insn)) == CGEN_INSN_BASE_VALUE (insn))