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sim: mips: fix -Wimplicit-fallthrough warnings

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Seems like these cases were meant to fallthru.
This commit is contained in:
Mike Frysinger
2023-12-21 01:34:54 -05:00
parent 80200ef6b4
commit 28c06ff1a1
3 changed files with 13 additions and 1 deletions
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4
sim/mips/cp1.c
View File

@@ -262,6 +262,7 @@ store_fpr (sim_cpu *cpu,
{ {
case fmt_uninterpreted_32: case fmt_uninterpreted_32:
fmt = fmt_uninterpreted; fmt = fmt_uninterpreted;
ATTRIBUTE_FALLTHROUGH;
case fmt_single: case fmt_single:
case fmt_word: case fmt_word:
if (STATE_VERBOSE_P (SD)) if (STATE_VERBOSE_P (SD))
@@ -274,6 +275,7 @@ store_fpr (sim_cpu *cpu,
case fmt_uninterpreted_64: case fmt_uninterpreted_64:
fmt = fmt_uninterpreted; fmt = fmt_uninterpreted;
ATTRIBUTE_FALLTHROUGH;
case fmt_uninterpreted: case fmt_uninterpreted:
case fmt_double: case fmt_double:
case fmt_long: case fmt_long:
@@ -294,6 +296,7 @@ store_fpr (sim_cpu *cpu,
{ {
case fmt_uninterpreted_32: case fmt_uninterpreted_32:
fmt = fmt_uninterpreted; fmt = fmt_uninterpreted;
ATTRIBUTE_FALLTHROUGH;
case fmt_single: case fmt_single:
case fmt_word: case fmt_word:
FGR[fpr] = (value & 0xFFFFFFFF); FGR[fpr] = (value & 0xFFFFFFFF);
@@ -302,6 +305,7 @@ store_fpr (sim_cpu *cpu,
case fmt_uninterpreted_64: case fmt_uninterpreted_64:
fmt = fmt_uninterpreted; fmt = fmt_uninterpreted;
ATTRIBUTE_FALLTHROUGH;
case fmt_uninterpreted: case fmt_uninterpreted:
case fmt_double: case fmt_double:
case fmt_long: case fmt_long:

4
sim/mips/interp.c
View File

@@ -1247,7 +1247,7 @@ sim_monitor (SIM_DESC sd,
if (A0 == 0) /* waitflag == NOWAIT */ if (A0 == 0) /* waitflag == NOWAIT */
V0 = (unsigned_word)-1; V0 = (unsigned_word)-1;
} }
/* Drop through to case 11 */ ATTRIBUTE_FALLTHROUGH;
case 11: /* char inbyte(void) */ case 11: /* char inbyte(void) */
{ {
@@ -1904,6 +1904,7 @@ signal_exception (SIM_DESC sd,
} }
/* else fall through to normal exception processing */ /* else fall through to normal exception processing */
sim_io_eprintf(sd,"ReservedInstruction at PC = 0x%s\n", pr_addr (cia)); sim_io_eprintf(sd,"ReservedInstruction at PC = 0x%s\n", pr_addr (cia));
ATTRIBUTE_FALLTHROUGH;
} }
default: default:
@@ -2329,6 +2330,7 @@ decode_coproc (SIM_DESC sd,
"Warning: PC 0x%lx:interp.c decode_coproc DEADC0DE\n", "Warning: PC 0x%lx:interp.c decode_coproc DEADC0DE\n",
(unsigned long)cia); (unsigned long)cia);
GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */ GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */
ATTRIBUTE_FALLTHROUGH;
/* CPR[0,rd] = GPR[rt]; */ /* CPR[0,rd] = GPR[rt]; */
default: default:
if (op == cp0_mfc0 || op == cp0_dmfc0) if (op == cp0_mfc0 || op == cp0_dmfc0)

6
sim/mips/m16e.igen
View File

@@ -212,16 +212,22 @@
switch (xsregs) { switch (xsregs) {
case 7: case 7:
do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[30]); do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[30]);
ATTRIBUTE_FALLTHROUGH;
case 6: case 6:
do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[23]); do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[23]);
ATTRIBUTE_FALLTHROUGH;
case 5: case 5:
do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[22]); do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[22]);
ATTRIBUTE_FALLTHROUGH;
case 4: case 4:
do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[21]); do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[21]);
ATTRIBUTE_FALLTHROUGH;
case 3: case 3:
do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[20]); do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[20]);
ATTRIBUTE_FALLTHROUGH;
case 2: case 2:
do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[19]); do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[19]);
ATTRIBUTE_FALLTHROUGH;
case 1: case 1:
do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[18]); do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[18]);
} }