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RISC-V: PR33216, Allow c.slli, c.srai, c.srli with 0 immediate as a hint

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The original patch,
e6f372ba66

Since recently c.slli64, c.srai64, and c.srli64 have been removed from the
riscv-isa-manual, c.slli, c.srli, and c.srai with 0 immediate are now listed
as hints,
https://github.com/riscv/riscv-isa-manual/pull/1942 and https://github.com/riscv/riscv-isa-manual/pull/2093

So allow c.slli, c.srli, and c.srai with 0 immediate as a hint.  Also allow to
assemble slli, srli and srai with 0 immediate to hint c.slli, c.srli and c.srai
when rvc is enabled.  The c.slli64, c.srai64, and c.srli64 should be kept as
aliases, so dis-assembler should disassemble to c.slli, c.srli, and c.srai with
0 immediate.

Passed rv32/64-elf/linux binutils testcases.

gas/
	PR 33216
	* testsuite/gas/riscv/c-zero-imm.d: Updated since allow c.slli64,
	c.srai64, and c.srli64 with 0 immediate as a hint.
	* testsuite/gas/riscv/c-zero-imm.s: Likewise.
	* testsuite/gas/riscv/zca.d: Likewise.
opcodes/
	PR 33216
	* riscv-opc.c (riscv_opcodes): Updated since allow c.slli64, c.srai64,
	and c.srli64 with 0 immediate as a hint.
This commit is contained in:
Nelson Chu
2025-07-29 12:45:28 +08:00
parent ad9f79ec39
commit 28520d7eed
4 changed files with 20 additions and 45 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
gas/testsuite/gas/riscv/c-zero-imm.d
View File

@@ -14,10 +14,10 @@ Disassembly of section .text:
[ ]+8:[ ]+0001[ ]+nop [ ]+8:[ ]+0001[ ]+nop
[ ]+a:[ ]+873a[ ]+mv[ ]+a4,a4 [ ]+a:[ ]+873a[ ]+mv[ ]+a4,a4
[ ]+c:[ ]+0781[ ]+addi[ ]+a5,a5,0 [ ]+c:[ ]+0781[ ]+addi[ ]+a5,a5,0
[ ]+e:[ ]+00051513[ ]+slli[ ]+a0,a0,0x0 [ ]+e:[ ]+0502[ ]+slli[ ]+a0,a0,0x0
[ ]+12:[ ]+0005d593[ ]+srli[ ]+a1,a1,0x0 [ ]+10:[ ]+8181[ ]+srli[ ]+a1,a1,0x0
[ ]+16:[ ]+40065613[ ]+srai[ ]+a2,a2,0x0 [ ]+12:[ ]+8601[ ]+srai[ ]+a2,a2,0x0
[ ]+1a:[ ]+0682[ ]+c.slli64[ ]+a3 [ ]+14:[ ]+0682[ ]+slli[ ]+a3,a3,0x0
[ ]+1c:[ ]+8301[ ]+c.srli64[ ]+a4 [ ]+16:[ ]+8301[ ]+srli[ ]+a4,a4,0x0
[ ]+1e:[ ]+8781[ ]+c.srai64[ ]+a5 [ ]+18:[ ]+8781[ ]+srai[ ]+a5,a5,0x0
#... #...

2
gas/testsuite/gas/riscv/c-zero-imm.s
View File

@@ -9,7 +9,7 @@
addi a4,a4,0 addi a4,a4,0
# These are hints. # These are hints.
c.addi a5,0 c.addi a5,0
# Don't let these compress to hints. # Allow these compress to hints.
slli a0, a0, 0 slli a0, a0, 0
srli a1, a1, 0 srli a1, a1, 0
srai a2, a2, 0 srai a2, a2, 0

2
gas/testsuite/gas/riscv/zca.d
View File

@@ -45,7 +45,7 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+8c25[ ]+c.xor[ ]+s0,s1 [ ]+[0-9a-f]+:[ ]+8c25[ ]+c.xor[ ]+s0,s1
[ ]+[0-9a-f]+:[ ]+8006[ ]+c.mv[ ]+zero,ra [ ]+[0-9a-f]+:[ ]+8006[ ]+c.mv[ ]+zero,ra
[ ]+[0-9a-f]+:[ ]+0006[ ]+c.slli[ ]+zero,0x1 [ ]+[0-9a-f]+:[ ]+0006[ ]+c.slli[ ]+zero,0x1
[ ]+[0-9a-f]+:[ ]+0002[ ]+c.slli64[ ]+zero [ ]+[0-9a-f]+:[ ]+0002[ ]+c.slli[ ]+zero,0x0
[ ]+[0-9a-f]+:[ ]+d845[ ]+c.beqz[ ]+s0,0[ ]+\<target\> [ ]+[0-9a-f]+:[ ]+d845[ ]+c.beqz[ ]+s0,0[ ]+\<target\>
[ ]+[0-9a-f]+:[ ]+f45d[ ]+c.bnez[ ]+s0,0[ ]+\<target\> [ ]+[0-9a-f]+:[ ]+f45d[ ]+c.bnez[ ]+s0,0[ ]+\<target\>
[ ]+[0-9a-f]+:[ ]+b775[ ]+c.j[ ]+0[ ]+\<target\> [ ]+[0-9a-f]+:[ ]+b775[ ]+c.j[ ]+0[ ]+\<target\>

49
opcodes/riscv-opc.c
View File

@@ -313,22 +313,6 @@ match_c_addi4spn (const struct riscv_opcode *op, insn_t insn)
return match_opcode (op, insn) && EXTRACT_CIWTYPE_ADDI4SPN_IMM (insn) != 0; return match_opcode (op, insn) && EXTRACT_CIWTYPE_ADDI4SPN_IMM (insn) != 0;
} }
/* This requires a non-zero shift. A zero rd is a hint, so is allowed. */
static int
match_c_slli (const struct riscv_opcode *op, insn_t insn)
{
return match_opcode (op, insn) && EXTRACT_CITYPE_IMM (insn) != 0;
}
/* This requires a non-zero rd, and a non-zero shift. */
static int
match_slli_as_c_slli (const struct riscv_opcode *op, insn_t insn)
{
return match_rd_nonzero (op, insn) && EXTRACT_CITYPE_IMM (insn) != 0;
}
/* This requires a zero shift. A zero rd is a hint, so is allowed. */ /* This requires a zero shift. A zero rd is a hint, so is allowed. */
static int static int
@@ -337,15 +321,6 @@ match_c_slli64 (const struct riscv_opcode *op, insn_t insn)
return match_opcode (op, insn) && EXTRACT_CITYPE_IMM (insn) == 0; return match_opcode (op, insn) && EXTRACT_CITYPE_IMM (insn) == 0;
} }
/* This is used for both srli and srai. This requires a non-zero shift.
A zero rd is not possible. */
static int
match_srxi_as_c_srxi (const struct riscv_opcode *op, insn_t insn)
{
return match_opcode (op, insn) && EXTRACT_CITYPE_IMM (insn) != 0;
}
static int static int
match_vs1_eq_vs2 (const struct riscv_opcode *op, match_vs1_eq_vs2 (const struct riscv_opcode *op,
insn_t insn) insn_t insn)
@@ -577,19 +552,19 @@ const struct riscv_opcode riscv_opcodes[] =
{"mips.ehb", 0, INSN_CLASS_XMIPSEXECTL, "", MATCH_MIPS_EHB, MASK_MIPS_EHB, match_opcode, 0 }, {"mips.ehb", 0, INSN_CLASS_XMIPSEXECTL, "", MATCH_MIPS_EHB, MASK_MIPS_EHB, match_opcode, 0 },
{"mips.ihb", 0, INSN_CLASS_XMIPSEXECTL, "", MATCH_MIPS_IHB, MASK_MIPS_IHB, match_opcode, 0 }, {"mips.ihb", 0, INSN_CLASS_XMIPSEXECTL, "", MATCH_MIPS_IHB, MASK_MIPS_IHB, match_opcode, 0 },
{"mips.pause", 0, INSN_CLASS_XMIPSEXECTL, "", MATCH_MIPS_PAUSE, MASK_MIPS_PAUSE, match_opcode, 0 }, {"mips.pause", 0, INSN_CLASS_XMIPSEXECTL, "", MATCH_MIPS_PAUSE, MASK_MIPS_PAUSE, match_opcode, 0 },
{"slli", 0, INSN_CLASS_ZCA, "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_slli_as_c_slli, INSN_ALIAS }, {"slli", 0, INSN_CLASS_ZCA, "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, INSN_ALIAS },
{"slli", 0, INSN_CLASS_I, "d,s,>", MATCH_SLLI, MASK_SLLI, match_opcode, 0 }, {"slli", 0, INSN_CLASS_I, "d,s,>", MATCH_SLLI, MASK_SLLI, match_opcode, 0 },
{"sll", 0, INSN_CLASS_ZCA, "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_slli_as_c_slli, INSN_ALIAS }, {"sll", 0, INSN_CLASS_ZCA, "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, INSN_ALIAS },
{"sll", 0, INSN_CLASS_I, "d,s,t", MATCH_SLL, MASK_SLL, match_opcode, 0 }, {"sll", 0, INSN_CLASS_I, "d,s,t", MATCH_SLL, MASK_SLL, match_opcode, 0 },
{"sll", 0, INSN_CLASS_I, "d,s,>", MATCH_SLLI, MASK_SLLI, match_opcode, INSN_ALIAS }, {"sll", 0, INSN_CLASS_I, "d,s,>", MATCH_SLLI, MASK_SLLI, match_opcode, INSN_ALIAS },
{"srli", 0, INSN_CLASS_ZCA, "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_srxi_as_c_srxi, INSN_ALIAS }, {"srli", 0, INSN_CLASS_ZCA, "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_rd_nonzero, INSN_ALIAS },
{"srli", 0, INSN_CLASS_I, "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, 0 }, {"srli", 0, INSN_CLASS_I, "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, 0 },
{"srl", 0, INSN_CLASS_ZCA, "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_srxi_as_c_srxi, INSN_ALIAS }, {"srl", 0, INSN_CLASS_ZCA, "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_rd_nonzero, INSN_ALIAS },
{"srl", 0, INSN_CLASS_I, "d,s,t", MATCH_SRL, MASK_SRL, match_opcode, 0 }, {"srl", 0, INSN_CLASS_I, "d,s,t", MATCH_SRL, MASK_SRL, match_opcode, 0 },
{"srl", 0, INSN_CLASS_I, "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, INSN_ALIAS }, {"srl", 0, INSN_CLASS_I, "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, INSN_ALIAS },
{"srai", 0, INSN_CLASS_ZCA, "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_srxi_as_c_srxi, INSN_ALIAS }, {"srai", 0, INSN_CLASS_ZCA, "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_rd_nonzero, INSN_ALIAS },
{"srai", 0, INSN_CLASS_I, "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, 0 }, {"srai", 0, INSN_CLASS_I, "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, 0 },
{"sra", 0, INSN_CLASS_ZCA, "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_srxi_as_c_srxi, INSN_ALIAS }, {"sra", 0, INSN_CLASS_ZCA, "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_rd_nonzero, INSN_ALIAS },
{"sra", 0, INSN_CLASS_I, "d,s,t", MATCH_SRA, MASK_SRA, match_opcode, 0 }, {"sra", 0, INSN_CLASS_I, "d,s,t", MATCH_SRA, MASK_SRA, match_opcode, 0 },
{"sra", 0, INSN_CLASS_I, "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, INSN_ALIAS }, {"sra", 0, INSN_CLASS_I, "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, INSN_ALIAS },
{"sub", 0, INSN_CLASS_ZCA, "Cs,Cw,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, INSN_ALIAS }, {"sub", 0, INSN_CLASS_ZCA, "Cs,Cw,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, INSN_ALIAS },
@@ -1199,12 +1174,12 @@ const struct riscv_opcode riscv_opcodes[] =
{"c.and", 0, INSN_CLASS_ZCA, "Cs,Ct", MATCH_C_AND, MASK_C_AND, match_opcode, 0 }, {"c.and", 0, INSN_CLASS_ZCA, "Cs,Ct", MATCH_C_AND, MASK_C_AND, match_opcode, 0 },
{"c.or", 0, INSN_CLASS_ZCA, "Cs,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, 0 }, {"c.or", 0, INSN_CLASS_ZCA, "Cs,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, 0 },
{"c.xor", 0, INSN_CLASS_ZCA, "Cs,Ct", MATCH_C_XOR, MASK_C_XOR, match_opcode, 0 }, {"c.xor", 0, INSN_CLASS_ZCA, "Cs,Ct", MATCH_C_XOR, MASK_C_XOR, match_opcode, 0 },
{"c.slli", 0, INSN_CLASS_ZCA, "d,C>", MATCH_C_SLLI, MASK_C_SLLI, match_c_slli, 0 }, {"c.slli64", 0, INSN_CLASS_ZCA, "d", MATCH_C_SLLI64, MASK_C_SLLI64, match_c_slli64, INSN_ALIAS },
{"c.srli", 0, INSN_CLASS_ZCA, "Cs,C>", MATCH_C_SRLI, MASK_C_SRLI, match_c_slli, 0 }, {"c.srli64", 0, INSN_CLASS_ZCA, "Cs", MATCH_C_SRLI64, MASK_C_SRLI64, match_c_slli64, INSN_ALIAS },
{"c.srai", 0, INSN_CLASS_ZCA, "Cs,C>", MATCH_C_SRAI, MASK_C_SRAI, match_c_slli, 0 }, {"c.srai64", 0, INSN_CLASS_ZCA, "Cs", MATCH_C_SRAI64, MASK_C_SRAI64, match_c_slli64, INSN_ALIAS },
{"c.slli64", 0, INSN_CLASS_ZCA, "d", MATCH_C_SLLI64, MASK_C_SLLI64, match_c_slli64, 0 }, {"c.slli", 0, INSN_CLASS_ZCA, "d,C>", MATCH_C_SLLI, MASK_C_SLLI, match_opcode, 0 },
{"c.srli64", 0, INSN_CLASS_ZCA, "Cs", MATCH_C_SRLI64, MASK_C_SRLI64, match_c_slli64, 0 }, {"c.srli", 0, INSN_CLASS_ZCA, "Cs,C>", MATCH_C_SRLI, MASK_C_SRLI, match_opcode, 0 },
{"c.srai64", 0, INSN_CLASS_ZCA, "Cs", MATCH_C_SRAI64, MASK_C_SRAI64, match_c_slli64, 0 }, {"c.srai", 0, INSN_CLASS_ZCA, "Cs,C>", MATCH_C_SRAI, MASK_C_SRAI, match_opcode, 0 },
{"c.andi", 0, INSN_CLASS_ZCA, "Cs,Co", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, 0 }, {"c.andi", 0, INSN_CLASS_ZCA, "Cs,Co", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, 0 },
{"c.addiw", 64, INSN_CLASS_ZCA, "d,Co", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, 0 }, {"c.addiw", 64, INSN_CLASS_ZCA, "d,Co", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, 0 },
{"c.addw", 64, INSN_CLASS_ZCA, "Cs,Ct", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, 0 }, {"c.addw", 64, INSN_CLASS_ZCA, "Cs,Ct", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, 0 },