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RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93).

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In fact rev8/orc.b/zext.h are the aliases of grevi/gorci/pack[w], so we
should update them to INSN_ALIAS when we have supported their true instruction
in the future.  Though we still use the [MATCH|MAKS]_[GREVI|GORCI|PACK|PACKW]
to encode them.  Besides, the orc.b has the same encoding both in rv32 and
rv64, so we just keep one of them in the opcode table.

This patch is implemented according to the following link,
https://github.com/riscv/riscv-bitmanip/pull/101

2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
            Jim Wilson  <jimw@sifive.com>
            Andrew Waterman  <andrew@sifive.com>
            Maxim Blinov  <maxim.blinov@embecosm.com>
            Kito Cheng  <kito.cheng@sifive.com>
            Nelson Chu  <nelson.chu@sifive.com>

bfd/
    * elfxx-riscv.c (riscv_std_z_ext_strtab): Added zba, zbb and zbc.
gas/
    * config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_ZB*.
    (riscv_get_default_ext_version): Do not check the default_isa_spec when
    the version defined in the riscv_opcodes table is ISA_SPEC_CLASS_DRAFT.
    * testsuite/gas/riscv/bitmanip-insns-32.d: New testcase.
    * testsuite/gas/riscv/bitmanip-insns-64.d: Likewise.
    * testsuite/gas/riscv/bitmanip-insns.s: Likewise.
include/
    * opcode/riscv-opc.h: Added MASK/MATCH/DECLARE_INSN for ZBA/ZBB/ZBC.
    * opcode/riscv.h (riscv_insn_class): Added INSN_CLASS_ZB*.
    (enum riscv_isa_spec_class): Added ISA_SPEC_CLASS_DRAFT for the
    frozen extensions.
opcodes/
    * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
    (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
This commit is contained in:
Claire Xenia Wolf
2020-12-15 07:11:03 -08:00
committed by Nelson Chu
parent d4e57b87a3
commit 2652cfad8d
12 changed files with 376 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
include/opcode/riscv.h
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@@ -311,6 +311,10 @@ enum riscv_insn_class
INSN_CLASS_D_AND_C,
INSN_CLASS_ZICSR,
INSN_CLASS_ZIFENCEI,
INSN_CLASS_ZBA,
INSN_CLASS_ZBB,
INSN_CLASS_ZBC,
INSN_CLASS_ZBA_OR_ZBB,
};
/* This structure holds information for a particular instruction. */
@@ -353,7 +357,8 @@ enum riscv_isa_spec_class
ISA_SPEC_CLASS_2P2,
ISA_SPEC_CLASS_20190608,
ISA_SPEC_CLASS_20191213
ISA_SPEC_CLASS_20191213,
ISA_SPEC_CLASS_DRAFT
};
#define RISCV_UNKNOWN_VERSION -1