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gas/testsuite/

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2007-09-20  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/sib.s: Add more eiz tests.
	* gas/i386/x86-64-sib.s: Add more riz tests.

	* gas/i386/sib-intel.d: Updated.
	* gas/i386/sib.d: Likewise.
	* gas/i386/x86-64-sib-intel.d: Likewise.
	* gas/i386/x86-64-sib.d: Likewise.

opcodes/

2007-09-20  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (OP_E_extended): Display eiz for [eiz*1 + offset].
This commit is contained in:
H.J. Lu
2007-09-20 20:13:26 +00:00
parent f3b1e08efe
commit 20afcfb756
9 changed files with 219 additions and 1 deletions
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4
opcodes/ChangeLog
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@@ -1,3 +1,7 @@
2007-09-20 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (OP_E_extended): Display eiz for [eiz*1 + offset].
2007-09-20 H.J. Lu <hongjiu.lu@intel.com>
PR 658

12
opcodes/i386-dis.c
View File

@@ -6314,6 +6314,7 @@ OP_E_extended (int bytemode, int sizeflag, int has_drex)
int havesib;
int havebase;
int haveindex;
int needindex;
int base;
int index = 0;
int scale = 0;
@@ -6368,7 +6369,15 @@ OP_E_extended (int bytemode, int sizeflag, int has_drex)
break;
}
havedisp = havebase || (havesib && (haveindex || scale != 0));
/* In 32bit mode, we need index register to tell [offset] from
[eiz*1 + offset]. */
needindex = (havesib
&& !havebase
&& !haveindex
&& address_mode == mode_32bit);
havedisp = (havebase
|| needindex
|| (havesib && (haveindex || scale != 0)));
if (!intel_syntax)
if (modrm.mod != 0 || (base & 7) == 5)
@@ -6402,6 +6411,7 @@ OP_E_extended (int bytemode, int sizeflag, int has_drex)
/* ESP/RSP won't allow index. If base isn't ESP/RSP,
print index to tell base + index from base. */
if (scale != 0
|| needindex
|| haveindex
|| (havebase && base != ESP_REG_NUM))
{