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Remove more shifts for sign/zero extension

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cpu/
	* epiphany.cpu (f-sdisp11): Don't sign extend with shifts.
	* lm32.cpu (f-branch, f-vall): Likewise.
	* m32.cpu (f-lab-8-16): Likewise.
opcodes/
	* arc-dis.c (BITS): Don't truncate high bits with shifts.
	* nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
	* tic54x-dis.c (print_instruction): Likewise.
	* tilegx-opc.c (parse_insn_tilegx): Likewise.
	* tilepro-opc.c (parse_insn_tilepro): Likewise.
	* visium-dis.c (disassem_class0): Likewise.
	* pdp11-dis.c (sign_extend): Likewise.
	(SIGN_BITS): Delete.
	* epiphany-ibld.c: Regenerate.
	* lm32-ibld.c: Regenerate.
	* m32c-ibld.c: Regenerate.
This commit is contained in:
Alan Modra
2019-12-11 16:45:14 +10:30
parent 13c9c48599
commit 1d61b03226
15 changed files with 58 additions and 33 deletions
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8
cpu/lm32.cpu
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@@ -128,11 +128,15 @@
(df f-branch "branch offset field" (PCREL-ADDR) 15 16 INT
((value pc) (sra SI (sub SI value pc) 2))
((value pc) (add SI pc (sra SI (sll SI value 16) 14)))
((value pc) (add SI pc (sub (xor (sll (and value #xffff) 2)
#x20000)
#x20000)))
)
(df f-call "call offset field" (PCREL-ADDR) 25 26 INT
((value pc) (sra SI (sub SI value pc) 2))
((value pc) (add SI pc (sra SI (sll SI value 6) 4)))
((value pc) (add SI pc (sub (xor (sll (and value #x3ffffff) 2)
#x8000000)
#x8000000)))
)