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RISC-V: Fixed wrong imply result for zce when -march=rv32id_zce

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The entry of "zce imply zcf" needs check_implicit_for_zcf, so it needs to be
placed after the entries of "whatever imply f".  Otherwise the implicit zcf
may be missed.  Also merge the march-implu-zce* testcases into imply testcases.
This commit is contained in:
Nelson Chu
2025-07-09 12:53:41 +08:00
parent 34fcc16e79
commit 0e16f1550a
6 changed files with 32 additions and 40 deletions
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18
bfd/elfxx-riscv.c
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@@ -1248,15 +1248,6 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"zvl128b", "+zvl64b", check_implicit_always}, {"zvl128b", "+zvl64b", check_implicit_always},
{"zvl64b", "+zvl32b", check_implicit_always}, {"zvl64b", "+zvl32b", check_implicit_always},
{"zce", "+zca,+zcb,+zcmp,+zcmt", check_implicit_always},
{"zce", "+zcf", check_implicit_for_zcf},
{"zcb", "+zca", check_implicit_always},
{"zcd", "+d,+zca", check_implicit_always},
{"zcf", "+f,+zca", check_implicit_always},
{"zcmp", "+zca", check_implicit_always},
{"zcmop", "+zca", check_implicit_always},
{"zcmt", "+zca,+zicsr", check_implicit_always},
{"zicfilp", "+zicsr", check_implicit_always}, {"zicfilp", "+zicsr", check_implicit_always},
{"zicfiss", "+zimop,+zicsr", check_implicit_always}, {"zicfiss", "+zimop,+zicsr", check_implicit_always},
{"zclsd", "+zca,+zilsd", check_implicit_always}, {"zclsd", "+zca,+zilsd", check_implicit_always},
@@ -1273,6 +1264,9 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"zhinx", "+zhinxmin", check_implicit_always}, {"zhinx", "+zhinxmin", check_implicit_always},
{"zhinxmin", "+zfinx", check_implicit_always}, {"zhinxmin", "+zfinx", check_implicit_always},
{"zcd", "+d,+zca", check_implicit_always},
{"zcf", "+f,+zca", check_implicit_always},
{"q", "+d", check_implicit_always}, {"q", "+d", check_implicit_always},
{"zqinx", "+zdinx", check_implicit_always}, {"zqinx", "+zdinx", check_implicit_always},
@@ -1286,6 +1280,12 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"zfinx", "+zicsr", check_implicit_always}, {"zfinx", "+zicsr", check_implicit_always},
{"f", "+zicsr", check_implicit_always}, {"f", "+zicsr", check_implicit_always},
{"zce", "+zcb,+zcmp,+zcmt", check_implicit_always},
{"zce", "+zcf", check_implicit_for_zcf},
{"zcb", "+zca", check_implicit_always},
{"zcmp", "+zca", check_implicit_always},
{"zcmop", "+zca", check_implicit_always},
{"zcmt", "+zca,+zicsr", check_implicit_always},
{"c", "+zcf", check_implicit_for_zcf}, {"c", "+zcf", check_implicit_for_zcf},
{"c", "+zcd", check_implicit_for_zcd}, {"c", "+zcd", check_implicit_for_zcd},
{"c", "+zca", check_implicit_always}, {"c", "+zca", check_implicit_always},

17
gas/testsuite/gas/riscv/imply.d
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@@ -45,12 +45,6 @@ SYMBOL TABLE:
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_zvl64b1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_zvl64b1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zca1p0_zcb1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_d2p2_zicsr2p0_zca1p0_zcd1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zca1p0_zcf1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zca1p0_zcmp1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zca1p0_zcmop1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zca1p0_zcmt1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicfilp1p0_zicsr2p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicfilp1p0_zicsr2p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicfiss1p0_zicsr2p0_zimop1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicfiss1p0_zicsr2p0_zimop1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_h1p0_zicsr2p0_sha1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssstateen1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_h1p0_zicsr2p0_sha1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssstateen1p0
@@ -63,6 +57,8 @@ SYMBOL TABLE:
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_h1p0_zicsr2p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_h1p0_zicsr2p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zfinx1p0_zhinx1p0_zhinxmin1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zfinx1p0_zhinx1p0_zhinxmin1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zfinx1p0_zhinxmin1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zfinx1p0_zhinxmin1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_d2p2_zicsr2p0_zca1p0_zcd1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zca1p0_zcf1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_d2p2_q2p2_zicsr2p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_d2p2_q2p2_zicsr2p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zfinx1p0_zdinx1p0_zqinx1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zfinx1p0_zdinx1p0_zqinx1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_d2p2_zicsr2p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_d2p2_zicsr2p0
@@ -73,6 +69,15 @@ SYMBOL TABLE:
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zfhmin1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zfhmin1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zfinx1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zfinx1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcf1p0_zcmp1p0_zcmt1p0
[0-9a-f]+ l .text 0+000 \$xrv64i2p1_f2p2_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_d2p2_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcf1p0_zcmp1p0_zcmt1p0
[0-9a-f]+ l .text 0+000 \$xrv64i2p1_f2p2_d2p2_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zca1p0_zcb1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zca1p0_zcmp1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zca1p0_zcmop1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zca1p0_zcmt1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_c2p0_zicsr2p0_zca1p0_zcf1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_c2p0_zicsr2p0_zca1p0_zcf1p0
[0-9a-f]+ l .text 0+000 \$xrv64i2p1_f2p2_c2p0_zicsr2p0_zca1p0 [0-9a-f]+ l .text 0+000 \$xrv64i2p1_f2p2_c2p0_zicsr2p0_zca1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_d2p2_c2p0_zicsr2p0_zca1p0_zcd1p0_zcf1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_d2p2_c2p0_zicsr2p0_zca1p0_zcd1p0_zcf1p0

19
gas/testsuite/gas/riscv/imply.s
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@@ -50,13 +50,6 @@ imply zve32x_zvl256b
imply zve32x_zvl128b imply zve32x_zvl128b
imply zve32x_zvl64b imply zve32x_zvl64b
imply zcb
imply zcd
imply zcf
imply zcmp
imply zcmop
imply zcmt
imply zicfilp imply zicfilp
imply zicfiss imply zicfiss
@@ -72,6 +65,9 @@ imply h
imply zhinx imply zhinx
imply zhinxmin imply zhinxmin
imply zcd
imply zcf
imply q imply q
imply zqinx imply zqinx
@@ -85,6 +81,15 @@ imply zfhmin
imply zfinx imply zfinx
imply f imply f
imply zce,if,32
imply zce,if,64
imply zce,id,32
imply zce,id,64
imply zce
imply zcb
imply zcmp
imply zcmop
imply zcmt
imply c,if,32 imply c,if,32
imply c,if,64 imply c,if,64
imply c,id,32 imply c,id,32

6
gas/testsuite/gas/riscv/march-imply-zce-f-32.d
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@@ -1,6 +0,0 @@
#as: -march=rv32if_zce -march-attr -misa-spec=20191213
#readelf: -A
#source: empty.s
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p1_f2p2_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcf1p0_zcmp1p0_zcmt1p0"

6
gas/testsuite/gas/riscv/march-imply-zce-f-64.d
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@@ -1,6 +0,0 @@
#as: -march=rv64if_zce -march-attr -misa-spec=20191213
#readelf: -A
#source: empty.s
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv64i2p1_f2p2_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0"

6
gas/testsuite/gas/riscv/march-imply-zce.d
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@@ -1,6 +0,0 @@
#as: -march=rv32i_zce -march-attr -misa-spec=20191213
#readelf: -A
#source: empty.s
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p1_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0"