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opcodes cgen: remove use of PTR

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Note that opcodes is regenerated with cgen commit d1dd5fcc38e reverted,
due to failure of bpf to compile with that patch applied.

.../opcodes/bpf-opc.c:57:11: error: conversion from ‘long unsigned int’ to ‘unsigned int’ changes value from ‘18446744073709486335’ to ‘4294902015’ [-Werror=overflow]
   57 |   64, 64, 0xffffffffffff00ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
plus other similar errors.

cpu/
	* mep.opc (print_tpreg, print_spreg): Delete unnecessary
	forward declarations.  Replace PTR with void *.
	* mt.opc (print_dollarhex, print_pcrel): Delete forward decls.
opcodes/
	* bpf-desc.c, * bpf-dis.c, * cris-desc.c,
	* epiphany-desc.c, * epiphany-dis.c,
	* fr30-desc.c, * fr30-dis.c, * frv-desc.c, * frv-dis.c,
	* ip2k-desc.c, * ip2k-dis.c, * iq2000-desc.c, * iq2000-dis.c,
	* lm32-desc.c, * lm32-dis.c, * m32c-desc.c, * m32c-dis.c,
	* m32r-desc.c, * m32r-dis.c, * mep-desc.c, * mep-dis.c,
	* mt-desc.c, * mt-dis.c, * or1k-desc.c, * or1k-dis.c,
	* xc16x-desc.c, * xc16x-dis.c,
	* xstormy16-desc.c, * xstormy16-dis.c: Regenerate.
This commit is contained in:
Alan Modra
2022-05-10 08:52:07 +09:30
parent 455f32e3c3
commit 0dfdb5234a
31 changed files with 1286 additions and 1298 deletions
Download Patch File Download Diff File Expand all files Collapse all files

42
opcodes/lm32-desc.c
View File

@@ -224,8 +224,8 @@ const CGEN_HW_ENTRY lm32_cgen_hw_table[] =
{ "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & lm32_cgen_opval_h_gr, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-csr", HW_H_CSR, CGEN_ASM_KEYWORD, (PTR) & lm32_cgen_opval_h_csr, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, & lm32_cgen_opval_h_gr, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-csr", HW_H_CSR, CGEN_ASM_KEYWORD, & lm32_cgen_opval_h_csr, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
};
@@ -276,79 +276,79 @@ const CGEN_OPERAND lm32_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", LM32_OPERAND_PC, HW_H_PC, 0, 0,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_NIL] } },
{ 0, { &lm32_cgen_ifld_table[LM32_F_NIL] } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* r0: register 0 */
{ "r0", LM32_OPERAND_R0, HW_H_GR, 25, 5,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_R0] } },
{ 0, { &lm32_cgen_ifld_table[LM32_F_R0] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* r1: register 1 */
{ "r1", LM32_OPERAND_R1, HW_H_GR, 20, 5,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_R1] } },
{ 0, { &lm32_cgen_ifld_table[LM32_F_R1] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* r2: register 2 */
{ "r2", LM32_OPERAND_R2, HW_H_GR, 15, 5,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_R2] } },
{ 0, { &lm32_cgen_ifld_table[LM32_F_R2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* shift: shift amout */
{ "shift", LM32_OPERAND_SHIFT, HW_H_UINT, 4, 5,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_SHIFT] } },
{ 0, { &lm32_cgen_ifld_table[LM32_F_SHIFT] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* imm: signed immediate */
{ "imm", LM32_OPERAND_IMM, HW_H_SINT, 15, 16,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
{ 0, { &lm32_cgen_ifld_table[LM32_F_IMM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* uimm: unsigned immediate */
{ "uimm", LM32_OPERAND_UIMM, HW_H_UINT, 15, 16,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_UIMM] } },
{ 0, { &lm32_cgen_ifld_table[LM32_F_UIMM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* branch: branch offset */
{ "branch", LM32_OPERAND_BRANCH, HW_H_IADDR, 15, 16,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_BRANCH] } },
{ 0, { &lm32_cgen_ifld_table[LM32_F_BRANCH] } },
{ 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* call: call offset */
{ "call", LM32_OPERAND_CALL, HW_H_IADDR, 25, 26,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_CALL] } },
{ 0, { &lm32_cgen_ifld_table[LM32_F_CALL] } },
{ 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* csr: csr */
{ "csr", LM32_OPERAND_CSR, HW_H_CSR, 25, 5,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_CSR] } },
{ 0, { &lm32_cgen_ifld_table[LM32_F_CSR] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* user: user */
{ "user", LM32_OPERAND_USER, HW_H_UINT, 10, 11,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_USER] } },
{ 0, { &lm32_cgen_ifld_table[LM32_F_USER] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* exception: exception */
{ "exception", LM32_OPERAND_EXCEPTION, HW_H_UINT, 25, 26,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_EXCEPTION] } },
{ 0, { &lm32_cgen_ifld_table[LM32_F_EXCEPTION] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* hi16: high 16-bit immediate */
{ "hi16", LM32_OPERAND_HI16, HW_H_UINT, 15, 16,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_UIMM] } },
{ 0, { &lm32_cgen_ifld_table[LM32_F_UIMM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* lo16: low 16-bit immediate */
{ "lo16", LM32_OPERAND_LO16, HW_H_UINT, 15, 16,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_UIMM] } },
{ 0, { &lm32_cgen_ifld_table[LM32_F_UIMM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* gp16: gp relative 16-bit immediate */
{ "gp16", LM32_OPERAND_GP16, HW_H_SINT, 15, 16,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
{ 0, { &lm32_cgen_ifld_table[LM32_F_IMM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* got16: got 16-bit immediate */
{ "got16", LM32_OPERAND_GOT16, HW_H_SINT, 15, 16,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
{ 0, { &lm32_cgen_ifld_table[LM32_F_IMM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* gotoffhi16: got offset high 16-bit immediate */
{ "gotoffhi16", LM32_OPERAND_GOTOFFHI16, HW_H_SINT, 15, 16,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
{ 0, { &lm32_cgen_ifld_table[LM32_F_IMM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* gotofflo16: got offset low 16-bit immediate */
{ "gotofflo16", LM32_OPERAND_GOTOFFLO16, HW_H_SINT, 15, 16,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
{ 0, { &lm32_cgen_ifld_table[LM32_F_IMM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* sentinel */
{ 0, 0, 0, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } }
};