FreeRTOS Source files:

+ Updated all ARM Cortex-M0 ports to include an additional ISB instruction as the scheduler is started.

Demo app files:
+ Fixex build issues in XMC1000 demos.

FreeRTOS/Source/portable/GCC/ARM_CM0/port.c

@@ -183,6 +183,7 @@ void vPortStartFirstTask( void )
 	"	msr psp, r0					\n" /* This is now the new top of stack to use in the task. */
 	"	movs r0, #2					\n" /* Switch to the psp stack. */
 	"	msr CONTROL, r0				\n"
+	"	isb							\n"
 	"	pop {r0-r5}					\n" /* Pop the registers that are saved automatically. */
 	"	mov lr, r5					\n" /* lr is now in r5. */
 	"	cpsie i						\n" /* The first task has its context and interrupts can be enabled. */

FreeRTOS/Source/portable/IAR/ARM_CM0/portasm.s

@@ -149,6 +149,7 @@ vPortStartFirstTask
 	msr psp, r0				/* This is now the new top of stack to use in the task. */
 	movs r0, #2				/* Switch to the psp stack. */
 	msr CONTROL, r0
+	isb
 	pop {r0-r5}				/* Pop the registers that are saved automatically. */
 	mov lr, r5				/* lr is now in r5. */
 	cpsie i					/* The first task has its context and interrupts can be enabled. */

FreeRTOS/Source/portable/RVDS/ARM_CM0/port.c

@@ -181,6 +181,7 @@ __asm void prvPortStartFirstTask( void )
 	msr psp, r0				/* This is now the new top of stack to use in the task. */
 	movs r0, #2				/* Switch to the psp stack. */
 	msr CONTROL, r0
+	isb
 	pop {r0-r5}				/* Pop the registers that are saved automatically. */
 	mov lr, r5				/* lr is now in r5. */
 	cpsie i					/* The first task has its context and interrupts can be enabled. */