#include "r_cg_macrodriver.h"
#include "r_cg_userdefine.h"
@@ -148,30 +153,26 @@
#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )
#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )
#define mainUART_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3UL )
-#define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY )
/* The priority used by the UART command console task. */
#define mainUART_COMMAND_CONSOLE_TASK_PRIORITY ( configMAX_PRIORITIES - 2 )
-/* A block time of zero simply means "don't block". */
-#define mainDONT_BLOCK ( 0UL )
-
/* The period after which the check timer will expire, in ms, provided no errors
have been reported by any of the standard demo tasks. ms are converted to the
equivalent in ticks using the portTICK_PERIOD_MS constant. */
-#define mainNO_ERROR_CHECK_TASK_PERIOD ( 3000UL / portTICK_PERIOD_MS )
+#define mainNO_ERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( 3000UL )
/* The period at which the check timer will expire, in ms, if an error has been
reported in one of the standard demo tasks. ms are converted to the equivalent
in ticks using the portTICK_PERIOD_MS constant. */
-#define mainERROR_CHECK_TASK_PERIOD ( 200UL / portTICK_PERIOD_MS )
+#define mainERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( 200UL )
/* Parameters that are passed into the register check tasks solely for the
purpose of ensuring parameters are passed into tasks correctly. */
-#define mainREG_TEST_1_PARAMETER ( ( void * ) 0x12121212UL )
-#define mainREG_TEST_2_PARAMETER ( ( void * ) 0x12345678UL )
+#define mainREG_TEST_1_PARAMETER ( ( void * ) 0x12121212UL )
+#define mainREG_TEST_2_PARAMETER ( ( void * ) 0x12345678UL )
/* The base period used by the timer test tasks. */
#define mainTIMER_TEST_PERIOD ( 50 )
@@ -212,6 +213,17 @@ static void prvRegTest2Implementation( void );
*/
static void prvPseudoRandomiser( void *pvParameters );
+/*
+ * Register commands that can be used with FreeRTOS+CLI. The commands are
+ * defined in CLI-Commands.c and File-Related-CLI-Command.c respectively.
+ */
+extern void vRegisterSampleCLICommands( void );
+
+/*
+ * The task that manages the FreeRTOS+CLI input and output.
+ */
+extern void vUARTCommandConsoleStart( uint16_t usStackSize, UBaseType_t uxPriority );
+
/*-----------------------------------------------------------*/
/* The following two variables are used to communicate the status of the
@@ -220,9 +232,6 @@ then the register check tasks have not discovered any errors. If a variable
stops incrementing, then an error has been found. */
volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;
-/* String for display in the web server. It is set to an error message if the
-check task detects an error. */
-const char *pcStatusMessage = "All tasks running without error";
/*-----------------------------------------------------------*/
void main_full( void )
@@ -250,7 +259,14 @@ void main_full( void )
xTaskCreate( prvRegTest2Task, "RegTst2", configMINIMAL_STACK_SIZE, mainREG_TEST_2_PARAMETER, tskIDLE_PRIORITY, NULL );
/* Create the task that just adds a little random behaviour. */
- xTaskCreate( prvPseudoRandomiser, "Rnd", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL );
+ xTaskCreate( prvPseudoRandomiser, "Rnd", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 2, NULL );
+
+ /* Start the tasks that implements the command console on the UART, as
+ described above. */
+ vUARTCommandConsoleStart( mainUART_COMMAND_CONSOLE_STACK_SIZE, mainUART_COMMAND_CONSOLE_TASK_PRIORITY );
+
+ /* Register the standard CLI commands. */
+ vRegisterSampleCLICommands();
/* Create the task that performs the 'check' functionality, as described at
the top of this file. */
@@ -404,7 +420,6 @@ unsigned long ulErrorFound = pdFALSE;
gone wrong (it might just be that the loop back connector required
by the comtest tasks has not been fitted). */
xDelayPeriod = mainERROR_CHECK_TASK_PERIOD;
- pcStatusMessage = "Error found in at least one task.";
}
}
}
@@ -412,7 +427,7 @@ unsigned long ulErrorFound = pdFALSE;
static void prvPseudoRandomiser( void *pvParameters )
{
-const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL, ulMinDelay = ( 35 / portTICK_PERIOD_MS );
+const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL, ulMinDelay = pdMS_TO_TICKS( 35 );
volatile uint32_t ulNextRand = ( uint32_t ) &pvParameters, ulValue;
/* This task does nothing other than ensure there is a little bit of
diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_sci_user.c b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_sci_user.c
index 6f4c8bca6..e163cc542 100644
--- a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_sci_user.c
+++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/cg_src/r_cg_sci_user.c
@@ -30,6 +30,16 @@
Pragma directive
***********************************************************************************************************************/
/* Start user code for pragma. Do not edit comment generated here */
+
+
+/*
+ * This file originated from an example project for the RSK - it has been
+ * adapted to allow it to be used in the FreeRTOS demo. Functions required by
+ * UARTCommandConsole.c have been added.
+ */
+
+
+
/* End user code. Do not edit comment generated here */
/***********************************************************************************************************************
@@ -38,6 +48,11 @@ Includes
#include "r_cg_macrodriver.h"
#include "r_cg_sci.h"
/* Start user code for include. Do not edit comment generated here */
+#include "rskrx71mdef.h"
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "serial.h"
/* End user code. Do not edit comment generated here */
#include "r_cg_userdefine.h"
@@ -50,7 +65,6 @@ extern uint8_t * gp_sci7_rx_address; /* SCI7 receive buffer addre
extern uint16_t g_sci7_rx_count; /* SCI7 receive data number */
extern uint16_t g_sci7_rx_length; /* SCI7 receive data length */
/* Start user code for global. Do not edit comment generated here */
-/* Flag used locally to detect transmission complete */
/* Global used to receive a character from the PC terminal */
uint8_t g_rx_char;
@@ -58,8 +72,21 @@ uint8_t g_rx_char;
/* Flag used to control transmission to PC terminal */
volatile uint8_t g_tx_flag = FALSE;
-/* Flag used locally to detect transmission complete */
-static volatile uint8_t sci6_txdone;
+/* Characters received from the UART are stored in this queue, ready to be
+received by the application. ***NOTE*** Using a queue in this way is very
+convenient, but also very inefficient. It can be used here because characters
+will only arrive slowly. In a higher bandwidth system a circular RAM buffer or
+DMA should be used in place of this queue. */
+static QueueHandle_t xRxQueue = NULL;
+
+/* When a task calls vSerialPutString() its handle is stored in xSendingTask,
+before being placed into the Blocked state (so does not use any CPU time) to
+wait for the transmission to end. The task handle is then used from the UART
+transmit end interrupt to remove the task from the Blocked state. */
+static TaskHandle_t xSendingTask = NULL;
+
+/* Flag used locally to detect transmission complete. This is used by the
+auto generated API only. */
static volatile uint8_t sci7_txdone;
/* End user code. Do not edit comment generated here */
@@ -98,7 +125,7 @@ static void r_sci7_transmit_interrupt(void)
***********************************************************************************************************************/
void r_sci7_transmitend_interrupt(void)
{
- /* Set TXD7 pin */
+ MPC.P90PFS.BYTE = 0x00U;
PORT9.PMR.BYTE &= 0xFEU;
SCI7.SCR.BIT.TIE = 0U;
SCI7.SCR.BIT.TE = 0U;
@@ -158,8 +185,20 @@ void r_sci7_receiveerror_interrupt(void)
static void r_sci7_callback_transmitend(void)
{
/* Start user code. Do not edit comment generated here */
+ BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+
+ /* The sci7_txdone flag is used by the auto generated API only. */
sci7_txdone = TRUE;
+ if( xSendingTask != NULL )
+ {
+ /* A task is waiting for the end of the Tx, unblock it now.
+ http://www.freertos.org/vTaskNotifyGiveFromISR.html */
+ vTaskNotifyGiveFromISR( xSendingTask, &xHigherPriorityTaskWoken );
+ xSendingTask = NULL;
+
+ portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ }
/* End user code. Do not edit comment generated here */
}
/***********************************************************************************************************************
@@ -171,15 +210,30 @@ static void r_sci7_callback_transmitend(void)
static void r_sci7_callback_receiveend(void)
{
/* Start user code. Do not edit comment generated here */
- /* Check the contents of g_rx_char */
- if (('c' == g_rx_char) || ('C' == g_rx_char))
+ BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+
+ configASSERT( xRxQueue );
+
+ /* Transmitting generates an interrupt for each character, which consumes
+ CPU time, and can cause standard demo RTOS tasks that monitor their own
+ performance to fail asserts - so don't receive new CLI commands if a
+ transmit is not already in progress. */
+ if( sci7_txdone == TRUE )
{
-//_RB_ g_adc_trigger = TRUE;
+ /* Characters received from the UART are stored in this queue, ready to be
+ received by the application. ***NOTE*** Using a queue in this way is very
+ convenient, but also very inefficient. It can be used here because
+ characters will only arrive slowly. In a higher bandwidth system a circular
+ RAM buffer or DMA should be used in place of this queue. */
+ xQueueSendFromISR( xRxQueue, &g_rx_char, &xHigherPriorityTaskWoken );
}
- /* Set up SCI7 receive buffer and callback function again */
+ /* Set up SCI7 receive buffer again */
R_SCI7_Serial_Receive((uint8_t *)&g_rx_char, 1);
+ /* See http://www.freertos.org/xQueueOverwriteFromISR.html for information
+ on the semantics of this ISR. */
+ portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
/* End user code. Do not edit comment generated here */
}
/***********************************************************************************************************************
@@ -228,5 +282,91 @@ MD_STATUS R_SCI7_AsyncTransmit (uint8_t * const tx_buf, const uint16_t tx_num)
* End of function R_SCI7_AsyncTransmit
*******************************************************************************/
+/* Function required in order to link UARTCommandConsole.c - which is used by
+multiple different demo application. */
+xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
+{
+ ( void ) ulWantedBaud;
+ ( void ) uxQueueLength;
+
+ /* Characters received from the UART are stored in this queue, ready to be
+ received by the application. ***NOTE*** Using a queue in this way is very
+ convenient, but also very inefficient. It can be used here because
+ characters will only arrive slowly. In a higher bandwidth system a circular
+ RAM buffer or DMA should be used in place of this queue. */
+ xRxQueue = xQueueCreate( uxQueueLength, sizeof( char ) );
+ configASSERT( xRxQueue );
+
+ /* Set up SCI1 receive buffer */
+ R_SCI7_Serial_Receive((uint8_t *) &g_rx_char, 1);
+
+ /* Ensure the interrupt priority is at or below
+ configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ IPR(SCI7, RXI7) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1;
+ IPR(SCI7, TXI7) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1;
+ IPR(ICU,GROUPBL0) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1;
+
+ /* Enable SCI1 operations */
+ R_SCI7_Start();
+
+ /* Only one UART is supported, so it doesn't matter what is returned
+ here. */
+ return 0;
+}
+
+/* Function required in order to link UARTCommandConsole.c - which is used by
+multiple different demo application. */
+void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned short usStringLength )
+{
+const TickType_t xMaxBlockTime = pdMS_TO_TICKS( 5000 );
+
+ /* Only one port is supported. */
+ ( void ) pxPort;
+
+ /* Clear the flag before initiating a new transmission */
+ sci7_txdone = FALSE;
+
+ /* Don't send the string unless the previous string has been sent. */
+ if( ( xSendingTask == NULL ) && ( usStringLength > 0 ) )
+ {
+ /* Ensure the calling task's notification state is not already
+ pending. */
+ vTaskNotifyStateClear( NULL );
+
+ /* Store the handle of the transmitting task. This is used to unblock
+ the task when the transmission has completed. */
+ xSendingTask = xTaskGetCurrentTaskHandle();
+
+ /* Send the string using the auto-generated API. */
+ R_SCI7_Serial_Send( ( uint8_t * ) pcString, usStringLength );
+
+ /* Wait in the Blocked state (so not using any CPU time) until the
+ transmission has completed. */
+ ulTaskNotifyTake( pdTRUE, xMaxBlockTime );
+ }
+}
+
+/* Function required in order to link UARTCommandConsole.c - which is used by
+multiple different demo application. */
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, TickType_t xBlockTime )
+{
+ /* Only one UART is supported. */
+ ( void ) pxPort;
+
+ /* Return a received character, if any are available. Otherwise block to
+ wait for a character. */
+ return xQueueReceive( xRxQueue, pcRxedChar, xBlockTime );
+}
+
+/* Function required in order to link UARTCommandConsole.c - which is used by
+multiple different demo application. */
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, TickType_t xBlockTime )
+{
+ /* Just mapped to vSerialPutString() so the block time is not used. */
+ ( void ) xBlockTime;
+
+ vSerialPutString( pxPort, &cOutChar, sizeof( cOutChar ) );
+ return pdPASS;
+}
/* End user code. Do not edit comment generated here */
diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/main.c b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/main.c
index 9cb47b35f..c2f285563 100644
--- a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/main.c
+++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/main.c
@@ -96,7 +96,7 @@
/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,
or 0 to run the more comprehensive test and demo application. */
-#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0
+#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1
/*-----------------------------------------------------------*/
@@ -141,6 +141,7 @@ int main( void )
}
#endif
+ /* Should never get reached. */
return 0;
}
/*-----------------------------------------------------------*/
@@ -202,6 +203,7 @@ volatile size_t xFreeHeapSpace;
void vApplicationTickHook( void )
{
+ /* The tick hook is not used by the blinky demo, but is by the full demo. */
#if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0
{
extern void vFullDemoTickHook( void );
@@ -213,7 +215,9 @@ void vApplicationTickHook( void )
/*-----------------------------------------------------------*/
/* The RX port uses this callback function to configure its tick interrupt.
-This allows the application to choose the tick interrupt source. */
+This allows the application to choose the tick interrupt source.
+***NOTE***: configTICK_VECTOR must be set in FreeRTOSConfig.h to be correct for
+whichever vector is used. */
void vApplicationSetupTimerInterrupt( void )
{
const uint32_t ulEnableRegisterWrite = 0xA50BUL, ulDisableRegisterWrite = 0xA500UL;
diff --git a/FreeRTOS/Source/include/FreeRTOS.h b/FreeRTOS/Source/include/FreeRTOS.h
index d8f969d9f..37e38bcf7 100644
--- a/FreeRTOS/Source/include/FreeRTOS.h
+++ b/FreeRTOS/Source/include/FreeRTOS.h
@@ -819,6 +819,14 @@ V8 if desired. */
#define xList List_t
#endif /* configENABLE_BACKWARD_COMPATIBILITY */
+/* Set configUSE_TASK_FPU_SUPPORT to 0 to omit floating point support even
+if floating point hardware is otherwise supported by the FreeRTOS port in use.
+This constant is not supported by all FreeRTOS ports that include floating
+point support. */
+#ifndef configUSE_TASK_FPU_SUPPORT
+ #define configUSE_TASK_FPU_SUPPORT 1
+#endif
+
#ifdef __cplusplus
}
#endif
diff --git a/FreeRTOS/Source/include/StackMacros.h b/FreeRTOS/Source/include/StackMacros.h
index 915fe209b..32b28e683 100644
--- a/FreeRTOS/Source/include/StackMacros.h
+++ b/FreeRTOS/Source/include/StackMacros.h
@@ -86,28 +86,10 @@
/*-----------------------------------------------------------*/
-#if( configCHECK_FOR_STACK_OVERFLOW == 0 )
-
- /* FreeRTOSConfig.h is not set to check for stack overflows. */
- #define taskFIRST_CHECK_FOR_STACK_OVERFLOW()
- #define taskSECOND_CHECK_FOR_STACK_OVERFLOW()
-
-#endif /* configCHECK_FOR_STACK_OVERFLOW == 0 */
-/*-----------------------------------------------------------*/
-
-#if( configCHECK_FOR_STACK_OVERFLOW == 1 )
-
- /* FreeRTOSConfig.h is only set to use the first method of
- overflow checking. */
- #define taskSECOND_CHECK_FOR_STACK_OVERFLOW()
-
-#endif
-/*-----------------------------------------------------------*/
-
-#if( ( configCHECK_FOR_STACK_OVERFLOW > 0 ) && ( portSTACK_GROWTH < 0 ) )
+#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )
/* Only the current stack state is to be checked. */
- #define taskFIRST_CHECK_FOR_STACK_OVERFLOW() \
+ #define taskCHECK_FOR_STACK_OVERFLOW() \
{ \
/* Is the currently saved stack pointer within the stack limit? */ \
if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack ) \
@@ -116,13 +98,13 @@
} \
}
-#endif /* configCHECK_FOR_STACK_OVERFLOW > 0 */
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
/*-----------------------------------------------------------*/
-#if( ( configCHECK_FOR_STACK_OVERFLOW > 0 ) && ( portSTACK_GROWTH > 0 ) )
+#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )
/* Only the current stack state is to be checked. */
- #define taskFIRST_CHECK_FOR_STACK_OVERFLOW() \
+ #define taskCHECK_FOR_STACK_OVERFLOW() \
{ \
\
/* Is the currently saved stack pointer within the stack limit? */ \
@@ -137,20 +119,18 @@
#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )
- #define taskSECOND_CHECK_FOR_STACK_OVERFLOW() \
- { \
- static const uint8_t ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \
- tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \
- tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \
- tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \
- tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \
- \
- \
- /* Has the extremity of the task stack ever been written over? */ \
- if( memcmp( ( const void * ) pxCurrentTCB->pxStack, ( const void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) \
- { \
- vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
- } \
+ #define taskCHECK_FOR_STACK_OVERFLOW() \
+ { \
+ const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack; \
+ const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5; \
+ \
+ if( ( pulStack[ 0 ] != ulCheckValue ) || \
+ ( pulStack[ 1 ] != ulCheckValue ) || \
+ ( pulStack[ 2 ] != ulCheckValue ) || \
+ ( pulStack[ 3 ] != ulCheckValue ) ) \
+ { \
+ vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
+ } \
}
#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
@@ -158,7 +138,7 @@
#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )
- #define taskSECOND_CHECK_FOR_STACK_OVERFLOW() \
+ #define taskCHECK_FOR_STACK_OVERFLOW() \
{ \
int8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack; \
static const uint8_t ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \
@@ -180,5 +160,12 @@
#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
/*-----------------------------------------------------------*/
+/* Remove stack overflow macro if not being used. */
+#ifndef taskCHECK_FOR_STACK_OVERFLOW
+ #define taskCHECK_FOR_STACK_OVERFLOW()
+#endif
+
+
+
#endif /* STACK_MACROS_H */
diff --git a/FreeRTOS/Source/include/task.h b/FreeRTOS/Source/include/task.h
index deda89492..5ecd9afb7 100644
--- a/FreeRTOS/Source/include/task.h
+++ b/FreeRTOS/Source/include/task.h
@@ -1812,6 +1812,18 @@ void vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPri
*/
uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+/**
+ * task. h
+ * void vTaskNotifyClear( TaskHandle_t xTask );
+ *
+ * Clear the notification state of the task referenced by the handle xTask. The
+ * task's notification value is not altered. Set xTask to NULL to clear the
+ * notification state of the calling task.
+ * \defgroup vTaskNotifyClear vTaskNotifyClear
+ * \ingroup TaskNotifications
+ */
+void vTaskNotifyStateClear( TaskHandle_t xTask );
+
/*-----------------------------------------------------------
* SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES
*----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/IAR/RXv2/port.c b/FreeRTOS/Source/portable/IAR/RXv2/port.c
index 1ba4c92c5..4d5306d8d 100644
--- a/FreeRTOS/Source/portable/IAR/RXv2/port.c
+++ b/FreeRTOS/Source/portable/IAR/RXv2/port.c
@@ -79,7 +79,6 @@
#include "string.h"
/* Hardware specifics. */
-#warning RX600v1 port included chip specific header file here.
#include
/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/MPLAB/PIC32MZ/ISR_Support.h b/FreeRTOS/Source/portable/MPLAB/PIC32MZ/ISR_Support.h
index a5b0fd4a0..612705445 100644
--- a/FreeRTOS/Source/portable/MPLAB/PIC32MZ/ISR_Support.h
+++ b/FreeRTOS/Source/portable/MPLAB/PIC32MZ/ISR_Support.h
@@ -69,9 +69,94 @@
#include "FreeRTOSConfig.h"
-#define portCONTEXT_SIZE 160
-#define portEPC_STACK_LOCATION 152
-#define portSTATUS_STACK_LOCATION 156
+#define portCONTEXT_SIZE 160
+#define portEPC_STACK_LOCATION 152
+#define portSTATUS_STACK_LOCATION 156
+#define portFPCSR_STACK_LOCATION 0
+#define portTASK_HAS_FPU_STACK_LOCATION 0
+#define portFPU_CONTEXT_SIZE 264
+
+/******************************************************************/
+.macro portSAVE_FPU_REGS offset, base
+ /* Macro to assist with saving just the FPU registers to the
+ * specified address and base offset,
+ * offset is a constant, base is the base pointer register */
+
+ sdc1 $f31, \offset + 248(\base)
+ sdc1 $f30, \offset + 240(\base)
+ sdc1 $f29, \offset + 232(\base)
+ sdc1 $f28, \offset + 224(\base)
+ sdc1 $f27, \offset + 216(\base)
+ sdc1 $f26, \offset + 208(\base)
+ sdc1 $f25, \offset + 200(\base)
+ sdc1 $f24, \offset + 192(\base)
+ sdc1 $f23, \offset + 184(\base)
+ sdc1 $f22, \offset + 176(\base)
+ sdc1 $f21, \offset + 168(\base)
+ sdc1 $f20, \offset + 160(\base)
+ sdc1 $f19, \offset + 152(\base)
+ sdc1 $f18, \offset + 144(\base)
+ sdc1 $f17, \offset + 136(\base)
+ sdc1 $f16, \offset + 128(\base)
+ sdc1 $f15, \offset + 120(\base)
+ sdc1 $f14, \offset + 112(\base)
+ sdc1 $f13, \offset + 104(\base)
+ sdc1 $f12, \offset + 96(\base)
+ sdc1 $f11, \offset + 88(\base)
+ sdc1 $f10, \offset + 80(\base)
+ sdc1 $f9, \offset + 72(\base)
+ sdc1 $f8, \offset + 64(\base)
+ sdc1 $f7, \offset + 56(\base)
+ sdc1 $f6, \offset + 48(\base)
+ sdc1 $f5, \offset + 40(\base)
+ sdc1 $f4, \offset + 32(\base)
+ sdc1 $f3, \offset + 24(\base)
+ sdc1 $f2, \offset + 16(\base)
+ sdc1 $f1, \offset + 8(\base)
+ sdc1 $f0, \offset + 0(\base)
+
+ .endm
+
+/******************************************************************/
+.macro portLOAD_FPU_REGS offset, base
+ /* Macro to assist with loading just the FPU registers from the
+ * specified address and base offset, offset is a constant,
+ * base is the base pointer register */
+
+ ldc1 $f0, \offset + 0(\base)
+ ldc1 $f1, \offset + 8(\base)
+ ldc1 $f2, \offset + 16(\base)
+ ldc1 $f3, \offset + 24(\base)
+ ldc1 $f4, \offset + 32(\base)
+ ldc1 $f5, \offset + 40(\base)
+ ldc1 $f6, \offset + 48(\base)
+ ldc1 $f7, \offset + 56(\base)
+ ldc1 $f8, \offset + 64(\base)
+ ldc1 $f9, \offset + 72(\base)
+ ldc1 $f10, \offset + 80(\base)
+ ldc1 $f11, \offset + 88(\base)
+ ldc1 $f12, \offset + 96(\base)
+ ldc1 $f13, \offset + 104(\base)
+ ldc1 $f14, \offset + 112(\base)
+ ldc1 $f15, \offset + 120(\base)
+ ldc1 $f16, \offset + 128(\base)
+ ldc1 $f17, \offset + 136(\base)
+ ldc1 $f18, \offset + 144(\base)
+ ldc1 $f19, \offset + 152(\base)
+ ldc1 $f20, \offset + 160(\base)
+ ldc1 $f21, \offset + 168(\base)
+ ldc1 $f22, \offset + 176(\base)
+ ldc1 $f23, \offset + 184(\base)
+ ldc1 $f24, \offset + 192(\base)
+ ldc1 $f25, \offset + 200(\base)
+ ldc1 $f26, \offset + 208(\base)
+ ldc1 $f27, \offset + 216(\base)
+ ldc1 $f28, \offset + 224(\base)
+ ldc1 $f29, \offset + 232(\base)
+ ldc1 $f30, \offset + 240(\base)
+ ldc1 $f31, \offset + 248(\base)
+
+ .endm
/******************************************************************/
.macro portSAVE_CONTEXT
@@ -81,10 +166,37 @@
captured. */
mfc0 k0, _CP0_CAUSE
addiu sp, sp, -portCONTEXT_SIZE
+
+ #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+ /* Test if we are already using the system stack. Only tasks may use the
+ FPU so if we are already in a nested interrupt then the FPU context does
+ not require saving. */
+ la k1, uxInterruptNesting
+ lw k1, 0(k1)
+ bne k1, zero, 2f
+ nop
+
+ /* Test if the current task needs the FPU context saving. */
+ la k1, ulTaskHasFPUContext
+ lw k1, 0(k1)
+ beq k1, zero, 1f
+ nop
+
+ /* Adjust the stack to account for the additional FPU context.*/
+ addiu sp, sp, -portFPU_CONTEXT_SIZE
+
+ 1:
+ /* Save the ulTaskHasFPUContext flag. */
+ sw k1, portTASK_HAS_FPU_STACK_LOCATION(sp)
+
+ 2:
+ #endif
+
mfc0 k1, _CP0_STATUS
- /* Also save s6 and s5 so they can be used. Any nesting interrupts should
- maintain the values of these registers across the ISR. */
+ /* Also save s7, s6 and s5 so they can be used. Any nesting interrupts
+ should maintain the values of these registers across the ISR. */
+ sw s7, 48(sp)
sw s6, 44(sp)
sw s5, 40(sp)
sw k1, portSTATUS_STACK_LOCATION(sp)
@@ -173,6 +285,29 @@
mflo s6, $ac0
sw s6, 8(s5)
+ /* Save the FPU context if the nesting count was zero. */
+ #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+ la s6, uxInterruptNesting
+ lw s6, 0(s6)
+ addiu s6, s6, -1
+ bne s6, zero, 1f
+ nop
+
+ /* Test if the current task needs the FPU context saving. */
+ lw s6, portTASK_HAS_FPU_STACK_LOCATION(s5)
+ beq s6, zero, 1f
+ nop
+
+ /* Save the FPU registers. */
+ portSAVE_FPU_REGS ( portCONTEXT_SIZE + 8 ), s5
+
+ /* Save the FPU status register */
+ cfc1 s6, $f31
+ sw s6, (portCONTEXT_SIZE + portFPCSR_STACK_LOCATION)(s5)
+
+ 1:
+ #endif
+
/* Update the task stack pointer value if nesting is zero. */
la s6, uxInterruptNesting
lw s6, (s6)
@@ -199,8 +334,24 @@
la s6, uxSavedTaskStackPointer
lw s5, (s6)
+ #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+ /* Restore the FPU context if required. */
+ lw s6, portTASK_HAS_FPU_STACK_LOCATION(s5)
+ beq s6, zero, 1f
+ nop
+
+ /* Restore the FPU registers. */
+ portLOAD_FPU_REGS ( portCONTEXT_SIZE + 8 ), s5
+
+ /* Restore the FPU status register. */
+ lw s6, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )(s5)
+ ctc1 s6, $f31
+ #endif
+
+1:
+
/* Restore the context. */
-1: lw s6, 128(s5)
+ lw s6, 128(s5)
mthi s6, $ac1
lw s6, 124(s5)
mtlo s6, $ac1
@@ -213,7 +364,7 @@
lw s6, 144(s5)
mthi s6, $ac3
lw s6, 140(s5)
- mtlo s6, $ac3
+ mtlo s6, $ac3
/* Restore DSPControl. */
lw s6, 148(s5)
@@ -227,6 +378,7 @@
/* s6 is loaded as it was used as a scratch register and therefore saved
as part of the interrupt context. */
+ lw s7, 48(s5)
lw s6, 44(s5)
lw v0, 52(s5)
lw v1, 56(s5)
@@ -257,14 +409,60 @@
addiu k1, k1, -1
sw k1, 0(k0)
- lw k0, portSTATUS_STACK_LOCATION(s5)
- lw k1, portEPC_STACK_LOCATION(s5)
+ #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+ /* If the nesting count is now zero then the FPU context may be restored. */
+ bne k1, zero, 1f
+ nop
- /* Leave the stack in its original state. First load sp from s5, then
- restore s5 from the stack. */
- add sp, zero, s5
- lw s5, 40(sp)
- addiu sp, sp, portCONTEXT_SIZE
+ /* Restore the value of ulTaskHasFPUContext */
+ la k0, ulTaskHasFPUContext
+ lw k1, 0(s5)
+ sw k1, 0(k0)
+
+ /* If the task does not have an FPU context then adjust the stack normally. */
+ beq k1, zero, 1f
+ nop
+
+ /* Restore the STATUS and EPC registers */
+ lw k0, portSTATUS_STACK_LOCATION(s5)
+ lw k1, portEPC_STACK_LOCATION(s5)
+
+ /* Leave the stack in its original state. First load sp from s5, then
+ restore s5 from the stack. */
+ add sp, zero, s5
+ lw s5, 40(sp)
+
+ /* Adjust the stack pointer to remove the FPU context */
+ addiu sp, sp, portFPU_CONTEXT_SIZE
+ beq zero, zero, 2f
+ nop
+
+ 1: /* Restore the STATUS and EPC registers */
+ lw k0, portSTATUS_STACK_LOCATION(s5)
+ lw k1, portEPC_STACK_LOCATION(s5)
+
+ /* Leave the stack in its original state. First load sp from s5, then
+ restore s5 from the stack. */
+ add sp, zero, s5
+ lw s5, 40(sp)
+
+ 2: /* Adjust the stack pointer */
+ addiu sp, sp, portCONTEXT_SIZE
+
+ #else
+
+ /* Restore the frame when there is no hardware FP support. */
+ lw k0, portSTATUS_STACK_LOCATION(s5)
+ lw k1, portEPC_STACK_LOCATION(s5)
+
+ /* Leave the stack in its original state. First load sp from s5, then
+ restore s5 from the stack. */
+ add sp, zero, s5
+ lw s5, 40(sp)
+
+ addiu sp, sp, portCONTEXT_SIZE
+
+ #endif // ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
mtc0 k0, _CP0_STATUS
mtc0 k1, _CP0_EPC
diff --git a/FreeRTOS/Source/portable/MPLAB/PIC32MZ/port.c b/FreeRTOS/Source/portable/MPLAB/PIC32MZ/port.c
index db1686731..26d7e857a 100644
--- a/FreeRTOS/Source/portable/MPLAB/PIC32MZ/port.c
+++ b/FreeRTOS/Source/portable/MPLAB/PIC32MZ/port.c
@@ -93,6 +93,8 @@
#define portIE_BIT ( 0x00000001 )
#define portEXL_BIT ( 0x00000002 )
#define portMX_BIT ( 0x01000000 ) /* Allow access to DSP instructions. */
+#define portCU1_BIT ( 0x20000000 ) /* enable CP1 for parts with hardware. */
+#define portFR_BIT ( 0x04000000 ) /* Enable 64 bit floating point registers. */
/* Bits within the CAUSE register. */
#define portCORE_SW_0 ( 0x00000100 )
@@ -100,7 +102,16 @@
/* The EXL bit is set to ensure interrupts do not occur while the context of
the first task is being restored. */
-#define portINITIAL_SR ( portIE_BIT | portEXL_BIT | portMX_BIT )
+#if ( __mips_hard_float == 1 )
+ #define portINITIAL_SR ( portIE_BIT | portEXL_BIT | portMX_BIT | portFR_BIT | portCU1_BIT )
+#else
+ #define portINITIAL_SR ( portIE_BIT | portEXL_BIT | portMX_BIT )
+#endif
+
+/* The initial value to store into the FPU status and control register. This is
+ only used on parts that support a hardware FPU. */
+#define portINITIAL_FPSCR (0x1000000) /* High perf on denormal ops */
+
/*
By default port.c generates its tick interrupt from TIMER1. The user can
@@ -184,6 +195,12 @@ StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
the callers stack, as some functions seem to want to do this. */
const StackType_t * const xISRStackTop = &( xISRStack[ configISR_STACK_SIZE - 7 ] );
+/* Saved as part of the task context. Set to pdFALSE if the task does not
+ require an FPU context. */
+#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+ uint32_t ulTaskHasFPUContext = 0;
+#endif
+
/*-----------------------------------------------------------*/
/*
@@ -191,7 +208,8 @@ const StackType_t * const xISRStackTop = &( xISRStack[ configISR_STACK_SIZE - 7
*/
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
- /* Ensure byte alignment is maintained when leaving this function. */
+ /* Ensure 8 byte alignment is maintained when leaving this function. */
+ pxTopOfStack--;
pxTopOfStack--;
*pxTopOfStack = (StackType_t) 0xDEADBEEF;
@@ -207,10 +225,10 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
pxTopOfStack--;
*pxTopOfStack = (StackType_t) pxCode; /* CP0_EPC */
- pxTopOfStack -= 7; /* Includes space for AC1 - AC3. */
-
- *pxTopOfStack = (StackType_t) 0x00000000; /* DSPControl */
pxTopOfStack--;
+
+ *pxTopOfStack = (StackType_t) 0x00000000; /* DSPControl */
+ pxTopOfStack -= 7; /* Includes space for AC1 - AC3. */
*pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS; /* ra */
pxTopOfStack -= 15;
@@ -218,6 +236,8 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
*pxTopOfStack = (StackType_t) pvParameters; /* Parameters to pass in. */
pxTopOfStack -= 15;
+ *pxTopOfStack = (StackType_t) pdFALSE; /*by default disable FPU context save on parts with FPU */
+
return pxTopOfStack;
}
/*-----------------------------------------------------------*/
@@ -361,6 +381,27 @@ void vPortClearInterruptMaskFromISR( UBaseType_t uxSavedStatusRegister )
}
/*-----------------------------------------------------------*/
+#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+
+ void vPortTaskUsesFPU(void)
+ {
+ extern void vPortInitialiseFPSCR( uint32_t uxFPSCRInit );
+
+ portENTER_CRITICAL();
+
+ /* Initialise the floating point status register. */
+ vPortInitialiseFPSCR(portINITIAL_FPSCR);
+
+ /* A task is registering the fact that it needs a FPU context. Set the
+ FPU flag (saved as part of the task context). */
+ ulTaskHasFPUContext = pdTRUE;
+
+ portEXIT_CRITICAL();
+ }
+
+#endif /* __mips_hard_float == 1 */
+
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/MPLAB/PIC32MZ/port_asm.S b/FreeRTOS/Source/portable/MPLAB/PIC32MZ/port_asm.S
index 05da9974c..c6bf4a326 100644
--- a/FreeRTOS/Source/portable/MPLAB/PIC32MZ/port_asm.S
+++ b/FreeRTOS/Source/portable/MPLAB/PIC32MZ/port_asm.S
@@ -77,10 +77,12 @@
.extern vTaskSwitchContext
.extern vPortIncrementTick
.extern xISRStackTop
+ .extern ulTaskHasFPUContext
.global vPortStartFirstTask
.global vPortYieldISR
.global vPortTickInterruptHandler
+ .global vPortInitialiseFPSCR
/******************************************************************/
@@ -189,228 +191,621 @@ vPortStartFirstTask:
.ent vPortYieldISR
vPortYieldISR:
- /* Make room for the context. First save the current status so it can be
- manipulated, and the cause and EPC registers so thier original values are
- captured. */
- addiu sp, sp, -portCONTEXT_SIZE
- mfc0 k1, _CP0_STATUS
+ #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+ /* Code sequence for FPU support, the context save requires advance
+ knowledge of the stack frame size and if the current task actually uses the
+ FPU. */
- /* Also save s6 and s5 so they can be used. Any nesting interrupts should
- maintain the values of these registers across the ISR. */
- sw s6, 44(sp)
- sw s5, 40(sp)
- sw k1, portSTATUS_STACK_LOCATION(sp)
+ /* Make room for the context. First save the current status so it can be
+ manipulated, and the cause and EPC registers so their original values are
+ captured. */
+ la k0, ulTaskHasFPUContext
+ lw k0, 0(k0)
+ beq k0, zero, 1f
+ addiu sp, sp, -portCONTEXT_SIZE /* always reserve space for the context. */
+ addiu sp, sp, -portFPU_CONTEXT_SIZE /* reserve additional space for the FPU context. */
+ 1:
+ mfc0 k1, _CP0_STATUS
- /* Prepare to re-enabled interrupts above the kernel priority. */
- ins k1, zero, 10, 7 /* Clear IPL bits 0:6. */
- ins k1, zero, 18, 1 /* Clear IPL bit 7. It would be an error here if this bit were set anyway. */
- ori k1, k1, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 )
- ins k1, zero, 1, 4 /* Clear EXL, ERL and UM. */
+ /* Also save s6 and s5 so they can be used. Any nesting interrupts should
+ maintain the values of these registers across the ISR. */
+ sw s6, 44(sp)
+ sw s5, 40(sp)
+ sw k1, portSTATUS_STACK_LOCATION(sp)
+ sw k0, portTASK_HAS_FPU_STACK_LOCATION(sp)
- /* s5 is used as the frame pointer. */
- add s5, zero, sp
+ /* Prepare to re-enabled interrupts above the kernel priority. */
+ ins k1, zero, 10, 7 /* Clear IPL bits 0:6. */
+ ins k1, zero, 18, 1 /* Clear IPL bit 7. It would be an error here if this bit were set anyway. */
+ ori k1, k1, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 )
+ ins k1, zero, 1, 4 /* Clear EXL, ERL and UM. */
- /* Swap to the system stack. This is not conditional on the nesting
- count as this interrupt is always the lowest priority and therefore
- the nesting is always 0. */
- la sp, xISRStackTop
- lw sp, (sp)
+ /* s5 is used as the frame pointer. */
+ add s5, zero, sp
- /* Set the nesting count. */
- la k0, uxInterruptNesting
- addiu s6, zero, 1
- sw s6, 0(k0)
+ /* Swap to the system stack. This is not conditional on the nesting
+ count as this interrupt is always the lowest priority and therefore
+ the nesting is always 0. */
+ la sp, xISRStackTop
+ lw sp, (sp)
- /* s6 holds the EPC value, this is saved with the rest of the context
- after interrupts are enabled. */
- mfc0 s6, _CP0_EPC
+ /* Set the nesting count. */
+ la k0, uxInterruptNesting
+ addiu s6, zero, 1
+ sw s6, 0(k0)
- /* Re-enable interrupts above configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- mtc0 k1, _CP0_STATUS
+ /* s6 holds the EPC value, this is saved with the rest of the context
+ after interrupts are enabled. */
+ mfc0 s6, _CP0_EPC
- /* Save the context into the space just created. s6 is saved again
- here as it now contains the EPC value. */
- sw ra, 120(s5)
- sw s8, 116(s5)
- sw t9, 112(s5)
- sw t8, 108(s5)
- sw t7, 104(s5)
- sw t6, 100(s5)
- sw t5, 96(s5)
- sw t4, 92(s5)
- sw t3, 88(s5)
- sw t2, 84(s5)
- sw t1, 80(s5)
- sw t0, 76(s5)
- sw a3, 72(s5)
- sw a2, 68(s5)
- sw a1, 64(s5)
- sw a0, 60(s5)
- sw v1, 56(s5)
- sw v0, 52(s5)
- sw s7, 48(s5)
- sw s6, portEPC_STACK_LOCATION(s5)
- /* s5 and s6 has already been saved. */
- sw s4, 36(s5)
- sw s3, 32(s5)
- sw s2, 28(s5)
- sw s1, 24(s5)
- sw s0, 20(s5)
- sw $1, 16(s5)
+ /* Re-enable interrupts above configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ mtc0 k1, _CP0_STATUS
- /* s7 is used as a scratch register as this should always be saved across
- nesting interrupts. */
+ /* Save the context into the space just created. s6 is saved again
+ here as it now contains the EPC value. */
+ sw ra, 120(s5)
+ sw s8, 116(s5)
+ sw t9, 112(s5)
+ sw t8, 108(s5)
+ sw t7, 104(s5)
+ sw t6, 100(s5)
+ sw t5, 96(s5)
+ sw t4, 92(s5)
+ sw t3, 88(s5)
+ sw t2, 84(s5)
+ sw t1, 80(s5)
+ sw t0, 76(s5)
+ sw a3, 72(s5)
+ sw a2, 68(s5)
+ sw a1, 64(s5)
+ sw a0, 60(s5)
+ sw v1, 56(s5)
+ sw v0, 52(s5)
+ sw s7, 48(s5)
+ sw s6, portEPC_STACK_LOCATION(s5)
+ /* s5 and s6 has already been saved. */
+ sw s4, 36(s5)
+ sw s3, 32(s5)
+ sw s2, 28(s5)
+ sw s1, 24(s5)
+ sw s0, 20(s5)
+ sw $1, 16(s5)
- /* Save the AC0, AC1, AC2 and AC3. */
- mfhi s7, $ac1
- sw s7, 128(s5)
- mflo s7, $ac1
- sw s7, 124(s5)
+ /* s7 is used as a scratch register as this should always be saved across
+ nesting interrupts. */
- mfhi s7, $ac2
- sw s7, 136(s5)
- mflo s7, $ac2
- sw s7, 132(s5)
+ /* Save the AC0, AC1, AC2 and AC3. */
+ mfhi s7, $ac1
+ sw s7, 128(s5)
+ mflo s7, $ac1
+ sw s7, 124(s5)
- mfhi s7, $ac3
- sw s7, 144(s5)
- mflo s7, $ac3
- sw s7, 140(s5)
+ mfhi s7, $ac2
+ sw s7, 136(s5)
+ mflo s7, $ac2
+ sw s7, 132(s5)
- rddsp s7
- sw s7, 148(s5)
+ mfhi s7, $ac3
+ sw s7, 144(s5)
+ mflo s7, $ac3
+ sw s7, 140(s5)
- mfhi s7, $ac0
- sw s7, 12(s5)
- mflo s7, $ac0
- sw s7, 8(s5)
+ rddsp s7
+ sw s7, 148(s5)
- /* Save the stack pointer to the task. */
- la s7, pxCurrentTCB
- lw s7, (s7)
- sw s5, (s7)
+ mfhi s7, $ac0
+ sw s7, 12(s5)
+ mflo s7, $ac0
+ sw s7, 8(s5)
- /* Set the interrupt mask to the max priority that can use the API. The
- yield handler will only be called at configKERNEL_INTERRUPT_PRIORITY which
- is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only ever
- raise the IPL value and never lower it. */
- di
- ehb
- mfc0 s7, _CP0_STATUS
- ins s7, zero, 10, 7
- ins s7, zero, 18, 1
- ori s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1
+ /* Test if FPU context save is required. */
+ lw s7, portTASK_HAS_FPU_STACK_LOCATION(s5)
+ beq s7, zero, 1f
+ nop
- /* This mtc0 re-enables interrupts, but only above
- configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- mtc0 s6, _CP0_STATUS
- ehb
+ /* Save the FPU registers above the normal context. */
+ portSAVE_FPU_REGS (portCONTEXT_SIZE + 8), s5
- /* Clear the software interrupt in the core. */
- mfc0 s6, _CP0_CAUSE
- ins s6, zero, 8, 1
- mtc0 s6, _CP0_CAUSE
- ehb
+ /* Save the FPU status register */
+ cfc1 s7, $f31
+ sw s7, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )(s5)
- /* Clear the interrupt in the interrupt controller. */
- la s6, IFS0CLR
- addiu s4, zero, 2
- sw s4, (s6)
+ 1:
+ /* Save the stack pointer to the task. */
+ la s7, pxCurrentTCB
+ lw s7, (s7)
+ sw s5, (s7)
- jal vTaskSwitchContext
- nop
+ /* Set the interrupt mask to the max priority that can use the API. The
+ yield handler will only be called at configKERNEL_INTERRUPT_PRIORITY which
+ is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only ever
+ raise the IPL value and never lower it. */
+ di
+ ehb
+ mfc0 s7, _CP0_STATUS
+ ins s7, zero, 10, 7
+ ins s7, zero, 18, 1
+ ori s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1
- /* Clear the interrupt mask again. The saved status value is still in s7. */
- mtc0 s7, _CP0_STATUS
- ehb
+ /* This mtc0 re-enables interrupts, but only above
+ configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ mtc0 s6, _CP0_STATUS
+ ehb
- /* Restore the stack pointer from the TCB. */
- la s0, pxCurrentTCB
- lw s0, (s0)
- lw s5, (s0)
+ /* Clear the software interrupt in the core. */
+ mfc0 s6, _CP0_CAUSE
+ ins s6, zero, 8, 1
+ mtc0 s6, _CP0_CAUSE
+ ehb
- /* Restore the rest of the context. */
- lw s0, 128(s5)
- mthi s0, $ac1
- lw s0, 124(s5)
- mtlo s0, $ac1
+ /* Clear the interrupt in the interrupt controller. */
+ la s6, IFS0CLR
+ addiu s4, zero, 2
+ sw s4, (s6)
- lw s0, 136(s5)
- mthi s0, $ac2
- lw s0, 132(s5)
- mtlo s0, $ac2
+ jal vTaskSwitchContext
+ nop
- lw s0, 144(s5)
- mthi s0, $ac3
- lw s0, 140(s5)
- mtlo s0, $ac3
+ /* Clear the interrupt mask again. The saved status value is still in s7. */
+ mtc0 s7, _CP0_STATUS
+ ehb
- lw s0, 148(s5)
- wrdsp s0
+ /* Restore the stack pointer from the TCB. */
+ la s0, pxCurrentTCB
+ lw s0, (s0)
+ lw s5, (s0)
- lw s0, 8(s5)
- mtlo s0, $ac0
- lw s0, 12(s5)
- mthi s0, $ac0
+ /* Test if the FPU context needs restoring. */
+ lw s0, portTASK_HAS_FPU_STACK_LOCATION(s5)
+ beq s0, zero, 1f
+ nop
- lw $1, 16(s5)
- lw s0, 20(s5)
- lw s1, 24(s5)
- lw s2, 28(s5)
- lw s3, 32(s5)
- lw s4, 36(s5)
+ /* Restore the FPU status register. */
+ lw s0, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )(s5)
+ ctc1 s0, $f31
- /* s5 is loaded later. */
- lw s6, 44(s5)
- lw s7, 48(s5)
- lw v0, 52(s5)
- lw v1, 56(s5)
- lw a0, 60(s5)
- lw a1, 64(s5)
- lw a2, 68(s5)
- lw a3, 72(s5)
- lw t0, 76(s5)
- lw t1, 80(s5)
- lw t2, 84(s5)
- lw t3, 88(s5)
- lw t4, 92(s5)
- lw t5, 96(s5)
- lw t6, 100(s5)
- lw t7, 104(s5)
- lw t8, 108(s5)
- lw t9, 112(s5)
- lw s8, 116(s5)
- lw ra, 120(s5)
+ /* Restore the FPU registers. */
+ portLOAD_FPU_REGS ( portCONTEXT_SIZE + 8 ), s5
- /* Protect access to the k registers, and others. */
- di
- ehb
+ 1:
+ /* Restore the rest of the context. */
+ lw s0, 128(s5)
+ mthi s0, $ac1
+ lw s0, 124(s5)
+ mtlo s0, $ac1
- /* Set nesting back to zero. As the lowest priority interrupt this
- interrupt cannot have nested. */
- la k0, uxInterruptNesting
- sw zero, 0(k0)
+ lw s0, 136(s5)
+ mthi s0, $ac2
+ lw s0, 132(s5)
+ mtlo s0, $ac2
- /* Switch back to use the real stack pointer. */
- add sp, zero, s5
+ lw s0, 144(s5)
+ mthi s0, $ac3
+ lw s0, 140(s5)
+ mtlo s0, $ac3
- /* Restore the real s5 value. */
- lw s5, 40(sp)
+ lw s0, 148(s5)
+ wrdsp s0
- /* Pop the status and epc values. */
- lw k1, portSTATUS_STACK_LOCATION(sp)
- lw k0, portEPC_STACK_LOCATION(sp)
+ lw s0, 8(s5)
+ mtlo s0, $ac0
+ lw s0, 12(s5)
+ mthi s0, $ac0
- /* Remove stack frame. */
- addiu sp, sp, portCONTEXT_SIZE
+ lw $1, 16(s5)
+ lw s0, 20(s5)
+ lw s1, 24(s5)
+ lw s2, 28(s5)
+ lw s3, 32(s5)
+ lw s4, 36(s5)
- mtc0 k1, _CP0_STATUS
- mtc0 k0, _CP0_EPC
+ /* s5 is loaded later. */
+ lw s6, 44(s5)
+ lw s7, 48(s5)
+ lw v0, 52(s5)
+ lw v1, 56(s5)
+ lw a0, 60(s5)
+ lw a1, 64(s5)
+ lw a2, 68(s5)
+ lw a3, 72(s5)
+ lw t0, 76(s5)
+ lw t1, 80(s5)
+ lw t2, 84(s5)
+ lw t3, 88(s5)
+ lw t4, 92(s5)
+ lw t5, 96(s5)
+ lw t6, 100(s5)
+ lw t7, 104(s5)
+ lw t8, 108(s5)
+ lw t9, 112(s5)
+ lw s8, 116(s5)
+ lw ra, 120(s5)
+
+ /* Protect access to the k registers, and others. */
+ di
+ ehb
+
+ /* Set nesting back to zero. As the lowest priority interrupt this
+ interrupt cannot have nested. */
+ la k0, uxInterruptNesting
+ sw zero, 0(k0)
+
+ /* Switch back to use the real stack pointer. */
+ add sp, zero, s5
+
+ /* Restore the real s5 value. */
+ lw s5, 40(sp)
+
+ /* Pop the FPU context value from the stack */
+ lw k0, portTASK_HAS_FPU_STACK_LOCATION(sp)
+ la k1, ulTaskHasFPUContext
+ sw k0, 0(k1)
+ beq k0, zero, 1f
+ nop
+
+ /* task has FPU context so adjust the stack frame after popping the
+ status and epc values. */
+ lw k1, portSTATUS_STACK_LOCATION(sp)
+ lw k0, portEPC_STACK_LOCATION(sp)
+ addiu sp, sp, portFPU_CONTEXT_SIZE
+ beq zero, zero, 2f
+ nop
+
+ 1:
+ /* Pop the status and epc values. */
+ lw k1, portSTATUS_STACK_LOCATION(sp)
+ lw k0, portEPC_STACK_LOCATION(sp)
+
+ 2:
+ /* Remove stack frame. */
+ addiu sp, sp, portCONTEXT_SIZE
+
+ #else
+ /* Code sequence for no FPU support, the context save requires advance
+ knowledge of the stack frame size when no FPU is being used */
+
+ /* Make room for the context. First save the current status so it can be
+ manipulated, and the cause and EPC registers so thier original values are
+ captured. */
+ addiu sp, sp, -portCONTEXT_SIZE
+ mfc0 k1, _CP0_STATUS
+
+ /* Also save s6 and s5 so they can be used. Any nesting interrupts should
+ maintain the values of these registers across the ISR. */
+ sw s6, 44(sp)
+ sw s5, 40(sp)
+ sw k1, portSTATUS_STACK_LOCATION(sp)
+
+ /* Prepare to re-enabled interrupts above the kernel priority. */
+ ins k1, zero, 10, 7 /* Clear IPL bits 0:6. */
+ ins k1, zero, 18, 1 /* Clear IPL bit 7. It would be an error here if this bit were set anyway. */
+ ori k1, k1, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 )
+ ins k1, zero, 1, 4 /* Clear EXL, ERL and UM. */
+
+ /* s5 is used as the frame pointer. */
+ add s5, zero, sp
+
+ /* Swap to the system stack. This is not conditional on the nesting
+ count as this interrupt is always the lowest priority and therefore
+ the nesting is always 0. */
+ la sp, xISRStackTop
+ lw sp, (sp)
+
+ /* Set the nesting count. */
+ la k0, uxInterruptNesting
+ addiu s6, zero, 1
+ sw s6, 0(k0)
+
+ /* s6 holds the EPC value, this is saved with the rest of the context
+ after interrupts are enabled. */
+ mfc0 s6, _CP0_EPC
+
+ /* Re-enable interrupts above configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ mtc0 k1, _CP0_STATUS
+
+ /* Save the context into the space just created. s6 is saved again
+ here as it now contains the EPC value. */
+ sw ra, 120(s5)
+ sw s8, 116(s5)
+ sw t9, 112(s5)
+ sw t8, 108(s5)
+ sw t7, 104(s5)
+ sw t6, 100(s5)
+ sw t5, 96(s5)
+ sw t4, 92(s5)
+ sw t3, 88(s5)
+ sw t2, 84(s5)
+ sw t1, 80(s5)
+ sw t0, 76(s5)
+ sw a3, 72(s5)
+ sw a2, 68(s5)
+ sw a1, 64(s5)
+ sw a0, 60(s5)
+ sw v1, 56(s5)
+ sw v0, 52(s5)
+ sw s7, 48(s5)
+ sw s6, portEPC_STACK_LOCATION(s5)
+ /* s5 and s6 has already been saved. */
+ sw s4, 36(s5)
+ sw s3, 32(s5)
+ sw s2, 28(s5)
+ sw s1, 24(s5)
+ sw s0, 20(s5)
+ sw $1, 16(s5)
+
+ /* s7 is used as a scratch register as this should always be saved across
+ nesting interrupts. */
+
+ /* Save the AC0, AC1, AC2 and AC3. */
+ mfhi s7, $ac1
+ sw s7, 128(s5)
+ mflo s7, $ac1
+ sw s7, 124(s5)
+
+ mfhi s7, $ac2
+ sw s7, 136(s5)
+ mflo s7, $ac2
+ sw s7, 132(s5)
+
+ mfhi s7, $ac3
+ sw s7, 144(s5)
+ mflo s7, $ac3
+ sw s7, 140(s5)
+
+ rddsp s7
+ sw s7, 148(s5)
+
+ mfhi s7, $ac0
+ sw s7, 12(s5)
+ mflo s7, $ac0
+ sw s7, 8(s5)
+
+ /* Save the stack pointer to the task. */
+ la s7, pxCurrentTCB
+ lw s7, (s7)
+ sw s5, (s7)
+
+ /* Set the interrupt mask to the max priority that can use the API. The
+ yield handler will only be called at configKERNEL_INTERRUPT_PRIORITY which
+ is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only ever
+ raise the IPL value and never lower it. */
+ di
+ ehb
+ mfc0 s7, _CP0_STATUS
+ ins s7, zero, 10, 7
+ ins s7, zero, 18, 1
+ ori s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1
+
+ /* This mtc0 re-enables interrupts, but only above
+ configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ mtc0 s6, _CP0_STATUS
+ ehb
+
+ /* Clear the software interrupt in the core. */
+ mfc0 s6, _CP0_CAUSE
+ ins s6, zero, 8, 1
+ mtc0 s6, _CP0_CAUSE
+ ehb
+
+ /* Clear the interrupt in the interrupt controller. */
+ la s6, IFS0CLR
+ addiu s4, zero, 2
+ sw s4, (s6)
+
+ jal vTaskSwitchContext
+ nop
+
+ /* Clear the interrupt mask again. The saved status value is still in s7. */
+ mtc0 s7, _CP0_STATUS
+ ehb
+
+ /* Restore the stack pointer from the TCB. */
+ la s0, pxCurrentTCB
+ lw s0, (s0)
+ lw s5, (s0)
+
+ /* Restore the rest of the context. */
+ lw s0, 128(s5)
+ mthi s0, $ac1
+ lw s0, 124(s5)
+ mtlo s0, $ac1
+
+ lw s0, 136(s5)
+ mthi s0, $ac2
+ lw s0, 132(s5)
+ mtlo s0, $ac2
+
+ lw s0, 144(s5)
+ mthi s0, $ac3
+ lw s0, 140(s5)
+ mtlo s0, $ac3
+
+ lw s0, 148(s5)
+ wrdsp s0
+
+ lw s0, 8(s5)
+ mtlo s0, $ac0
+ lw s0, 12(s5)
+ mthi s0, $ac0
+
+ lw $1, 16(s5)
+ lw s0, 20(s5)
+ lw s1, 24(s5)
+ lw s2, 28(s5)
+ lw s3, 32(s5)
+ lw s4, 36(s5)
+
+ /* s5 is loaded later. */
+ lw s6, 44(s5)
+ lw s7, 48(s5)
+ lw v0, 52(s5)
+ lw v1, 56(s5)
+ lw a0, 60(s5)
+ lw a1, 64(s5)
+ lw a2, 68(s5)
+ lw a3, 72(s5)
+ lw t0, 76(s5)
+ lw t1, 80(s5)
+ lw t2, 84(s5)
+ lw t3, 88(s5)
+ lw t4, 92(s5)
+ lw t5, 96(s5)
+ lw t6, 100(s5)
+ lw t7, 104(s5)
+ lw t8, 108(s5)
+ lw t9, 112(s5)
+ lw s8, 116(s5)
+ lw ra, 120(s5)
+
+ /* Protect access to the k registers, and others. */
+ di
+ ehb
+
+ /* Set nesting back to zero. As the lowest priority interrupt this
+ interrupt cannot have nested. */
+ la k0, uxInterruptNesting
+ sw zero, 0(k0)
+
+ /* Switch back to use the real stack pointer. */
+ add sp, zero, s5
+
+ /* Restore the real s5 value. */
+ lw s5, 40(sp)
+
+ /* Pop the status and epc values. */
+ lw k1, portSTATUS_STACK_LOCATION(sp)
+ lw k0, portEPC_STACK_LOCATION(sp)
+
+ /* Remove stack frame. */
+ addiu sp, sp, portCONTEXT_SIZE
+
+ #endif /* ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
+
+ /* Restore the status and EPC registers and return */
+ mtc0 k1, _CP0_STATUS
+ mtc0 k0, _CP0_EPC
ehb
eret
nop
- .end vPortYieldISR
+ .end vPortYieldISR
+
+/******************************************************************/
+
+#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+
+ .macro portFPUSetAndInc reg, dest
+ mtc1 \reg, \dest
+ cvt.d.w \dest, \dest
+ addiu \reg, \reg, 1
+ .endm
+
+ .set noreorder
+ .set noat
+ .section .text, code
+ .ent vPortInitialiseFPSCR
+
+vPortInitialiseFPSCR:
+
+ /* Initialize the floating point status register in CP1. The initial
+ value is passed in a0. */
+ ctc1 a0, $f31
+
+ /* Clear the FPU registers */
+ addiu a0, zero, 0x0000
+ portFPUSetAndInc a0, $f0
+ portFPUSetAndInc a0, $f1
+ portFPUSetAndInc a0, $f2
+ portFPUSetAndInc a0, $f3
+ portFPUSetAndInc a0, $f4
+ portFPUSetAndInc a0, $f5
+ portFPUSetAndInc a0, $f6
+ portFPUSetAndInc a0, $f7
+ portFPUSetAndInc a0, $f8
+ portFPUSetAndInc a0, $f9
+ portFPUSetAndInc a0, $f10
+ portFPUSetAndInc a0, $f11
+ portFPUSetAndInc a0, $f12
+ portFPUSetAndInc a0, $f13
+ portFPUSetAndInc a0, $f14
+ portFPUSetAndInc a0, $f15
+ portFPUSetAndInc a0, $f16
+ portFPUSetAndInc a0, $f17
+ portFPUSetAndInc a0, $f18
+ portFPUSetAndInc a0, $f19
+ portFPUSetAndInc a0, $f20
+ portFPUSetAndInc a0, $f21
+ portFPUSetAndInc a0, $f22
+ portFPUSetAndInc a0, $f23
+ portFPUSetAndInc a0, $f24
+ portFPUSetAndInc a0, $f25
+ portFPUSetAndInc a0, $f26
+ portFPUSetAndInc a0, $f27
+ portFPUSetAndInc a0, $f28
+ portFPUSetAndInc a0, $f29
+ portFPUSetAndInc a0, $f30
+ portFPUSetAndInc a0, $f31
+
+ jr ra
+ nop
+
+ .end vPortInitialiseFPSCR
+
+#endif /* ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
+
+#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+
+ /**********************************************************************/
+ /* Test read back */
+ /* a0 = address to store registers */
+
+ .set noreorder
+ .set noat
+ .section .text, code
+ .ent vPortFPUReadback
+ .global vPortFPUReadback
+
+vPortFPUReadback:
+ sdc1 $f0, 0(a0)
+ sdc1 $f1, 8(a0)
+ sdc1 $f2, 16(a0)
+ sdc1 $f3, 24(a0)
+ sdc1 $f4, 32(a0)
+ sdc1 $f5, 40(a0)
+ sdc1 $f6, 48(a0)
+ sdc1 $f7, 56(a0)
+ sdc1 $f8, 64(a0)
+ sdc1 $f9, 72(a0)
+ sdc1 $f10, 80(a0)
+ sdc1 $f11, 88(a0)
+ sdc1 $f12, 96(a0)
+ sdc1 $f13, 104(a0)
+ sdc1 $f14, 112(a0)
+ sdc1 $f15, 120(a0)
+ sdc1 $f16, 128(a0)
+ sdc1 $f17, 136(a0)
+ sdc1 $f18, 144(a0)
+ sdc1 $f19, 152(a0)
+ sdc1 $f20, 160(a0)
+ sdc1 $f21, 168(a0)
+ sdc1 $f22, 176(a0)
+ sdc1 $f23, 184(a0)
+ sdc1 $f24, 192(a0)
+ sdc1 $f25, 200(a0)
+ sdc1 $f26, 208(a0)
+ sdc1 $f27, 216(a0)
+ sdc1 $f28, 224(a0)
+ sdc1 $f29, 232(a0)
+ sdc1 $f30, 240(a0)
+ sdc1 $f31, 248(a0)
+
+ jr ra
+ nop
+
+ .end vPortFPUReadback
+
+#endif /* ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
+
diff --git a/FreeRTOS/Source/portable/MPLAB/PIC32MZ/portmacro.h b/FreeRTOS/Source/portable/MPLAB/PIC32MZ/portmacro.h
index 7b5034fbf..e400070bc 100644
--- a/FreeRTOS/Source/portable/MPLAB/PIC32MZ/portmacro.h
+++ b/FreeRTOS/Source/portable/MPLAB/PIC32MZ/portmacro.h
@@ -183,6 +183,15 @@ extern void vPortClearInterruptMaskFromISR( UBaseType_t );
#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
+#if ( __mips_hard_float == 0 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+ #error configUSE_TASK_FPU_SUPPORT can only be set to 1 when the part supports a hardware FPU module.
+#endif
+
+#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+ void vPortTaskUsesFPU( void );
+ #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+#endif
+
#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
#endif
diff --git a/FreeRTOS/Source/timers.c b/FreeRTOS/Source/timers.c
index 9ede09f61..663b60af0 100644
--- a/FreeRTOS/Source/timers.c
+++ b/FreeRTOS/Source/timers.c
@@ -233,7 +233,7 @@ static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) PRIV
* If a timer has expired, process it. Otherwise, block the timer service task
* until either a timer does expire or a command is received.
*/
-static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, const BaseType_t xListWasEmpty ) PRIVILEGED_FUNCTION;
+static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty ) PRIVILEGED_FUNCTION;
/*-----------------------------------------------------------*/
@@ -442,7 +442,7 @@ BaseType_t xListWasEmpty;
}
/*-----------------------------------------------------------*/
-static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, const BaseType_t xListWasEmpty )
+static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty )
{
TickType_t xTimeNow;
BaseType_t xTimerListsWereSwitched;
@@ -471,6 +471,13 @@ BaseType_t xTimerListsWereSwitched;
received - whichever comes first. The following line cannot
be reached unless xNextExpireTime > xTimeNow, except in the
case when the current timer list is empty. */
+ if( xListWasEmpty != pdFALSE )
+ {
+ /* The current timer list is empty - is the overflow list
+ also empty? */
+ xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );
+ }
+
vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );
if( xTaskResumeAll() == pdFALSE )